2022-05-14 00:21:06

by Zhou Yanjie

[permalink] [raw]
Subject: [PATCH 0/3] Refresh device tree and defconfig for Ingenic SoCs and boards.

1.Add PWM node for X1830 SoC from Ingenic.
2.Add SSI nodes for X1000 SoC and X1830 SoC from Ingenic.
3.Refresh SSI related nodes in CU1000-Neo and CU1830-Neo.
4.The X1830 SoC used by the CU1830-Neo and the X1000 SoC
used by the CU1000-Neo are both single-core processors,
therefore the "OST_CLK_PERCPU_TIMER" ABI should not be
used in the OST nodes of the CU1830-Neo and CU1000-Neo,
it is just a coincidence that there is no problem now.
So replace the misused "OST_CLK_PERCPU_TIMER" ABI with
the correct "OST_CLK_EVENT_TIMER" ABI.
5.Refresh the defconfig files of the CU1000-Neo board and
the CU1830-Neo board, remove the selection of SPI-GPIO,
and add the selection of SSI.

周琰杰 (Zhou Yanjie) (3):
MIPS: Ingenic: Add PWM nodes for X1830.
MIPS: Ingenic: Refresh device tree for Ingenic SoCs and boards.
MIPS: Ingenic: Refresh defconfig for CU1000-Neo and CU1830-Neo.

arch/mips/boot/dts/ingenic/cu1000-neo.dts | 77 ++++++++++++++++---------------
arch/mips/boot/dts/ingenic/cu1830-neo.dts | 76 +++++++++++++++---------------
arch/mips/boot/dts/ingenic/x1000.dtsi | 20 ++++++++
arch/mips/boot/dts/ingenic/x1830.dtsi | 53 +++++++++++++++++++++
arch/mips/configs/cu1000-neo_defconfig | 2 +-
arch/mips/configs/cu1830-neo_defconfig | 2 +-
6 files changed, 154 insertions(+), 76 deletions(-)

--
2.7.4



2022-05-14 00:37:32

by Zhou Yanjie

[permalink] [raw]
Subject: [PATCH 2/3] MIPS: Ingenic: Refresh device tree for Ingenic SoCs and boards.

1.Add SSI nodes for X1000 SoC and X1830 SoC from Ingenic.
2.Refresh SSI related nodes in CU1000-Neo and CU1830-Neo.
3.The X1830 SoC used by the CU1830-Neo and the X1000 SoC
used by the CU1000-Neo are both single-core processors,
therefore the "OST_CLK_PERCPU_TIMER" ABI should not be
used in the OST nodes of the CU1830-Neo and CU1000-Neo,
it is just a coincidence that there is no problem now.
So replace the misused "OST_CLK_PERCPU_TIMER" ABI with
the correct "OST_CLK_EVENT_TIMER" ABI.

Signed-off-by: 周琰杰 (Zhou Yanjie) <[email protected]>
---
arch/mips/boot/dts/ingenic/cu1000-neo.dts | 77 ++++++++++++++++---------------
arch/mips/boot/dts/ingenic/cu1830-neo.dts | 76 +++++++++++++++---------------
arch/mips/boot/dts/ingenic/x1000.dtsi | 20 ++++++++
arch/mips/boot/dts/ingenic/x1830.dtsi | 39 ++++++++++++++++
4 files changed, 138 insertions(+), 74 deletions(-)

diff --git a/arch/mips/boot/dts/ingenic/cu1000-neo.dts b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
index 9c67b4f..b44d3b1 100644
--- a/arch/mips/boot/dts/ingenic/cu1000-neo.dts
+++ b/arch/mips/boot/dts/ingenic/cu1000-neo.dts
@@ -31,42 +31,6 @@
};
};

- ssi: spi-gpio {
- compatible = "spi-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
- num-chipselects = <1>;
-
- mosi-gpios = <&gpd 2 GPIO_ACTIVE_HIGH>;
- miso-gpios = <&gpd 3 GPIO_ACTIVE_HIGH>;
- sck-gpios = <&gpd 0 GPIO_ACTIVE_HIGH>;
- cs-gpios = <&gpd 1 GPIO_ACTIVE_HIGH>;
-
- status = "okay";
-
- spi-max-frequency = <50000000>;
-
- sc16is752: expander@0 {
- compatible = "nxp,sc16is752";
- reg = <0>; /* CE0 */
- spi-max-frequency = <4000000>;
-
- clocks = <&exclk_sc16is752>;
-
- interrupt-parent = <&gpc>;
- interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- exclk_sc16is752: sc16is752 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <48000000>;
- };
- };
- };
-
wlan_pwrseq: msc1-pwrseq {
compatible = "mmc-pwrseq-simple";

@@ -90,7 +54,7 @@

&ost {
/* 1500 kHz for the system timer and clocksource */
- assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
+ assigned-clocks = <&ost OST_CLK_EVENT_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
assigned-clock-rates = <1500000>, <1500000>;
};

@@ -101,6 +65,39 @@
pinctrl-0 = <&pins_uart2>;
};

+&ssi {
+ status = "okay";
+
+ num-cs = <2>;
+ cs-gpios = <0>, <&gpc 20 GPIO_ACTIVE_LOW>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_ssi>;
+
+ sc16is752: expander@0 {
+ compatible = "nxp,sc16is752";
+ reg = <0>; /* CE0 */
+
+ spi-rx-bus-width = <1>;
+ spi-tx-bus-width = <1>;
+ spi-max-frequency = <4000000>;
+
+ clocks = <&exclk_sc16is752>;
+
+ interrupt-parent = <&gpc>;
+ interrupts = <6 IRQ_TYPE_EDGE_FALLING>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ exclk_sc16is752: sc16is752 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+ };
+};
+
&i2c0 {
status = "okay";

@@ -225,6 +222,12 @@
bias-pull-up;
};

+ pins_ssi: ssi {
+ function = "ssi";
+ groups = "ssi-dt-d", "ssi-dr-d", "ssi-clk-d", "ssi-ce0-d";
+ bias-disable;
+ };
+
pins_i2c0: i2c0 {
function = "i2c0";
groups = "i2c0-data";
diff --git a/arch/mips/boot/dts/ingenic/cu1830-neo.dts b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
index 0727bc9..461efba 100644
--- a/arch/mips/boot/dts/ingenic/cu1830-neo.dts
+++ b/arch/mips/boot/dts/ingenic/cu1830-neo.dts
@@ -31,42 +31,6 @@
};
};

- ssi0: spi-gpio {
- compatible = "spi-gpio";
- #address-cells = <1>;
- #size-cells = <0>;
- num-chipselects = <1>;
-
- mosi-gpios = <&gpc 12 GPIO_ACTIVE_HIGH>;
- miso-gpios = <&gpc 11 GPIO_ACTIVE_HIGH>;
- sck-gpios = <&gpc 15 GPIO_ACTIVE_HIGH>;
- cs-gpios = <&gpc 16 GPIO_ACTIVE_HIGH>;
-
- status = "okay";
-
- spi-max-frequency = <50000000>;
-
- sc16is752: expander@0 {
- compatible = "nxp,sc16is752";
- reg = <0>; /* CE0 */
- spi-max-frequency = <4000000>;
-
- clocks = <&exclk_sc16is752>;
-
- interrupt-parent = <&gpb>;
- interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
-
- gpio-controller;
- #gpio-cells = <2>;
-
- exclk_sc16is752: sc16is752 {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <48000000>;
- };
- };
- };
-
wlan_pwrseq: msc1-pwrseq {
compatible = "mmc-pwrseq-simple";

@@ -90,7 +54,7 @@

&ost {
/* 1500 kHz for the system timer and clocksource */
- assigned-clocks = <&ost OST_CLK_PERCPU_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
+ assigned-clocks = <&ost OST_CLK_EVENT_TIMER>, <&ost OST_CLK_GLOBAL_TIMER>;
assigned-clock-rates = <1500000>, <1500000>;
};

@@ -101,6 +65,38 @@
pinctrl-0 = <&pins_uart1>;
};

+&ssi0 {
+ status = "okay";
+
+ num-cs = <2>;
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_ssi0>;
+
+ sc16is752: expander@0 {
+ compatible = "nxp,sc16is752";
+ reg = <0>; /* CE0 */
+
+ spi-rx-bus-width = <1>;
+ spi-tx-bus-width = <1>;
+ spi-max-frequency = <4000000>;
+
+ clocks = <&exclk_sc16is752>;
+
+ interrupt-parent = <&gpb>;
+ interrupts = <18 IRQ_TYPE_EDGE_FALLING>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ exclk_sc16is752: sc16is752 {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+ };
+};
+
&i2c0 {
status = "okay";

@@ -229,6 +225,12 @@
bias-pull-up;
};

+ pins_ssi0: ssi0 {
+ function = "ssi0";
+ groups = "ssi0-dt", "ssi0-dr", "ssi0-clk", "ssi0-ce0", "ssi0-ce1";
+ bias-disable;
+ };
+
pins_i2c0: i2c0 {
function = "i2c0";
groups = "i2c0-data";
diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi b/arch/mips/boot/dts/ingenic/x1000.dtsi
index 591692d..958a5ef 100644
--- a/arch/mips/boot/dts/ingenic/x1000.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
@@ -259,6 +259,25 @@
status = "disabled";
};

+ ssi: spi@10043000 {
+ compatible = "ingenic,x1000-spi";
+ reg = <0x10043000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <8>;
+
+ clocks = <&cgu X1000_CLK_SSI>;
+ clock-names = "spi";
+
+ dmas = <&pdma X1000_DMA_SSI0_RX 0xffffffff>,
+ <&pdma X1000_DMA_SSI0_TX 0xffffffff>;
+ dma-names = "rx", "tx";
+
+ status = "disabled";
+ };
+
i2c0: i2c-controller@10050000 {
compatible = "ingenic,x1000-i2c";
reg = <0x10050000 0x1000>;
@@ -304,6 +323,7 @@
pdma: dma-controller@13420000 {
compatible = "ingenic,x1000-dma";
reg = <0x13420000 0x400>, <0x13421000 0x40>;
+
#dma-cells = <2>;

interrupt-parent = <&intc>;
diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi
index ffe6073..231c72a 100644
--- a/arch/mips/boot/dts/ingenic/x1830.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
@@ -241,6 +241,44 @@
status = "disabled";
};

+ ssi0: spi@10043000 {
+ compatible = "ingenic,x1830-spi", "ingenic,x1000-spi";
+ reg = <0x10043000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <9>;
+
+ clocks = <&cgu X1830_CLK_SSI0>;
+ clock-names = "spi";
+
+ dmas = <&pdma X1830_DMA_SSI0_RX 0xffffffff>,
+ <&pdma X1830_DMA_SSI0_TX 0xffffffff>;
+ dma-names = "rx", "tx";
+
+ status = "disabled";
+ };
+
+ ssi1: spi@10044000 {
+ compatible = "ingenic,x1830-spi", "ingenic,x1000-spi";
+ reg = <0x10044000 0x20>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupt-parent = <&intc>;
+ interrupts = <8>;
+
+ clocks = <&cgu X1830_CLK_SSI1>;
+ clock-names = "spi";
+
+ dmas = <&pdma X1830_DMA_SSI1_RX 0xffffffff>,
+ <&pdma X1830_DMA_SSI1_TX 0xffffffff>;
+ dma-names = "rx", "tx";
+
+ status = "disabled";
+ };
+
i2c0: i2c-controller@10050000 {
compatible = "ingenic,x1830-i2c", "ingenic,x1000-i2c";
reg = <0x10050000 0x1000>;
@@ -295,6 +333,7 @@
pdma: dma-controller@13420000 {
compatible = "ingenic,x1830-dma";
reg = <0x13420000 0x400>, <0x13421000 0x40>;
+
#dma-cells = <2>;

interrupt-parent = <&intc>;
--
2.7.4


2022-05-14 01:31:25

by Zhou Yanjie

[permalink] [raw]
Subject: [PATCH 1/3] MIPS: Ingenic: Add PWM nodes for X1830.

Add PWM node for X1830 SoC from Ingenic.

Signed-off-by: 周琰杰 (Zhou Yanjie) <[email protected]>
---
arch/mips/boot/dts/ingenic/x1830.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)

diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi b/arch/mips/boot/dts/ingenic/x1830.dtsi
index 5aa805a..ffe6073 100644
--- a/arch/mips/boot/dts/ingenic/x1830.dtsi
+++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
@@ -121,6 +121,20 @@
clocks = <&tcu TCU_CLK_WDT>;
clock-names = "wdt";
};
+
+ pwm: pwm@40 {
+ compatible = "ingenic,x1830-pwm", "ingenic,jz4740-pwm";
+ reg = <0x40 0x80>;
+
+ #pwm-cells = <3>;
+
+ clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>,
+ <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>,
+ <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>,
+ <&tcu TCU_CLK_TIMER6>, <&tcu TCU_CLK_TIMER7>;
+ clock-names = "timer0", "timer1", "timer2", "timer3",
+ "timer4", "timer5", "timer6", "timer7";
+ };
};

rtc: rtc@10003000 {
--
2.7.4


2022-05-14 02:30:11

by Zhou Yanjie

[permalink] [raw]
Subject: [PATCH 3/3] MIPS: Ingenic: Refresh defconfig for CU1000-Neo and CU1830-Neo.

Refresh the defconfig files of CU1000-Neo board and CU1830-Neo board,
remove the selection of SPI-GPIO, and add the selection of SSI.

Signed-off-by: 周琰杰 (Zhou Yanjie) <[email protected]>
---
arch/mips/configs/cu1000-neo_defconfig | 2 +-
arch/mips/configs/cu1830-neo_defconfig | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/mips/configs/cu1000-neo_defconfig b/arch/mips/configs/cu1000-neo_defconfig
index 9d75f5b..5bd55eb 100644
--- a/arch/mips/configs/cu1000-neo_defconfig
+++ b/arch/mips/configs/cu1000-neo_defconfig
@@ -61,7 +61,7 @@ CONFIG_SERIAL_SC16IS7XX_SPI=y
CONFIG_I2C=y
CONFIG_I2C_JZ4780=y
CONFIG_SPI=y
-CONFIG_SPI_GPIO=y
+CONFIG_SPI_INGENIC=y
CONFIG_GPIO_SYSFS=y
CONFIG_SENSORS_ADS7828=m
CONFIG_WATCHDOG=y
diff --git a/arch/mips/configs/cu1830-neo_defconfig b/arch/mips/configs/cu1830-neo_defconfig
index 29decd00..cc69688 100644
--- a/arch/mips/configs/cu1830-neo_defconfig
+++ b/arch/mips/configs/cu1830-neo_defconfig
@@ -64,7 +64,7 @@ CONFIG_SERIAL_SC16IS7XX_SPI=y
CONFIG_I2C=y
CONFIG_I2C_JZ4780=y
CONFIG_SPI=y
-CONFIG_SPI_GPIO=y
+CONFIG_SPI_INGENIC=y
CONFIG_GPIO_SYSFS=y
CONFIG_SENSORS_ADS7828=m
CONFIG_WATCHDOG=y
--
2.7.4


2022-05-23 09:37:37

by Thomas Bogendoerfer

[permalink] [raw]
Subject: Re: [PATCH 0/3] Refresh device tree and defconfig for Ingenic SoCs and boards.

On Fri, May 13, 2022 at 03:33:38AM +0800, 周琰杰 (Zhou Yanjie) wrote:
> 1.Add PWM node for X1830 SoC from Ingenic.
> 2.Add SSI nodes for X1000 SoC and X1830 SoC from Ingenic.
> 3.Refresh SSI related nodes in CU1000-Neo and CU1830-Neo.
> 4.The X1830 SoC used by the CU1830-Neo and the X1000 SoC
> used by the CU1000-Neo are both single-core processors,
> therefore the "OST_CLK_PERCPU_TIMER" ABI should not be
> used in the OST nodes of the CU1830-Neo and CU1000-Neo,
> it is just a coincidence that there is no problem now.
> So replace the misused "OST_CLK_PERCPU_TIMER" ABI with
> the correct "OST_CLK_EVENT_TIMER" ABI.
> 5.Refresh the defconfig files of the CU1000-Neo board and
> the CU1830-Neo board, remove the selection of SPI-GPIO,
> and add the selection of SSI.
>
> 周琰杰 (Zhou Yanjie) (3):
> MIPS: Ingenic: Add PWM nodes for X1830.
> MIPS: Ingenic: Refresh device tree for Ingenic SoCs and boards.
> MIPS: Ingenic: Refresh defconfig for CU1000-Neo and CU1830-Neo.
>
> arch/mips/boot/dts/ingenic/cu1000-neo.dts | 77 ++++++++++++++++---------------
> arch/mips/boot/dts/ingenic/cu1830-neo.dts | 76 +++++++++++++++---------------
> arch/mips/boot/dts/ingenic/x1000.dtsi | 20 ++++++++
> arch/mips/boot/dts/ingenic/x1830.dtsi | 53 +++++++++++++++++++++
> arch/mips/configs/cu1000-neo_defconfig | 2 +-
> arch/mips/configs/cu1830-neo_defconfig | 2 +-
> 6 files changed, 154 insertions(+), 76 deletions(-)
>
> --
> 2.7.4

seried applied to mips-next.

Thomas.

--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]