From: Guo Ren <[email protected]>
In commit 588a513d3425 ("arm64: Fix race condition on PG_dcache_clean
in __sync_icache_dcache()"), we found RISC-V has the same issue as the
previous arm64. The previous implementation didn't guarantee the correct
sequence of operations, which means flush_icache_all() hasn't been
called when the PG_dcache_clean was set. That would cause a risk of page
synchronization.
Fixes: 08f051eda33b ("RISC-V: Flush I$ when making a dirty page executable")
Signed-off-by: Guo Ren <[email protected]>
Signed-off-by: Guo Ren <[email protected]>
---
Changelog:
V2:
- Optimize commit log
- Rebase on riscv for-next (20230127)
V1:
https://lore.kernel.org/linux-riscv/[email protected]/
---
arch/riscv/mm/cacheflush.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
index 3cc07ed45aeb..fcd6145fbead 100644
--- a/arch/riscv/mm/cacheflush.c
+++ b/arch/riscv/mm/cacheflush.c
@@ -90,8 +90,10 @@ void flush_icache_pte(pte_t pte)
if (PageHuge(page))
page = compound_head(page);
- if (!test_and_set_bit(PG_dcache_clean, &page->flags))
+ if (!test_bit(PG_dcache_clean, &page->flags)) {
flush_icache_all();
+ set_bit(PG_dcache_clean, &page->flags);
+ }
}
#endif /* CONFIG_MMU */
--
2.36.1
On Thu, Jan 26, 2023 at 10:53:06PM -0500, [email protected] wrote:
> From: Guo Ren <[email protected]>
>
> In commit 588a513d3425 ("arm64: Fix race condition on PG_dcache_clean
> in __sync_icache_dcache()"), we found RISC-V has the same issue as the
> previous arm64. The previous implementation didn't guarantee the correct
> sequence of operations, which means flush_icache_all() hasn't been
> called when the PG_dcache_clean was set. That would cause a risk of page
> synchronization.
>
> Fixes: 08f051eda33b ("RISC-V: Flush I$ when making a dirty page executable")
> Signed-off-by: Guo Ren <[email protected]>
> Signed-off-by: Guo Ren <[email protected]>
> ---
> Changelog:
> V2:
> - Optimize commit log
> - Rebase on riscv for-next (20230127)
>
> V1:
> https://lore.kernel.org/linux-riscv/[email protected]/
> ---
> arch/riscv/mm/cacheflush.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
> index 3cc07ed45aeb..fcd6145fbead 100644
> --- a/arch/riscv/mm/cacheflush.c
> +++ b/arch/riscv/mm/cacheflush.c
> @@ -90,8 +90,10 @@ void flush_icache_pte(pte_t pte)
> if (PageHuge(page))
> page = compound_head(page);
>
> - if (!test_and_set_bit(PG_dcache_clean, &page->flags))
> + if (!test_bit(PG_dcache_clean, &page->flags)) {
> flush_icache_all();
> + set_bit(PG_dcache_clean, &page->flags);
> + }
> }
> #endif /* CONFIG_MMU */
>
> --
> 2.36.1
>
Reviewed-by: Andrew Jones <[email protected]>
Thanks,
drew
Hey Guo Ren,
On Thu, Jan 26, 2023 at 10:53:06PM -0500, [email protected] wrote:
> From: Guo Ren <[email protected]>
>
> In commit 588a513d3425 ("arm64: Fix race condition on PG_dcache_clean
> in __sync_icache_dcache()"), we found RISC-V has the same issue as the
> previous arm64. The previous implementation didn't guarantee the correct
> sequence of operations, which means flush_icache_all() hasn't been
> called when the PG_dcache_clean was set. That would cause a risk of page
> synchronization.
>
> Fixes: 08f051eda33b ("RISC-V: Flush I$ when making a dirty page executable")
> Signed-off-by: Guo Ren <[email protected]>
> Signed-off-by: Guo Ren <[email protected]>
> ---
> Changelog:
> V2:
> - Optimize commit log
Probably would have benefited from providing the analysis that the arm64
commit did, for riscv, rather than referring to theirs.
But that's not really important and the diff itself seems sound, so:
Reviewed-by: Conor Dooley <[email protected]>
Thanks,
Conor.
> - Rebase on riscv for-next (20230127)
>
> V1:
> https://lore.kernel.org/linux-riscv/[email protected]/
> ---
> arch/riscv/mm/cacheflush.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
> index 3cc07ed45aeb..fcd6145fbead 100644
> --- a/arch/riscv/mm/cacheflush.c
> +++ b/arch/riscv/mm/cacheflush.c
> @@ -90,8 +90,10 @@ void flush_icache_pte(pte_t pte)
> if (PageHuge(page))
> page = compound_head(page);
>
> - if (!test_and_set_bit(PG_dcache_clean, &page->flags))
> + if (!test_bit(PG_dcache_clean, &page->flags)) {
> flush_icache_all();
> + set_bit(PG_dcache_clean, &page->flags);
> + }
> }
> #endif /* CONFIG_MMU */
>
> --
> 2.36.1
>
On Sat, Jan 28, 2023 at 7:36 AM Conor Dooley <[email protected]> wrote:
>
> Hey Guo Ren,
>
> On Thu, Jan 26, 2023 at 10:53:06PM -0500, [email protected] wrote:
> > From: Guo Ren <[email protected]>
> >
> > In commit 588a513d3425 ("arm64: Fix race condition on PG_dcache_clean
> > in __sync_icache_dcache()"), we found RISC-V has the same issue as the
> > previous arm64. The previous implementation didn't guarantee the correct
> > sequence of operations, which means flush_icache_all() hasn't been
> > called when the PG_dcache_clean was set. That would cause a risk of page
> > synchronization.
> >
> > Fixes: 08f051eda33b ("RISC-V: Flush I$ when making a dirty page executable")
> > Signed-off-by: Guo Ren <[email protected]>
> > Signed-off-by: Guo Ren <[email protected]>
> > ---
> > Changelog:
> > V2:
> > - Optimize commit log
>
> Probably would have benefited from providing the analysis that the arm64
> commit did, for riscv, rather than referring to theirs.
Maybe you are right, but they are almost the same for this patch. So I
didn't want to duplicate the commit log but gave out the original
instead.
> But that's not really important and the diff itself seems sound, so:
> Reviewed-by: Conor Dooley <[email protected]>
Thx.
>
> Thanks,
> Conor.
>
> > - Rebase on riscv for-next (20230127)
> >
> > V1:
> > https://lore.kernel.org/linux-riscv/[email protected]/
> > ---
> > arch/riscv/mm/cacheflush.c | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/riscv/mm/cacheflush.c b/arch/riscv/mm/cacheflush.c
> > index 3cc07ed45aeb..fcd6145fbead 100644
> > --- a/arch/riscv/mm/cacheflush.c
> > +++ b/arch/riscv/mm/cacheflush.c
> > @@ -90,8 +90,10 @@ void flush_icache_pte(pte_t pte)
> > if (PageHuge(page))
> > page = compound_head(page);
> >
> > - if (!test_and_set_bit(PG_dcache_clean, &page->flags))
> > + if (!test_bit(PG_dcache_clean, &page->flags)) {
> > flush_icache_all();
> > + set_bit(PG_dcache_clean, &page->flags);
> > + }
> > }
> > #endif /* CONFIG_MMU */
> >
> > --
> > 2.36.1
> >
--
Best Regards
Guo Ren
On Thu, 26 Jan 2023 22:53:06 -0500, [email protected] wrote:
> In commit 588a513d3425 ("arm64: Fix race condition on PG_dcache_clean
> in __sync_icache_dcache()"), we found RISC-V has the same issue as the
> previous arm64. The previous implementation didn't guarantee the correct
> sequence of operations, which means flush_icache_all() hasn't been
> called when the PG_dcache_clean was set. That would cause a risk of page
> synchronization.
>
> [...]
Applied, thanks!
[1/1] riscv: Fixup race condition on PG_dcache_clean in flush_icache_pte
https://git.kernel.org/palmer/c/950b879b7f02
Best regards,
--
Palmer Dabbelt <[email protected]>
Hello:
This patch was applied to riscv/linux.git (fixes)
by Palmer Dabbelt <[email protected]>:
On Thu, 26 Jan 2023 22:53:06 -0500 you wrote:
> From: Guo Ren <[email protected]>
>
> In commit 588a513d3425 ("arm64: Fix race condition on PG_dcache_clean
> in __sync_icache_dcache()"), we found RISC-V has the same issue as the
> previous arm64. The previous implementation didn't guarantee the correct
> sequence of operations, which means flush_icache_all() hasn't been
> called when the PG_dcache_clean was set. That would cause a risk of page
> synchronization.
>
> [...]
Here is the summary with links:
- [V2] riscv: Fixup race condition on PG_dcache_clean in flush_icache_pte
https://git.kernel.org/riscv/c/950b879b7f02
You are awesome, thank you!
--
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