Do some small clean up.
0c562876972ee dmaengine: fsl-edma: remove 'slave_id' from fsl_edma_chan
d9b66cb5fdf62 dmaengine: fsl-edma: add safety check for 'srcid'
aae21b7528311 dmaengine: fsl-edma: clean up chclk and FSL_EDMA_DRV_HAS_CHCLK
Update binding doc.
23a1d1a6609fa dt-bindings: fsl-dma: fsl-edma: add fsl,imx8ulp-edma compatible string
Add 8ulp support.
dmaengine: fsl-edma: add i.MX8ULP edma support
Signed-off-by: Frank Li <[email protected]>
---
Changes in v3:
- Change clock name form CHXX-CLK to chxx
- Fix typeo 'clock'
- Add dma-cell description
- About clock-names:
items:
oneOf:
- const: dma
- pattern: ...
Which already detect naming wrong, for example:
clock-names = "dma", "ch00", "ch01", "ch02", "ch03",
....
"ch28", "ch29", "ch30", "abcc";
arch/arm64/boot/dts/freescale/imx8ulp-evk.dtb: dma-controller@29010000: clock-names:32: 'oneOf' conditional failed, one must be fixed:
'dma' was expected
'abcc' does not match '^ch(0[0-9]|[1-2][0-9]|3[01])$'
Only lose order check, such as ch00, dma, ch03, ch02, can pass check.
I think it is good enough.
I tried rob's suggestion, but met some technology issue. Detail see
https://lore.kernel.org/imx/[email protected]/T/#mc5767dd505d4b7cfc66586a0631684a57e735476
- Link to v2: https://lore.kernel.org/r/[email protected]
Changes in v2:
Fixed dt-bind about clocks number restriction for vf610. Keep the same
restriction for other compatible string.
Send out v2 to avoid consiste test rebot report build error.
Fixed build error
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <[email protected]>
| Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/
Rework dt-binding commit message. Add reason why change clk number to 33.
- Link to v1: https://lore.kernel.org/r/[email protected]
---
Frank Li (3):
dmaengine: fsl-edma: remove 'slave_id' from fsl_edma_chan
dmaengine: fsl-edma: add safety check for 'srcid'
dmaengine: fsl-edma: clean up chclk and FSL_EDMA_DRV_HAS_CHCLK
Joy Zou (2):
dt-bindings: dma: fsl-edma: add fsl,imx8ulp-edma compatible string
dmaengine: fsl-edma: add i.MX8ULP edma support
.../devicetree/bindings/dma/fsl,edma.yaml | 40 +++++++++++++++++-
drivers/dma/fsl-edma-common.c | 6 +++
drivers/dma/fsl-edma-common.h | 2 -
drivers/dma/fsl-edma-main.c | 47 ++++++++++++++++------
drivers/dma/mcf-edma-main.c | 4 +-
5 files changed, 80 insertions(+), 19 deletions(-)
---
base-commit: 37cbf12c590dbe3e66c6d489aaf9b35f7b6a0670
change-id: 20240227-8ulp_edma-12ee2648d74b
Best regards,
---
Frank Li <[email protected]>
The 'slave_id' field is redundant as it duplicates the functionality of
'srcid'. Remove 'slave_id' from fsl_edma_chan to eliminate redundancy.
Signed-off-by: Frank Li <[email protected]>
---
drivers/dma/fsl-edma-common.h | 1 -
drivers/dma/fsl-edma-main.c | 10 +++++-----
drivers/dma/mcf-edma-main.c | 4 ++--
3 files changed, 7 insertions(+), 8 deletions(-)
diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
index 7bf0aba471a8c..4cf1de9f0e512 100644
--- a/drivers/dma/fsl-edma-common.h
+++ b/drivers/dma/fsl-edma-common.h
@@ -151,7 +151,6 @@ struct fsl_edma_chan {
enum dma_status status;
enum fsl_edma_pm_state pm_state;
bool idle;
- u32 slave_id;
struct fsl_edma_engine *edma;
struct fsl_edma_desc *edesc;
struct dma_slave_config cfg;
diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c
index 402f0058a180c..0a6e0c4040274 100644
--- a/drivers/dma/fsl-edma-main.c
+++ b/drivers/dma/fsl-edma-main.c
@@ -114,8 +114,8 @@ static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec,
if (chan) {
chan->device->privatecnt++;
fsl_chan = to_fsl_edma_chan(chan);
- fsl_chan->slave_id = dma_spec->args[1];
- fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id,
+ fsl_chan->srcid = dma_spec->args[1];
+ fsl_edma_chan_mux(fsl_chan, fsl_chan->srcid,
true);
mutex_unlock(&fsl_edma->fsl_edma_mutex);
return chan;
@@ -540,7 +540,7 @@ static int fsl_edma_probe(struct platform_device *pdev)
fsl_chan->edma = fsl_edma;
fsl_chan->pm_state = RUNNING;
- fsl_chan->slave_id = 0;
+ fsl_chan->srcid = 0;
fsl_chan->idle = true;
fsl_chan->dma_dir = DMA_NONE;
fsl_chan->vchan.desc_free = fsl_edma_free_desc;
@@ -682,8 +682,8 @@ static int fsl_edma_resume_early(struct device *dev)
continue;
fsl_chan->pm_state = RUNNING;
edma_write_tcdreg(fsl_chan, 0, csr);
- if (fsl_chan->slave_id != 0)
- fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, true);
+ if (fsl_chan->srcid != 0)
+ fsl_edma_chan_mux(fsl_chan, fsl_chan->srcid, true);
}
if (!(fsl_edma->drvdata->flags & FSL_EDMA_DRV_SPLIT_REG))
diff --git a/drivers/dma/mcf-edma-main.c b/drivers/dma/mcf-edma-main.c
index dba6317838767..78c606f6d0026 100644
--- a/drivers/dma/mcf-edma-main.c
+++ b/drivers/dma/mcf-edma-main.c
@@ -195,7 +195,7 @@ static int mcf_edma_probe(struct platform_device *pdev)
struct fsl_edma_chan *mcf_chan = &mcf_edma->chans[i];
mcf_chan->edma = mcf_edma;
- mcf_chan->slave_id = i;
+ mcf_chan->srcid = i;
mcf_chan->idle = true;
mcf_chan->dma_dir = DMA_NONE;
mcf_chan->vchan.desc_free = fsl_edma_free_desc;
@@ -277,7 +277,7 @@ bool mcf_edma_filter_fn(struct dma_chan *chan, void *param)
if (chan->device->dev->driver == &mcf_edma_driver.driver) {
struct fsl_edma_chan *mcf_chan = to_fsl_edma_chan(chan);
- return (mcf_chan->slave_id == (uintptr_t)param);
+ return (mcf_chan->srcid == (uintptr_t)param);
}
return false;
--
2.34.1
Ensure that 'srcid' is a non-zero value to avoid dtb passing invalid
'srcid' to the driver.
Signed-off-by: Frank Li <[email protected]>
---
drivers/dma/fsl-edma-main.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c
index 0a6e0c4040274..2148a7f1ae843 100644
--- a/drivers/dma/fsl-edma-main.c
+++ b/drivers/dma/fsl-edma-main.c
@@ -115,6 +115,13 @@ static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec,
chan->device->privatecnt++;
fsl_chan = to_fsl_edma_chan(chan);
fsl_chan->srcid = dma_spec->args[1];
+
+ if (!fsl_chan->srcid) {
+ dev_err(&fsl_chan->pdev->dev, "Invalidate srcid %d\n",
+ fsl_chan->srcid);
+ return NULL;
+ }
+
fsl_edma_chan_mux(fsl_chan, fsl_chan->srcid,
true);
mutex_unlock(&fsl_edma->fsl_edma_mutex);
--
2.34.1
No device currently utilizes chclk and FSL_EDMA_DRV_HAS_CHCLK features.
Removes these unused features.
Signed-off-by: Frank Li <[email protected]>
---
drivers/dma/fsl-edma-common.h | 2 --
drivers/dma/fsl-edma-main.c | 8 --------
2 files changed, 10 deletions(-)
diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
index 4cf1de9f0e512..532f647e540e7 100644
--- a/drivers/dma/fsl-edma-common.h
+++ b/drivers/dma/fsl-edma-common.h
@@ -192,7 +192,6 @@ struct fsl_edma_desc {
#define FSL_EDMA_DRV_WRAP_IO BIT(3)
#define FSL_EDMA_DRV_EDMA64 BIT(4)
#define FSL_EDMA_DRV_HAS_PD BIT(5)
-#define FSL_EDMA_DRV_HAS_CHCLK BIT(6)
#define FSL_EDMA_DRV_HAS_CHMUX BIT(7)
/* imx8 QM audio edma remote local swapped */
#define FSL_EDMA_DRV_QUIRK_SWAPPED BIT(8)
@@ -237,7 +236,6 @@ struct fsl_edma_engine {
void __iomem *muxbase[DMAMUX_NR];
struct clk *muxclk[DMAMUX_NR];
struct clk *dmaclk;
- struct clk *chclk;
struct mutex fsl_edma_mutex;
const struct fsl_edma_drvdata *drvdata;
u32 n_chans;
diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c
index 2148a7f1ae843..41c71c360ff1f 100644
--- a/drivers/dma/fsl-edma-main.c
+++ b/drivers/dma/fsl-edma-main.c
@@ -483,14 +483,6 @@ static int fsl_edma_probe(struct platform_device *pdev)
}
}
- if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) {
- fsl_edma->chclk = devm_clk_get_enabled(&pdev->dev, "mp");
- if (IS_ERR(fsl_edma->chclk)) {
- dev_err(&pdev->dev, "Missing MP block clock.\n");
- return PTR_ERR(fsl_edma->chclk);
- }
- }
-
ret = of_property_read_variable_u32_array(np, "dma-channel-mask", chan_mask, 1, 2);
if (ret > 0) {
--
2.34.1
From: Joy Zou <[email protected]>
Introduce the compatible string 'fsl,imx8ulp-edma' to enable support for
the i.MX8ULP's eDMA, alongside adjusting the clock numbering. The i.MX8ULP
eDMA architecture features one clock for each DMA channel and an additional
clock for the core controller. Given a maximum of 32 DMA channels, the
maximum clock number consequently increases to 33.
Signed-off-by: Joy Zou <[email protected]>
Signed-off-by: Frank Li <[email protected]>
---
Notes:
Changes in v3:
- Change clock name form CHXX-CLK to chxx
- Fix typeo 'clock'
- Add dma-cell description
- About clock-names:
items:
oneOf:
- const: dma
- pattern: ...
Which already detect naming wrong, for example:
clock-names = "dma", "ch00", "ch01", "ch02", "ch03",
....
"ch28", "ch29", "ch30", "abcc";
arch/arm64/boot/dts/freescale/imx8ulp-evk.dtb: dma-controller@29010000: clock-names:32: 'oneOf' conditional failed, one must be fixed:
'dma' was expected
'abcc' does not match '^ch(0[0-9]|[1-2][0-9]|3[01])$'
Only lose order check, such as ch00, dma, ch03, ch02, can pass check.
I think it is good enough.
I tried rob's suggestion, but met some technology issue. Detail see
https://lore.kernel.org/imx/[email protected]/T/#mc5767dd505d4b7cfc66586a0631684a57e735476
.../devicetree/bindings/dma/fsl,edma.yaml | 40 ++++++++++++++++++++--
1 file changed, 38 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/dma/fsl,edma.yaml b/Documentation/devicetree/bindings/dma/fsl,edma.yaml
index aa51d278cb67b..825f4715499e5 100644
--- a/Documentation/devicetree/bindings/dma/fsl,edma.yaml
+++ b/Documentation/devicetree/bindings/dma/fsl,edma.yaml
@@ -23,6 +23,7 @@ properties:
- fsl,imx7ulp-edma
- fsl,imx8qm-adma
- fsl,imx8qm-edma
+ - fsl,imx8ulp-edma
- fsl,imx93-edma3
- fsl,imx93-edma4
- fsl,imx95-edma5
@@ -43,6 +44,17 @@ properties:
maxItems: 64
"#dma-cells":
+ description: |
+ Specifies the number of cells needed to encode an DMA channel.
+
+ Encode for cells number 2:
+ cell 0: index of dma channel mux instance.
+ cell 1: peripheral dma request id.
+
+ Encode for cells number 3:
+ cell 0: peripheral dma request id.
+ cell 1: dma channel priority.
+ cell 2: bitmask, defined at include/dt-bindings/dma/fsl-edma.h
enum:
- 2
- 3
@@ -53,11 +65,11 @@ properties:
clocks:
minItems: 1
- maxItems: 2
+ maxItems: 33
clock-names:
minItems: 1
- maxItems: 2
+ maxItems: 33
big-endian:
description: |
@@ -108,6 +120,7 @@ allOf:
properties:
clocks:
minItems: 2
+ maxItems: 2
clock-names:
items:
- const: dmamux0
@@ -136,6 +149,7 @@ allOf:
properties:
clock:
minItems: 2
+ maxItems: 2
clock-names:
items:
- const: dma
@@ -151,6 +165,28 @@ allOf:
dma-channels:
const: 32
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8ulp-edma
+ then:
+ properties:
+ clocks:
+ minItems: 33
+ clock-names:
+ minItems: 33
+ items:
+ oneOf:
+ - const: dma
+ - pattern: "^ch(0[0-9]|[1-2][0-9]|3[01])$"
+
+ interrupt-names: false
+ interrupts:
+ minItems: 32
+ "#dma-cells":
+ const: 3
+
unevaluatedProperties: false
examples:
--
2.34.1
From: Joy Zou <[email protected]>
Add support for the i.MX8ULP platform to the eDMA driver. Introduce the use
of the correct FSL_EDMA_DRV_HAS_CHCLK flag to handle per-channel clock
configurations.
Signed-off-by: Joy Zou <[email protected]>
Reviewed-by: Frank Li <[email protected]>
---
drivers/dma/fsl-edma-common.c | 6 ++++++
drivers/dma/fsl-edma-common.h | 1 +
drivers/dma/fsl-edma-main.c | 22 ++++++++++++++++++++++
3 files changed, 29 insertions(+)
diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index b18faa7cfedb9..f9144b0154396 100644
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -3,6 +3,7 @@
// Copyright (c) 2013-2014 Freescale Semiconductor, Inc
// Copyright (c) 2017 Sysam, Angelo Dureghello <[email protected]>
+#include <linux/clk.h>
#include <linux/dmapool.h>
#include <linux/module.h>
#include <linux/slab.h>
@@ -810,6 +811,9 @@ int fsl_edma_alloc_chan_resources(struct dma_chan *chan)
{
struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
+ if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_CHCLK)
+ clk_prepare_enable(fsl_chan->clk);
+
fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev,
fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_TCD64 ?
sizeof(struct fsl_edma_hw_tcd64) : sizeof(struct fsl_edma_hw_tcd),
@@ -838,6 +842,8 @@ void fsl_edma_free_chan_resources(struct dma_chan *chan)
fsl_chan->tcd_pool = NULL;
fsl_chan->is_sw = false;
fsl_chan->srcid = 0;
+ if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_CHCLK)
+ clk_disable_unprepare(fsl_chan->clk);
}
void fsl_edma_cleanup_vchan(struct dma_device *dmadev)
diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h
index 532f647e540e7..01157912bfd5f 100644
--- a/drivers/dma/fsl-edma-common.h
+++ b/drivers/dma/fsl-edma-common.h
@@ -192,6 +192,7 @@ struct fsl_edma_desc {
#define FSL_EDMA_DRV_WRAP_IO BIT(3)
#define FSL_EDMA_DRV_EDMA64 BIT(4)
#define FSL_EDMA_DRV_HAS_PD BIT(5)
+#define FSL_EDMA_DRV_HAS_CHCLK BIT(6)
#define FSL_EDMA_DRV_HAS_CHMUX BIT(7)
/* imx8 QM audio edma remote local swapped */
#define FSL_EDMA_DRV_QUIRK_SWAPPED BIT(8)
diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c
index 41c71c360ff1f..755a3dc3b0a78 100644
--- a/drivers/dma/fsl-edma-main.c
+++ b/drivers/dma/fsl-edma-main.c
@@ -356,6 +356,16 @@ static struct fsl_edma_drvdata imx8qm_audio_data = {
.setup_irq = fsl_edma3_irq_init,
};
+static struct fsl_edma_drvdata imx8ulp_data = {
+ .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_CHCLK | FSL_EDMA_DRV_HAS_DMACLK |
+ FSL_EDMA_DRV_EDMA3,
+ .chreg_space_sz = 0x10000,
+ .chreg_off = 0x10000,
+ .mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux),
+ .mux_skip = 0x10000,
+ .setup_irq = fsl_edma3_irq_init,
+};
+
static struct fsl_edma_drvdata imx93_data3 = {
.flags = FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA3,
.chreg_space_sz = 0x10000,
@@ -388,6 +398,7 @@ static const struct of_device_id fsl_edma_dt_ids[] = {
{ .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data},
{ .compatible = "fsl,imx8qm-edma", .data = &imx8qm_data},
{ .compatible = "fsl,imx8qm-adma", .data = &imx8qm_audio_data},
+ { .compatible = "fsl,imx8ulp-edma", .data = &imx8ulp_data},
{ .compatible = "fsl,imx93-edma3", .data = &imx93_data3},
{ .compatible = "fsl,imx93-edma4", .data = &imx93_data4},
{ .compatible = "fsl,imx95-edma5", .data = &imx95_data5},
@@ -441,6 +452,7 @@ static int fsl_edma_probe(struct platform_device *pdev)
struct fsl_edma_engine *fsl_edma;
const struct fsl_edma_drvdata *drvdata = NULL;
u32 chan_mask[2] = {0, 0};
+ char clk_name[36];
struct edma_regs *regs;
int chans;
int ret, i;
@@ -550,11 +562,21 @@ static int fsl_edma_probe(struct platform_device *pdev)
+ i * drvdata->chreg_space_sz + drvdata->chreg_off + len;
fsl_chan->mux_addr = fsl_edma->membase + drvdata->mux_off + i * drvdata->mux_skip;
+ if (drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK) {
+ snprintf(clk_name, sizeof(clk_name), "ch%02d", i);
+ fsl_chan->clk = devm_clk_get_enabled(&pdev->dev,
+ (const char *)clk_name);
+
+ if (IS_ERR(fsl_chan->clk))
+ return PTR_ERR(fsl_chan->clk);
+ }
fsl_chan->pdev = pdev;
vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
edma_write_tcdreg(fsl_chan, cpu_to_le32(0), csr);
fsl_edma_chan_mux(fsl_chan, 0, false);
+ if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_HAS_CHCLK)
+ clk_disable_unprepare(fsl_chan->clk);
}
ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma);
--
2.34.1
On Sat, 23 Mar 2024 11:34:53 -0400, Frank Li wrote:
> From: Joy Zou <[email protected]>
>
> Introduce the compatible string 'fsl,imx8ulp-edma' to enable support for
> the i.MX8ULP's eDMA, alongside adjusting the clock numbering. The i.MX8ULP
> eDMA architecture features one clock for each DMA channel and an additional
> clock for the core controller. Given a maximum of 32 DMA channels, the
> maximum clock number consequently increases to 33.
>
> Signed-off-by: Joy Zou <[email protected]>
> Signed-off-by: Frank Li <[email protected]>
> ---
>
> Notes:
> Changes in v3:
> - Change clock name form CHXX-CLK to chxx
> - Fix typeo 'clock'
> - Add dma-cell description
> - About clock-names:
> items:
> oneOf:
> - const: dma
> - pattern: ...
>
> Which already detect naming wrong, for example:
>
> clock-names = "dma", "ch00", "ch01", "ch02", "ch03",
> ....
> "ch28", "ch29", "ch30", "abcc";
>
> arch/arm64/boot/dts/freescale/imx8ulp-evk.dtb: dma-controller@29010000: clock-names:32: 'oneOf' conditional failed, one must be fixed:
> 'dma' was expected
> 'abcc' does not match '^ch(0[0-9]|[1-2][0-9]|3[01])$'
>
> Only lose order check, such as ch00, dma, ch03, ch02, can pass check.
> I think it is good enough.
>
> I tried rob's suggestion, but met some technology issue. Detail see
>
> https://lore.kernel.org/imx/[email protected]/T/#mc5767dd505d4b7cfc66586a0631684a57e735476
>
> .../devicetree/bindings/dma/fsl,edma.yaml | 40 ++++++++++++++++++++--
> 1 file changed, 38 insertions(+), 2 deletions(-)
>
Reviewed-by: Rob Herring <[email protected]>
On Sat, 23 Mar 2024 11:34:49 -0400, Frank Li wrote:
> Do some small clean up.
>
> 0c562876972ee dmaengine: fsl-edma: remove 'slave_id' from fsl_edma_chan
> d9b66cb5fdf62 dmaengine: fsl-edma: add safety check for 'srcid'
> aae21b7528311 dmaengine: fsl-edma: clean up chclk and FSL_EDMA_DRV_HAS_CHCLK
>
> Update binding doc.
> 23a1d1a6609fa dt-bindings: fsl-dma: fsl-edma: add fsl,imx8ulp-edma compatible string
>
> [...]
Applied, thanks!
[1/5] dmaengine: fsl-edma: remove 'slave_id' from fsl_edma_chan
commit: cee8cbfc7be8ff9f3ccf258134f9ab2c273abb75
[2/5] dmaengine: fsl-edma: add safety check for 'srcid'
commit: 6aa60f79e6794bbbc571ea4e0501b9fcc26026e2
[3/5] dmaengine: fsl-edma: clean up chclk and FSL_EDMA_DRV_HAS_CHCLK
commit: 9a5000cf70bcfcb5dd4e5b4bae0a01fb9bdf9fa1
[4/5] dt-bindings: dma: fsl-edma: add fsl,imx8ulp-edma compatible string
commit: b14f56beb289ff67fe484d720bf09092163f90c8
[5/5] dmaengine: fsl-edma: add i.MX8ULP edma support
commit: d8d4355861d874cbd1395ec0edcbe4e0f6940738
Best regards,
--
~Vinod