The following commit has been merged into the x86/cpu branch of tip:
Commit-ID: 68b4c6d168c547b19ba5697f9398c3f4aa8b4276
Gitweb: https://git.kernel.org/tip/68b4c6d168c547b19ba5697f9398c3f4aa8b4276
Author: Tony Luck <[email protected]>
AuthorDate: Wed, 24 Apr 2024 11:15:13 -07:00
Committer: Dave Hansen <[email protected]>
CommitterDate: Fri, 26 Apr 2024 08:49:24 -07:00
x86/mce: Switch to new Intel CPU model defines
New CPU #defines encode vendor and family as well as model.
Signed-off-by: Tony Luck <[email protected]>
Signed-off-by: Dave Hansen <[email protected]>
Link: https://lore.kernel.org/all/20240424181513.41810-1-tony.luck%40intel.com
---
arch/x86/kernel/cpu/mce/severity.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/arch/x86/kernel/cpu/mce/severity.c b/arch/x86/kernel/cpu/mce/severity.c
index fc8988c..7293a1c 100644
--- a/arch/x86/kernel/cpu/mce/severity.c
+++ b/arch/x86/kernel/cpu/mce/severity.c
@@ -12,7 +12,7 @@
#include <linux/uaccess.h>
#include <asm/mce.h>
-#include <asm/intel-family.h>
+#include <asm/cpu_device_id.h>
#include <asm/traps.h>
#include <asm/insn.h>
#include <asm/insn-eval.h>
@@ -45,14 +45,14 @@ static struct severity {
unsigned char context;
unsigned char excp;
unsigned char covered;
- unsigned char cpu_model;
+ unsigned int cpu_vfm;
unsigned char cpu_minstepping;
unsigned char bank_lo, bank_hi;
char *msg;
} severities[] = {
#define MCESEV(s, m, c...) { .sev = MCE_ ## s ## _SEVERITY, .msg = m, ## c }
#define BANK_RANGE(l, h) .bank_lo = l, .bank_hi = h
-#define MODEL_STEPPING(m, s) .cpu_model = m, .cpu_minstepping = s
+#define VFM_STEPPING(m, s) .cpu_vfm = m, .cpu_minstepping = s
#define KERNEL .context = IN_KERNEL
#define USER .context = IN_USER
#define KERNEL_RECOV .context = IN_KERNEL_RECOV
@@ -128,7 +128,7 @@ static struct severity {
MCESEV(
AO, "Uncorrected Patrol Scrub Error",
SER, MASK(MCI_STATUS_UC|MCI_ADDR|0xffffeff0, MCI_ADDR|0x001000c0),
- MODEL_STEPPING(INTEL_FAM6_SKYLAKE_X, 4), BANK_RANGE(13, 18)
+ VFM_STEPPING(INTEL_SKYLAKE_X, 4), BANK_RANGE(13, 18)
),
/* ignore OVER for UCNA */
@@ -398,7 +398,7 @@ static noinstr int mce_severity_intel(struct mce *m, struct pt_regs *regs, char
continue;
if (s->excp && excp != s->excp)
continue;
- if (s->cpu_model && boot_cpu_data.x86_model != s->cpu_model)
+ if (s->cpu_vfm && boot_cpu_data.x86_model != s->cpu_vfm)
continue;
if (s->cpu_minstepping && boot_cpu_data.x86_stepping < s->cpu_minstepping)
continue;
On Fri, Apr 26, 2024 at 06:12:11PM -0000, tip-bot2 for Tony Luck wrote:
> @@ -398,7 +398,7 @@ static noinstr int mce_severity_intel(struct mce *m, struct pt_regs *regs, char
> continue;
> if (s->excp && excp != s->excp)
> continue;
> - if (s->cpu_model && boot_cpu_data.x86_model != s->cpu_model)
> + if (s->cpu_vfm && boot_cpu_data.x86_model != s->cpu_vfm)
Hold on, isn't this supposed to be:
if (s->cpu_vfm && boot_cpu_data.cpu_vfm != s->cpu_vfm)
?
You're getting rid of the ->x86_model checking altogether...
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
This is obviously nonsense. Fix it.
Fixes: 68b4c6d168c5 ("x86/mce: Switch to new Intel CPU model defines")
Reported-by: Borislav Petkov <[email protected]>
Signed-off-by: Tony Luck <[email protected]>
---
Boris: Do you rebase x86/cpu branch in TIP? If so this could be merged
into the broken patch. If not then slap it on top. Risk of bisection
breakage is tiny as this only affects a quirk handling patrol scrub
errors on Skylake and Cascade lake systems.
arch/x86/kernel/cpu/mce/severity.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/mce/severity.c b/arch/x86/kernel/cpu/mce/severity.c
index 7293a1c49050..e7892f11c70f 100644
--- a/arch/x86/kernel/cpu/mce/severity.c
+++ b/arch/x86/kernel/cpu/mce/severity.c
@@ -398,7 +398,7 @@ static noinstr int mce_severity_intel(struct mce *m, struct pt_regs *regs, char
continue;
if (s->excp && excp != s->excp)
continue;
- if (s->cpu_vfm && boot_cpu_data.x86_model != s->cpu_vfm)
+ if (s->cpu_vfm && boot_cpu_data.x86_vfm != s->cpu_vfm)
continue;
if (s->cpu_minstepping && boot_cpu_data.x86_stepping < s->cpu_minstepping)
continue;
--
2.44.0
On Sun, Apr 28, 2024 at 07:20:51PM -0700, Tony Luck wrote:
> This is obviously nonsense. Fix it.
>
> Fixes: 68b4c6d168c5 ("x86/mce: Switch to new Intel CPU model defines")
> Reported-by: Borislav Petkov <[email protected]>
> Signed-off-by: Tony Luck <[email protected]>
> ---
>
> Boris: Do you rebase x86/cpu branch in TIP? If so this could be merged
> into the broken patch. If not then slap it on top. Risk of bisection
> breakage is tiny as this only affects a quirk handling patrol scrub
> errors on Skylake and Cascade lake systems.
Lemme try to rebase. And btw, you could've avoided the same name
patches:
e063b531d4e8 (refs/remotes/tip/x86/cpu) x86/mm: Switch to new Intel CPU model defines
94eb882e9575 x86/tsc_msr: Switch to new Intel CPU model defines
95be3ccd711c x86/tsc: Switch to new Intel CPU model defines
7cd2e9a90299 x86/cpu: Switch to new Intel CPU model defines
343ec8beae30 x86/resctrl: Switch to new Intel CPU model defines
43e8e0a95a89 x86/resctrl: Switch to new Intel CPU model defines
<--
173e856a55d0 x86/microcode/intel: Switch to new Intel CPU model defines
68b4c6d168c5 x86/mce: Switch to new Intel CPU model defines
8a5943977900 x86/mce: Switch to new Intel CPU model defines
066f54e65e47 x86/mce: Switch to new Intel CPU model defines
<---
34304acb3290 x86/cpu: Switch to new Intel CPU model defines
77d0930acedf x86/cpu/intel_epb: Switch to new Intel CPU model defines
a7c345216f88 x86/aperfmperf: Switch to new Intel CPU model defines
22878345b4c1 x86/apic: Switch to new Intel CPU model defines
e8475a26a94f perf/x86/msr: Switch to new Intel CPU model defines
438731421a2f perf/x86/intel/uncore: Switch to new Intel CPU model defines
d413a1955a8e perf/x86/intel/uncore: Switch to new Intel CPU model defines
9b2583d8103e perf/x86/intel/uncore: Switch to new Intel CPU model defines
<---
a7011b852a30 perf/x86/intel/pt: Switch to new Intel CPU model defines
0011a51d73d5 perf/x86/lbr: Switch to new Intel CPU model defines
5ee800945a34 perf/x86/intel/cstate: Switch to new Intel CPU model defines
and why in the hell are there 2 or 3 patches of the same name touching
the same thing? Why can't they be a single patch?
Lemme rebase the lot.
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
> and why in the hell are there 2 or 3 patches of the same name touching
> the same thing? Why can't they be a single patch?
I made one patch per file touched (wherever possible ... there are a few patches
where ".h" and ".c" files needed to be bundled together).
> Lemme rebase the lot.
Thanks. I just did a "git fetch" the x86/cpu branch. It all looks good.
-Tony
On Mon, Apr 29, 2024 at 04:05:29PM +0000, Luck, Tony wrote:
> I made one patch per file touched (wherever possible ... there are a few patches
> where ".h" and ".c" files needed to be bundled together).
I figured. I think the next step would've been to group them all into
a single patch based on the subject prefix. But we're doing that now
anyway.
> Thanks. I just did a "git fetch" the x86/cpu branch. It all looks good.
Thx!
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette