This adds support to the TI eQEP counter driver for subscribing to
overflow and underflow events using the counter chrdev interface.
Signed-off-by: David Lechner <[email protected]>
---
This is split out from a series that was sent a few years back [1] that
I never finished, so I'm calling it v2. This was tested on a BeagleBone
Blue using LEGO MINDSTORMS EV3 motors and this script[2].
[1]: https://lore.kernel.org/linux-iio/[email protected]/
[2]: https://github.com/dlech/linux-counter-ti-eqep-python/blob/3745b0840736248d8e60cc675a0f43558fcbb2af/test.py
v2 changes:
* Only clear interrupts that were handled.
* Don't set default QPOSMAX value.
* Don't error when setting QPOSMAX to 0.
* Use regmap_write() when appropriate.
* Validate watch channel.
* Use counter_priv().
---
drivers/counter/ti-eqep.c | 106 +++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 105 insertions(+), 1 deletion(-)
diff --git a/drivers/counter/ti-eqep.c b/drivers/counter/ti-eqep.c
index 072b11fd6b32..9f4ca219385c 100644
--- a/drivers/counter/ti-eqep.c
+++ b/drivers/counter/ti-eqep.c
@@ -7,6 +7,7 @@
#include <linux/bitops.h>
#include <linux/counter.h>
+#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/mod_devicetable.h>
#include <linux/module.h>
@@ -67,6 +68,44 @@
#define QEPCTL_UTE BIT(1)
#define QEPCTL_WDE BIT(0)
+#define QEINT_UTO BIT(11)
+#define QEINT_IEL BIT(10)
+#define QEINT_SEL BIT(9)
+#define QEINT_PCM BIT(8)
+#define QEINT_PCR BIT(7)
+#define QEINT_PCO BIT(6)
+#define QEINT_PCU BIT(5)
+#define QEINT_WTO BIT(4)
+#define QEINT_QDC BIT(3)
+#define QEINT_PHE BIT(2)
+#define QEINT_PCE BIT(1)
+
+#define QFLG_UTO BIT(11)
+#define QFLG_IEL BIT(10)
+#define QFLG_SEL BIT(9)
+#define QFLG_PCM BIT(8)
+#define QFLG_PCR BIT(7)
+#define QFLG_PCO BIT(6)
+#define QFLG_PCU BIT(5)
+#define QFLG_WTO BIT(4)
+#define QFLG_QDC BIT(3)
+#define QFLG_PHE BIT(2)
+#define QFLG_PCE BIT(1)
+#define QFLG_INT BIT(0)
+
+#define QCLR_UTO BIT(11)
+#define QCLR_IEL BIT(10)
+#define QCLR_SEL BIT(9)
+#define QCLR_PCM BIT(8)
+#define QCLR_PCR BIT(7)
+#define QCLR_PCO BIT(6)
+#define QCLR_PCU BIT(5)
+#define QCLR_WTO BIT(4)
+#define QCLR_QDC BIT(3)
+#define QCLR_PHE BIT(2)
+#define QCLR_PCE BIT(1)
+#define QCLR_INT BIT(0)
+
/* EQEP Inputs */
enum {
TI_EQEP_SIGNAL_QEPA, /* QEPA/XCLK */
@@ -238,12 +277,49 @@ static int ti_eqep_action_read(struct counter_device *counter,
}
}
+static int ti_eqep_events_configure(struct counter_device *counter)
+{
+ struct ti_eqep_cnt *priv = counter_priv(counter);
+ struct counter_event_node *event_node;
+ u32 qeint = 0;
+
+ list_for_each_entry(event_node, &counter->events_list, l) {
+ switch (event_node->event) {
+ case COUNTER_EVENT_OVERFLOW:
+ qeint |= QEINT_PCO;
+ break;
+ case COUNTER_EVENT_UNDERFLOW:
+ qeint |= QEINT_PCU;
+ break;
+ }
+ }
+
+ return regmap_write(priv->regmap16, QEINT, qeint);
+}
+
+static int ti_eqep_watch_validate(struct counter_device *counter,
+ const struct counter_watch *watch)
+{
+ switch (watch->event) {
+ case COUNTER_EVENT_OVERFLOW:
+ case COUNTER_EVENT_UNDERFLOW:
+ if (watch->channel != 0)
+ return -EINVAL;
+
+ return 0;
+ default:
+ return -EINVAL;
+ }
+}
+
static const struct counter_ops ti_eqep_counter_ops = {
.count_read = ti_eqep_count_read,
.count_write = ti_eqep_count_write,
.function_read = ti_eqep_function_read,
.function_write = ti_eqep_function_write,
.action_read = ti_eqep_action_read,
+ .events_configure = ti_eqep_events_configure,
+ .watch_validate = ti_eqep_watch_validate,
};
static int ti_eqep_position_ceiling_read(struct counter_device *counter,
@@ -354,6 +430,25 @@ static struct counter_count ti_eqep_counts[] = {
},
};
+static irqreturn_t ti_eqep_irq_handler(int irq, void *dev_id)
+{
+ struct counter_device *counter = dev_id;
+ struct ti_eqep_cnt *priv = counter_priv(counter);
+ u32 qflg;
+
+ regmap_read(priv->regmap16, QFLG, &qflg);
+
+ if (qflg & QFLG_PCO)
+ counter_push_event(counter, COUNTER_EVENT_OVERFLOW, 0);
+
+ if (qflg & QFLG_PCU)
+ counter_push_event(counter, COUNTER_EVENT_UNDERFLOW, 0);
+
+ regmap_write(priv->regmap16, QCLR, qflg);
+
+ return IRQ_HANDLED;
+}
+
static const struct regmap_config ti_eqep_regmap32_config = {
.name = "32-bit",
.reg_bits = 32,
@@ -376,7 +471,7 @@ static int ti_eqep_probe(struct platform_device *pdev)
struct counter_device *counter;
struct ti_eqep_cnt *priv;
void __iomem *base;
- int err;
+ int err, irq;
counter = devm_counter_alloc(dev, sizeof(*priv));
if (!counter)
@@ -397,6 +492,15 @@ static int ti_eqep_probe(struct platform_device *pdev)
if (IS_ERR(priv->regmap16))
return PTR_ERR(priv->regmap16);
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0)
+ return irq;
+
+ err = devm_request_threaded_irq(dev, irq, NULL, ti_eqep_irq_handler,
+ IRQF_ONESHOT, dev_name(dev), counter);
+ if (err < 0)
+ return dev_err_probe(dev, err, "failed to request IRQ\n");
+
counter->name = dev_name(dev);
counter->parent = dev;
counter->ops = &ti_eqep_counter_ops;
---
base-commit: bb3f1c5fc434b0b177449f7f73ea9b112b397dd1
change-id: 20240609-counter-ti-eqep-over-under-events-8e7ace53d35a
On Sun, Jun 09, 2024 at 04:49:33PM -0500, David Lechner wrote:
> This adds support to the TI eQEP counter driver for subscribing to
> overflow and underflow events using the counter chrdev interface.
>
> Signed-off-by: David Lechner <[email protected]>
> ---
> This is split out from a series that was sent a few years back [1] that
> I never finished, so I'm calling it v2. This was tested on a BeagleBone
> Blue using LEGO MINDSTORMS EV3 motors and this script[2].
>
> [1]: https://lore.kernel.org/linux-iio/[email protected]/
> [2]: https://github.com/dlech/linux-counter-ti-eqep-python/blob/3745b0840736248d8e60cc675a0f43558fcbb2af/test.py
>
> v2 changes:
> * Only clear interrupts that were handled.
> * Don't set default QPOSMAX value.
> * Don't error when setting QPOSMAX to 0.
> * Use regmap_write() when appropriate.
> * Validate watch channel.
> * Use counter_priv().
Hi David,
It's nice to see progress on this again. I remember there being some
sort of interrupt storm if QPOSMAX was set to 0. Is that still the case,
or was it resolved with the changes in this version?
Willia Breathitt Gray
On 6/15/24 2:01 AM, William Breathitt Gray wrote:
> On Sun, Jun 09, 2024 at 04:49:33PM -0500, David Lechner wrote:
>> This adds support to the TI eQEP counter driver for subscribing to
>> overflow and underflow events using the counter chrdev interface.
>>
>> Signed-off-by: David Lechner <[email protected]>
>> ---
>> This is split out from a series that was sent a few years back [1] that
>> I never finished, so I'm calling it v2. This was tested on a BeagleBone
>> Blue using LEGO MINDSTORMS EV3 motors and this script[2].
>>
>> [1]: https://lore.kernel.org/linux-iio/[email protected]/
>> [2]: https://github.com/dlech/linux-counter-ti-eqep-python/blob/3745b0840736248d8e60cc675a0f43558fcbb2af/test.py
>>
>> v2 changes:
>> * Only clear interrupts that were handled.
>> * Don't set default QPOSMAX value.
>> * Don't error when setting QPOSMAX to 0.
>> * Use regmap_write() when appropriate.
>> * Validate watch channel.
>> * Use counter_priv().
>
> Hi David,
>
> It's nice to see progress on this again. I remember there being some
> sort of interrupt storm if QPOSMAX was set to 0. Is that still the case,
> or was it resolved with the changes in this version?
>
> Willia Breathitt Gray
I haven't tried it with the rest of the old series yet, but with this
patch, it is not a problem to set QPOSMAX (ceiling) to 0.
On Sun, 09 Jun 2024 16:49:33 -0500, David Lechner wrote:
> This adds support to the TI eQEP counter driver for subscribing to
> overflow and underflow events using the counter chrdev interface.
>
>
Applied, thanks!
[1/1] counter: ti-eqep: implement over/underflow events
commit: 1c30c6d024726e2af2a5608474bf1fb6937f5740
Best regards,
--
William Breathitt Gray <[email protected]>