How stable is hyperthreading under kernel-2.4.18? I compiled the kernel
for the Pentium4 and dmesg shows CPU0 and CPU1, but CPU1 is disabled.
How do I enable CPU1 and should I?? Do other libraries need to be updated
or is hyperthreading like having a two processor box?
--Lou
On Sat, Jun 01, 2002 at 08:40:44PM -0400, Louis Garcia wrote:
> How stable is hyperthreading under kernel-2.4.18? I compiled the kernel
> for the Pentium4 and dmesg shows CPU0 and CPU1, but CPU1 is disabled.
> How do I enable CPU1 and should I?? Do other libraries need to be updated
> or is hyperthreading like having a two processor box?
acpismp=force seems to work on 2.4 here.
Cheers,
Bill
Did I forget to say this is a UP box? I just wanted to know if
hyperthreading is stable for a UP P4 box. Will acpismp=force still help?
Thanks, --Lou
On Sat, 2002-06-01 at 20:50, William Lee Irwin III wrote:
> On Sat, Jun 01, 2002 at 08:40:44PM -0400, Louis Garcia wrote:
> > How stable is hyperthreading under kernel-2.4.18? I compiled the kernel
> > for the Pentium4 and dmesg shows CPU0 and CPU1, but CPU1 is disabled.
> > How do I enable CPU1 and should I?? Do other libraries need to be updated
> > or is hyperthreading like having a two processor box?
>
> acpismp=force seems to work on 2.4 here.
>
>
> Cheers,
> Bill
On Sat, Jun 01, 2002 at 09:14:23PM -0400, Louis Garcia wrote:
> Did I forget to say this is a UP box? I just wanted to know if
> hyperthreading is stable for a UP P4 box. Will acpismp=force still help?
> Thanks, --Lou
Not sure, I'd imagine if you had an SMP kernel it would work.
Cheers,
Bill
On 1 Jun 2002, Louis Garcia wrote:
> Did I forget to say this is a UP box? I just wanted to know if
> hyperthreading is stable for a UP P4 box. Will acpismp=force still help?
CONFIG_SMP must be on. the fact that you have a single CPU does not mean
that spinlocks have to resolve to {} with ht
- Davide
I was just thinking about that. Do you now if this has a real speed
improvement?
--Lou
On Sat, 2002-06-01 at 21:44, Davide Libenzi wrote:
> On 1 Jun 2002, Louis Garcia wrote:
>
> > Did I forget to say this is a UP box? I just wanted to know if
> > hyperthreading is stable for a UP P4 box. Will acpismp=force still help?
>
> CONFIG_SMP must be on. the fact that you have a single CPU does not mean
> that spinlocks have to resolve to {} with ht
>
>
>
> - Davide
>
>
On 1 Jun 2002, Louis Garcia wrote:
> I was just thinking about that. Do you now if this has a real speed
> improvement?
intel claims up to 30-40% but i've never tried it. the bottleneck is that
they share fsb and cache but in any case having an extra exec-path might
help more than demage. this is for your sleepless nights :
http://www.intel.com/technology/itj/2002/volume06issue01/art01_hyper/vol6iss1_art01.pdf
- Davide
Does anyone know if the P4 Xeon's use HT as well, or is it mainly for UP
DP boxes?
On Sat, 2002-06-01 at 22:04, Davide Libenzi wrote:
> On 1 Jun 2002, Louis Garcia wrote:
>
> > I was just thinking about that. Do you now if this has a real speed
> > improvement?
>
> intel claims up to 30-40% but i've never tried it. the bottleneck is that
> they share fsb and cache but in any case having an extra exec-path might
> help more than demage. this is for your sleepless nights :
>
> http://www.intel.com/technology/itj/2002/volume06issue01/art01_hyper/vol6iss1_art01.pdf
>
>
>
>
> - Davide
>
>
> -
> To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> the body of a message to [email protected]
> More majordomo info at http://vger.kernel.org/majordomo-info.html
> Please read the FAQ at http://www.tux.org/lkml/
My guess would be yes. Since the P4 and the P4 Xeon is the same core
chip. The Xeon's just have more cache.
--Lou
On Sun, 2002-06-02 at 01:12, Austin Gonyou wrote:
> Does anyone know if the P4 Xeon's use HT as well, or is it mainly for UP
> DP boxes?
>
>
>
> On Sat, 2002-06-01 at 22:04, Davide Libenzi wrote:
> > On 1 Jun 2002, Louis Garcia wrote:
> >
> > > I was just thinking about that. Do you now if this has a real speed
> > > improvement?
> >
> > intel claims up to 30-40% but i've never tried it. the bottleneck is that
> > they share fsb and cache but in any case having an extra exec-path might
> > help more than demage. this is for your sleepless nights :
> >
> > http://www.intel.com/technology/itj/2002/volume06issue01/art01_hyper/vol6iss1_art01.pdf
> >
> >
> >
> >
> > - Davide
> >
> >
> > -
> > To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
> > the body of a message to [email protected]
> > More majordomo info at http://vger.kernel.org/majordomo-info.html
> > Please read the FAQ at http://www.tux.org/lkml/
On Sun, 2002-06-02 at 08:12, Austin Gonyou wrote:
> Does anyone know if the P4 Xeon's use HT as well, or is it mainly for UP
> DP boxes?
As per the link quoted below, HT was first intriduced on the Xeon line.
> > http://www.intel.com/technology/itj/2002/volume06issue01/art01_hyper/vol6iss1_art01.pdf
--
Gilad Ben-Yossef <[email protected]>
Code mangler, senior coffee drinker and VP SIGSEGV
Qlusters ltd.
"A billion flies _can_ be wrong - I'd rather eat lamb chops than shit."
-- Linus Torvalds on lkml
After reading that doc, I've found it's certainly a good explanation of
what HT is and how it (*mostly*?) works. Should be interesting to see
when the 6650 gets here what happens then.
On Sun, 2002-06-02 at 03:32, Gilad Ben-Yossef wrote:
> On Sun, 2002-06-02 at 08:12, Austin Gonyou wrote:
> > Does anyone know if the P4 Xeon's use HT as well, or is it mainly for UP
> > DP boxes?
>
> As per the link quoted below, HT was first intriduced on the Xeon line.
>
> > > http://www.intel.com/technology/itj/2002/volume06issue01/art01_hyper/vol6iss1_art01.pdf
>
> --
> Gilad Ben-Yossef <[email protected]>
> Code mangler, senior coffee drinker and VP SIGSEGV
> Qlusters ltd.
>
> "A billion flies _can_ be wrong - I'd rather eat lamb chops than shit."
> -- Linus Torvalds on lkml
>
>
>
>
On Saturday 01 June 2002 09:39 pm, Louis Garcia wrote:
> I was just thinking about that. Do you now if this has a real speed
> improvement?
As with most speed improvements, it depends on your workload.
Hyper-threading is a way of keeping more execution cores busy more of the
time, hopefully without putting as much pressure on the cache and memory bus
(which are the REAL performance bottlenecks with a clock multipler of 18X or
so) quite as badly as VLIW/EPIC seem to.
If you're running something like distributed.net that has a small enough
cache footprint, hyperthreading might be really nice. But seti@home will
probably suck: it flushes cache contents 24/7.
More to the point, one of the recurring arguments in favor of dual processors
is that having a second proc to handle interrupt-triggered asynchronous work
(disk activity,mouse move, keypress, network packet) can, in theory,
significantly lower your latency.
And in the future, it allows them to pull the Xeon trick of blowing a HUGE
transistor budget on L1 or on-die L2 cache (next time they rev their
manufacturing process), and potentially get some actual real-world benefit
out of it (as something other than compensating for their brain-dead SMP
memory bus design).
The main down side (other than two threads fighting for the same cache space,
although interrupts and context switches are going to do that ANYWAY, so...)
is probably less locality of reference about memory access, so you wind up
doing more bank switching and such, adding latency to main memory accesses.
There's a great old series about how memory works on Ars Technica (from SRAM
and DRAM to DDR vs Rambus...):
Part 1: http://www.arstechnica.com/paedia/r/ram_guide/ram_guide.part1-1.html
Part 2: http://www.arstechnica.com/paedia/r/ram_guide/ram_guide.part2-1.html
Part 3: http://www.arstechnica.com/paedia/r/ram_guide/ram_guide.part3-1.html
(And once again, a new technology emerges for which DDR is just a little bit
better than Rambus... :)
</rampant opinion>
Rob