Met a problem in my research. I run some code on a
Xeon
dual-processor machine. It seems to me that there is a
cache coherence problem. As I am not so familiar
to this topic, I would like to ask some experts about
the following questions.
1. Do Xeon processors have hardware mechanisms to
maintain cache coherence?
2. Does the SMP kernel handle the cache coherence
problem
3. What should I do if both of them don't handle cache
coherence.
Thanks.
Frank Samuel
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On Mon, Aug 19, 2002 at 11:21:21AM -0700, Xuehua Chen wrote:
> Met a problem in my research. I run some code on a
> Xeon dual-processor machine. It seems to me that there is
> a cache coherence problem. As I am not so familiar
> to this topic, I would like to ask some experts about
> the following questions.
>
> 1. Do Xeon processors have hardware mechanisms to
> maintain cache coherence?
Yes, in usual closely coupled SMP systems.
> 2. Does the SMP kernel handle the cache coherence
> problem
In its own ways, yes. It is relying on hardware doing
it in major part.
> 3. What should I do if both of them don't handle cache
> coherence.
Report the issue with lots of technical details
on [email protected], and possibly continue
discussion there.
Data like:
- What machine, whose motherboard ?
- How much memory ?
- What steppings are the processors ? (not same ?)
- How you configured the kernel ?
(Not quite the entire .config file, just first
50 lines or so telling processor details.)
And most importantly:
- Describe why do you suspect there is cache-coherence
problem in the system ? In the kernel side, or
in your application ? How it is manifesting itself ?
> Thanks.
> Frank Samuel
/Matti Aarnio
On Mon, 2002-08-19 at 19:21, Xuehua Chen wrote:
> 1. Do Xeon processors have hardware mechanisms to
> maintain cache coherence?
Yes
> 2. Does the SMP kernel handle the cache coherence
> problem
The kernel has to manage side issues (TLB shootdown etc)
> 3. What should I do if both of them don't handle cache
> coherence.
Debug your code. It is possible you are hitting a kernel bug but its
extremely unlikely.
On Monday 19 August 2002 11:21 am, Xuehua Chen wrote:
> Met a problem in my research. I run some code on a
> Xeon
> dual-processor machine. It seems to me that there is a
> cache coherence problem. As I am not so familiar
> to this topic, I would like to ask some experts about
> the following questions.
>
> 1. Do Xeon processors have hardware mechanisms to
> maintain cache coherence?
Someone at Intel can correct me, but I believe they use a modified MESI cache
coherency protocol. Note that this coherency does not guarantee indivisible
read-modify-write operations unless atomic opcodes are used. (xchg or lock
<opcode>)
> 2. Does the SMP kernel handle the cache coherence
> problem
See Alan's and others' postings. The kernel relies on the hardware to keep
its act straight, then takes care of MMU coherency.
> 3. What should I do if both of them don't handle cache
> coherence.
See 1 and 2. Consider using futexes or some other mutex mechanism appropriate
to user or kernel code.
> Thanks.
>
> Frank Samuel
--
James Cleverdon
IBM xSeries Linux Solutions
{jamesclv(Unix, preferred), cleverdj(Notes)} at us dot ibm dot com