Hi,
I read the Intel IA-32 developer's manual recently, and I found
the cache lines for L1 and L2 caches in Pentium4 are 64 bytes
wide, but the thing make me confused is that the default value
CONFIG_X86_L1_CACHE_SHIFT option in 2.4.x kernel is 7, why it's
not 6? Any expanation about this would be appreciated!
--
Best regards,
Michael Chen mailto:[email protected]
michaelc wrote:
> I read the Intel IA-32 developer's manual recently, and I found
> the cache lines for L1 and L2 caches in Pentium4 are 64 bytes
> wide, but the thing make me confused is that the default value
> CONFIG_X86_L1_CACHE_SHIFT option in 2.4.x kernel is 7, why it's
> not 6? Any expanation about this would be appreciated!
I don't recall seeing an answer to this.
Was there one?
Cheers,
-- Jamie
What's even more interesting is the following:
tux:/usr/src/linux-2.6.0-test3 # grep -r "CONFIG_X86_L1_CACHE_SHIFT" *
arch/i386/defconfig:CONFIG_X86_L1_CACHE_SHIFT=7
arch/x86_64/defconfig:CONFIG_X86_L1_CACHE_SHIFT=6
include/asm-x86_64/cache.h:#define L1_CACHE_SHIFT
(CONFIG_X86_L1_CACHE_SHIFT)
include/linux/autoconf.h:#define CONFIG_X86_L1_CACHE_SHIFT 5
include/asm-i386/cache.h:#define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
include/asm/cache.h:#define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
include/config/x86/l1/cache/shift.h:#define CONFIG_X86_L1_CACHE_SHIFT 5
tux:/usr/src/linux-2.6.0-test3 #
Life sure is interesting.
Cheers,
Dave
Jamie Lokier wrote:
> michaelc wrote:
>
>> I read the Intel IA-32 developer's manual recently, and I found
>> the cache lines for L1 and L2 caches in Pentium4 are 64 bytes
>> wide, but the thing make me confused is that the default value
>> CONFIG_X86_L1_CACHE_SHIFT option in 2.4.x kernel is 7, why it's
>> not 6? Any expanation about this would be appreciated!
>
>
> I don't recall seeing an answer to this.
> Was there one?
>
> Cheers,
> -- Jamie
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On Sun, Aug 17, 2003 at 09:25:35PM +0100, Jamie Lokier wrote:
> michaelc wrote:
> > I read the Intel IA-32 developer's manual recently, and I found
> > the cache lines for L1 and L2 caches in Pentium4 are 64 bytes
> > wide, but the thing make me confused is that the default value
> > CONFIG_X86_L1_CACHE_SHIFT option in 2.4.x kernel is 7, why it's
> > not 6? Any expanation about this would be appreciated!
>
> I don't recall seeing an answer to this.
> Was there one?
ISTR it was something to do with how the P4 cachelines are laid out.
Something like 2 sectors of 64 byte lines.
Dave
--
Dave Jones http://www.codemonkey.org.uk
On Sun, Aug 17, 2003 at 04:36:51PM -0400, David B. Stevens wrote:
> What's even more interesting is the following:
why ?
> tux:/usr/src/linux-2.6.0-test3 # grep -r "CONFIG_X86_L1_CACHE_SHIFT" *
> arch/i386/defconfig:CONFIG_X86_L1_CACHE_SHIFT=7
> arch/x86_64/defconfig:CONFIG_X86_L1_CACHE_SHIFT=6
correct default values for P4 and Hammer respectively.
> include/asm-x86_64/cache.h:#define L1_CACHE_SHIFT
> (CONFIG_X86_L1_CACHE_SHIFT)
Looks sane.
> include/linux/autoconf.h:#define CONFIG_X86_L1_CACHE_SHIFT 5
compile-time generated from .config
> include/asm-i386/cache.h:#define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
> include/asm/cache.h:#define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
looks sane
> include/config/x86/l1/cache/shift.h:#define CONFIG_X86_L1_CACHE_SHIFT 5
compile time generated from .config.
Dave
--
Dave Jones http://www.codemonkey.org.uk
Jamie Lokier wrote:
> michaelc wrote:
>
>> I read the Intel IA-32 developer's manual recently, and I found
>> the cache lines for L1 and L2 caches in Pentium4 are 64 bytes
>> wide, but the thing make me confused is that the default value
>> CONFIG_X86_L1_CACHE_SHIFT option in 2.4.x kernel is 7, why it's
>> not 6? Any expanation about this would be appreciated!
>
>
> I don't recall seeing an answer to this.
> Was there one?
There is some confusion about P4 cache line size but
Intel Software Developer's Manual VOL 1
Page 2.12, Par 2.6:
"128-byte cache line size
- Two 64-byte sectors"
regards,
Philippe Elie
Dave,
Thanks that explains it.
The layout as well as the size needs to be taken into account.
Cheers,
Dave
Dave Jones wrote:
> On Sun, Aug 17, 2003 at 04:36:51PM -0400, David B. Stevens wrote:
> > What's even more interesting is the following:
>
> why ?
>
> > tux:/usr/src/linux-2.6.0-test3 # grep -r "CONFIG_X86_L1_CACHE_SHIFT" *
> > arch/i386/defconfig:CONFIG_X86_L1_CACHE_SHIFT=7
> > arch/x86_64/defconfig:CONFIG_X86_L1_CACHE_SHIFT=6
>
> correct default values for P4 and Hammer respectively.
>
> > include/asm-x86_64/cache.h:#define L1_CACHE_SHIFT
> > (CONFIG_X86_L1_CACHE_SHIFT)
>
> Looks sane.
>
> > include/linux/autoconf.h:#define CONFIG_X86_L1_CACHE_SHIFT 5
>
> compile-time generated from .config
>
> > include/asm-i386/cache.h:#define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
> > include/asm/cache.h:#define L1_CACHE_SHIFT (CONFIG_X86_L1_CACHE_SHIFT)
>
> looks sane
>
> > include/config/x86/l1/cache/shift.h:#define CONFIG_X86_L1_CACHE_SHIFT 5
>
> compile time generated from .config.
>
> Dave
>