Add support to tg3 for bcm5752 hardware. Also clean-up a lot
of multi-way if statements and replace them with checks of flags
representing classes of tg3 hardware.
Patches to follow...
Replace a number of three-way if statements checking for 5705, 5750,
and 5752 to reference the equivalent TG3_FLG2_5705_PLUS flag instead.
Signed-off-by: John W. Linville <[email protected]>
---
drivers/net/tg3.c | 16 ++++------------
1 files changed, 4 insertions(+), 12 deletions(-)
--- bcm5752-support/drivers/net/tg3.c.orig 2005-04-08 17:42:28.059553796 -0400
+++ bcm5752-support/drivers/net/tg3.c 2005-04-08 17:42:16.584131525 -0400
@@ -85,9 +85,7 @@
/* hardware minimum and maximum for a single frame's data payload */
#define TG3_MIN_MTU 60
#define TG3_MAX_MTU(tp) \
- ((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 && \
- GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 && \
- GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) ? 9000 : 1500)
+ (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 9000 : 1500)
/* These numbers seem to be hard coded in the NIC firmware somehow.
* You can't change the ring sizes, but you can change where you place
@@ -863,9 +861,7 @@ out:
if ((tp->phy_id & PHY_ID_MASK) == PHY_ID_BCM5401) {
/* Cannot do read-modify-write on 5401 */
tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
- } else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
- GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
- GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) {
+ } else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
u32 phy_reg;
/* Set bit 14 with read-modify-write to preserve other bits */
@@ -877,9 +873,7 @@ out:
/* Set phy register 0x10 bit 0 to high fifo elasticity to support
* jumbo frames transmission.
*/
- if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
- GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
- GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) {
+ if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS)) {
u32 phy_reg;
if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
@@ -8483,9 +8477,7 @@ static int __devinit tg3_test_dma(struct
/* DMA read watermark not used on PCIE */
tp->dma_rwctrl |= 0x00180000;
} else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+ if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
tp->dma_rwctrl |= 0x003f0000;
else
tp->dma_rwctrl |= 0x003f000f;
Use check of TG3_FLG2_5750_PLUS in tg3_get_invariants to set
TG3_FLG2_5705_PLUS flag.
Signed-off-by: John W. Linville <[email protected]>
---
drivers/net/tg3.c | 9 ++++-----
1 files changed, 4 insertions(+), 5 deletions(-)
--- bcm5752-support/drivers/net/tg3.c.orig 2005-04-08 18:13:24.632333096 -0400
+++ bcm5752-support/drivers/net/tg3.c 2005-04-08 18:13:19.559031079 -0400
@@ -7928,15 +7928,14 @@ static int __devinit tg3_get_invariants(
tp->pci_hdr_type = (cacheline_sz_reg >> 16) & 0xff;
tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
- if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
- (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
- (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752))
- tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
-
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
+ if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
+ (tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
+ tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
+
if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
Add hard-coded definition of bcm5752 PCI ID to tg3_pci_tbl.
Signed-off-by: John W. Linville <[email protected]>
---
Next patch will change entry to use pci_ids.h-based definition.
drivers/net/tg3.c | 2 ++
1 files changed, 2 insertions(+)
--- bcm5752-support/drivers/net/tg3.c.orig 2005-04-08 17:30:08.886197282 -0400
+++ bcm5752-support/drivers/net/tg3.c 2005-04-08 17:30:17.113065813 -0400
@@ -206,6 +206,8 @@ static struct pci_device_id tg3_pci_tbl[
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
+ { PCI_VENDOR_ID_BROADCOM, 0x1600, /* TIGON3_5752 */
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753M,
Define TG3_FLG2_5750_PLUS flag and set it in tg3_get_invariants for
ASIC_REV_5750 or ASIC_REV_5752.
Signed-off-by: John W. Linville <[email protected]>
---
drivers/net/tg3.c | 4 ++++
drivers/net/tg3.h | 1 +
2 files changed, 5 insertions(+)
--- bcm5752-support/drivers/net/tg3.c.orig 2005-04-08 17:47:31.186930125 -0400
+++ bcm5752-support/drivers/net/tg3.c 2005-04-08 17:47:16.409928291 -0400
@@ -7951,6 +7951,10 @@ static int __devinit tg3_get_invariants(
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+ tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
+
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
--- bcm5752-support/drivers/net/tg3.h.orig 2005-04-08 17:47:35.536341972 -0400
+++ bcm5752-support/drivers/net/tg3.h 2005-04-08 17:44:48.578234813 -0400
@@ -2101,6 +2101,7 @@ struct tg3 {
#define TG3_FLG2_HW_TSO 0x00010000
#define TG3_FLG2_SERDES_PREEMPHASIS 0x00020000
#define TG3_FLG2_5705_PLUS 0x00040000
+#define TG3_FLG2_5750_PLUS 0x00080000
u32 split_mode_max_reqs;
#define SPLIT_MODE_5704_MAX_REQ 3
Replace existing ASIC_REV_5752 definition with ASIC_REV_5752_A0,
and add definition for ASIC_REV_5752_A1. Then, add ASIC_REV_5752_A1
to check for setting TG3_FLG2_5750_PLUS in tg3_get_invariants.
Signed-off-by: John W. Linville <[email protected]>
---
drivers/net/tg3.c | 3 ++-
drivers/net/tg3.h | 5 ++++-
2 files changed, 6 insertions(+), 2 deletions(-)
--- bcm5752-support/drivers/net/tg3.c.orig 2005-04-12 14:19:06.302429500 -0400
+++ bcm5752-support/drivers/net/tg3.c 2005-04-12 14:17:50.963846711 -0400
@@ -7929,7 +7929,8 @@ static int __devinit tg3_get_invariants(
tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752_A0 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752_A1)
tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
--- bcm5752-support/drivers/net/tg3.h.orig 2005-04-12 14:19:06.288431435 -0400
+++ bcm5752-support/drivers/net/tg3.h 2005-04-12 14:17:50.981844223 -0400
@@ -125,6 +125,8 @@
#define CHIPREV_ID_5750_A0 0x4000
#define CHIPREV_ID_5750_A1 0x4001
#define CHIPREV_ID_5750_A3 0x4003
+#define CHIPREV_ID_5752_A0 0x5000
+#define CHIPREV_ID_5752_A1 0x6001
#define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
#define ASIC_REV_5700 0x07
#define ASIC_REV_5701 0x00
@@ -132,7 +134,8 @@
#define ASIC_REV_5704 0x02
#define ASIC_REV_5705 0x03
#define ASIC_REV_5750 0x04
-#define ASIC_REV_5752 0x05
+#define ASIC_REV_5752_A0 0x05
+#define ASIC_REV_5752_A1 0x06
#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
#define CHIPREV_5700_AX 0x70
#define CHIPREV_5700_BX 0x71
Add proper entry for bcm5752 PCI ID to pci_ids.h, and use it in tg3.
Signed-off-by: John W. Linville <[email protected]>
---
I did this separately in case patches like this (i.e. new PCI IDs)
need to come from more "official" sources.
drivers/net/tg3.c | 2 +-
include/linux/pci_ids.h | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
--- bcm5752-support/drivers/net/tg3.c.orig 2005-04-08 17:35:34.834372048 -0400
+++ bcm5752-support/drivers/net/tg3.c 2005-04-08 17:34:42.536563710 -0400
@@ -206,7 +206,7 @@ static struct pci_device_id tg3_pci_tbl[
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5751F,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
- { PCI_VENDOR_ID_BROADCOM, 0x1600, /* TIGON3_5752 */
+ { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5752,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753,
PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },
--- bcm5752-support/include/linux/pci_ids.h.orig 2005-04-08 17:30:45.655140363 -0400
+++ bcm5752-support/include/linux/pci_ids.h 2005-04-08 17:31:52.965883217 -0400
@@ -2065,6 +2065,7 @@
#define PCI_DEVICE_ID_AFAVLAB_P030 0x2182
#define PCI_VENDOR_ID_BROADCOM 0x14e4
+#define PCI_DEVICE_ID_TIGON3_5752 0x1600
#define PCI_DEVICE_ID_TIGON3_5700 0x1644
#define PCI_DEVICE_ID_TIGON3_5701 0x1645
#define PCI_DEVICE_ID_TIGON3_5702 0x1646
Rewrite checks in tg3_get_invariants to use TG3_FLG2_5705_PLUS and
TG3_FLG2_5750_PLUS flags.
Signed-off-by: John W. Linville <[email protected]>
---
drivers/net/tg3.c | 7 ++-----
1 files changed, 2 insertions(+), 5 deletions(-)
--- bcm5752-support/drivers/net/tg3.c.orig 2005-04-08 18:11:46.207874683 -0400
+++ bcm5752-support/drivers/net/tg3.c 2005-04-08 18:11:36.696183379 -0400
@@ -7937,8 +7937,7 @@ static int __devinit tg3_get_invariants(
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+ if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
@@ -8068,9 +8067,7 @@ static int __devinit tg3_get_invariants(
if (tp->pci_chip_rev_id == CHIPREV_ID_5704_A0)
tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+ if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)
tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
/* Only 5701 and later support tagged irq status mode.
Rewrite of a couple of troublesome multi-way if statements to use
TG3_FLG2_5705_PLUS flag.
Signed-off-by: John W. Linville <[email protected]>
---
drivers/net/tg3.c | 12 ++++--------
1 files changed, 4 insertions(+), 8 deletions(-)
--- bcm5752-support/drivers/net/tg3.c.orig 2005-04-08 18:00:31.886220435 -0400
+++ bcm5752-support/drivers/net/tg3.c 2005-04-08 18:08:55.969298725 -0400
@@ -5237,10 +5237,8 @@ static int tg3_reset_hw(struct tg3 *tp)
RDMAC_MODE_LNGREAD_ENAB);
if (tp->tg3_flags & TG3_FLAG_SPLIT_MODE)
rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
- if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
- tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
- (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)) {
+ if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
+ tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
(tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
@@ -5353,10 +5351,8 @@ static int tg3_reset_hw(struct tg3 *tp)
WDMAC_MODE_FIFOURUN_ENAB | WDMAC_MODE_FIFOOREAD_ENAB |
WDMAC_MODE_LNGREAD_ENAB);
- if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
- tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
- (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)) {
+ if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
+ tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) {
if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
(tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
Track-down all references to ASIC_REV_5750 and mirror them with
references to the newly defined ASIC_REV_5752.
Signed-off-by: John W. Linville <[email protected]>
---
drivers/net/tg3.c | 63 ++++++++++++++++++++++++++++++++++++------------------
1 files changed, 42 insertions(+), 21 deletions(-)
--- bcm5752-support/drivers/net/tg3.c.orig 2005-04-08 17:28:59.660670261 -0400
+++ bcm5752-support/drivers/net/tg3.c 2005-04-08 17:29:05.039934450 -0400
@@ -86,7 +86,8 @@
#define TG3_MIN_MTU 60
#define TG3_MAX_MTU(tp) \
((GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 && \
- GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) ? 9000 : 1500)
+ GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 && \
+ GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) ? 9000 : 1500)
/* These numbers seem to be hard coded in the NIC firmware somehow.
* You can't change the ring sizes, but you can change where you place
@@ -861,7 +862,8 @@ out:
/* Cannot do read-modify-write on 5401 */
tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
} else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
- GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
+ GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
+ GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) {
u32 phy_reg;
/* Set bit 14 with read-modify-write to preserve other bits */
@@ -874,7 +876,8 @@ out:
* jumbo frames transmission.
*/
if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 &&
- GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750) {
+ GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
+ GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752) {
u32 phy_reg;
if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &phy_reg))
@@ -1068,7 +1071,8 @@ static int tg3_set_power_state(struct tg
mac_mode = MAC_MODE_PORT_MODE_TBI;
}
- if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750)
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
+ GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752)
tw32(MAC_LED_CTRL, tp->led_ctrl);
if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
@@ -3967,7 +3971,8 @@ static int tg3_chip_reset(struct tg3 *tp
tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
}
}
@@ -5041,7 +5046,8 @@ static int tg3_reset_hw(struct tg3 *tp)
tw32(GRC_MISC_CFG, val);
/* Initialize MBUF/DESC pool. */
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
/* Do nothing. */
} else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
@@ -5240,7 +5246,8 @@ static int tg3_reset_hw(struct tg3 *tp)
rdmac_mode |= RDMAC_MODE_SPLIT_ENABLE;
if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
- (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)) {
+ (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)) {
if (tp->tg3_flags2 & TG3_FLG2_TSO_CAPABLE &&
(tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
@@ -5355,7 +5362,8 @@ static int tg3_reset_hw(struct tg3 *tp)
if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
tp->pci_chip_rev_id != CHIPREV_ID_5705_A0) ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+ (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)) {
if ((tp->tg3_flags & TG3_FLG2_TSO_CAPABLE) &&
(tp->pci_chip_rev_id == CHIPREV_ID_5705_A1 ||
tp->pci_chip_rev_id == CHIPREV_ID_5705_A2)) {
@@ -7028,7 +7036,8 @@ static void __devinit tg3_get_nvram_info
tw32(NVRAM_CFG1, nvcfg1);
}
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
tp->nvram_jedecnum = JEDEC_ATMEL;
@@ -7093,7 +7102,8 @@ static void __devinit tg3_nvram_init(str
GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
tp->tg3_flags |= TG3_FLAG_NVRAM;
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
u32 nvaccess = tr32(NVRAM_ACCESS);
tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
@@ -7102,7 +7112,8 @@ static void __devinit tg3_nvram_init(str
tg3_get_nvram_info(tp);
tg3_get_nvram_size(tp);
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
u32 nvaccess = tr32(NVRAM_ACCESS);
tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
@@ -7195,7 +7206,8 @@ static int tg3_nvram_read(struct tg3 *tp
tg3_nvram_lock(tp);
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
u32 nvaccess = tr32(NVRAM_ACCESS);
tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
@@ -7210,7 +7222,8 @@ static int tg3_nvram_read(struct tg3 *tp
tg3_nvram_unlock(tp);
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
u32 nvaccess = tr32(NVRAM_ACCESS);
tw32_f(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
@@ -7438,7 +7451,8 @@ static int tg3_nvram_write_block(struct
tg3_nvram_lock(tp);
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
u32 nvaccess = tr32(NVRAM_ACCESS);
tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
@@ -7463,7 +7477,8 @@ static int tg3_nvram_write_block(struct
grc_mode = tr32(GRC_MODE);
tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
u32 nvaccess = tr32(NVRAM_ACCESS);
tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
@@ -7581,7 +7596,8 @@ static int __devinit tg3_phy_probe(struc
} else
eeprom_phy_id = 0;
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) {
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
SHASTA_EXT_LED_MODE_MASK);
} else
@@ -7634,7 +7650,8 @@ static int __devinit tg3_phy_probe(struc
if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
}
if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
@@ -7932,10 +7949,12 @@ static int __devinit tg3_get_invariants(
tp->pci_bist = (cacheline_sz_reg >> 24) & 0xff;
if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
- (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750))
+ (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750) ||
+ (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752))
tp->tg3_flags2 |= TG3_FLG2_5705_PLUS;
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
+ if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
tp->tg3_flags2 |= TG3_FLG2_HW_TSO;
if (pci_find_capability(tp->pdev, PCI_CAP_ID_EXP) != 0)
@@ -8066,7 +8085,8 @@ static int __devinit tg3_get_invariants(
tp->tg3_flags2 |= TG3_FLG2_PHY_5704_A0_BUG;
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
tp->tg3_flags2 |= TG3_FLG2_PHY_BER_BUG;
/* Only 5701 and later support tagged irq status mode.
@@ -8462,7 +8482,8 @@ static int __devinit tg3_test_dma(struct
tp->dma_rwctrl |= 0x00180000;
} else if (!(tp->tg3_flags & TG3_FLAG_PCIX_MODE)) {
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750)
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
+ GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
tp->dma_rwctrl |= 0x003f0000;
else
tp->dma_rwctrl |= 0x003f000f;
Replace a number of two-way if statements checking for 5750, and/or
5752 to reference the newly-defined TG3_FLG2_5750_PLUS flag instead.
Signed-off-by: John W. Linville <[email protected]>
---
drivers/net/tg3.c | 38 +++++++++++++-------------------------
1 files changed, 13 insertions(+), 25 deletions(-)
--- bcm5752-support/drivers/net/tg3.c.orig 2005-04-08 17:57:50.096149244 -0400
+++ bcm5752-support/drivers/net/tg3.c 2005-04-08 17:57:10.716485067 -0400
@@ -1067,8 +1067,7 @@ static int tg3_set_power_state(struct tg
mac_mode = MAC_MODE_PORT_MODE_TBI;
}
- if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5750 &&
- GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5752)
+ if (!(tp->tg3_flags2 & TG3_FLG2_5750_PLUS))
tw32(MAC_LED_CTRL, tp->led_ctrl);
if (((power_caps & PCI_PM_CAP_PME_D3cold) &&
@@ -3967,8 +3966,7 @@ static int tg3_chip_reset(struct tg3 *tp
tg3_read_mem(tp, NIC_SRAM_DATA_CFG, &nic_cfg);
if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+ if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
}
}
@@ -5042,8 +5040,7 @@ static int tg3_reset_hw(struct tg3 *tp)
tw32(GRC_MISC_CFG, val);
/* Initialize MBUF/DESC pool. */
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+ if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
/* Do nothing. */
} else if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
tw32(BUFMGR_MB_POOL_ADDR, NIC_SRAM_MBUF_POOL_BASE);
@@ -7032,8 +7029,7 @@ static void __devinit tg3_get_nvram_info
tw32(NVRAM_CFG1, nvcfg1);
}
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+ if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
switch (nvcfg1 & NVRAM_CFG1_VENDOR_MASK) {
case FLASH_VENDOR_ATMEL_FLASH_BUFFERED:
tp->nvram_jedecnum = JEDEC_ATMEL;
@@ -7098,8 +7094,7 @@ static void __devinit tg3_nvram_init(str
GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5701) {
tp->tg3_flags |= TG3_FLAG_NVRAM;
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+ if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
u32 nvaccess = tr32(NVRAM_ACCESS);
tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
@@ -7108,8 +7103,7 @@ static void __devinit tg3_nvram_init(str
tg3_get_nvram_info(tp);
tg3_get_nvram_size(tp);
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+ if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
u32 nvaccess = tr32(NVRAM_ACCESS);
tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
@@ -7202,8 +7196,7 @@ static int tg3_nvram_read(struct tg3 *tp
tg3_nvram_lock(tp);
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+ if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
u32 nvaccess = tr32(NVRAM_ACCESS);
tw32_f(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
@@ -7218,8 +7211,7 @@ static int tg3_nvram_read(struct tg3 *tp
tg3_nvram_unlock(tp);
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+ if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
u32 nvaccess = tr32(NVRAM_ACCESS);
tw32_f(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
@@ -7447,8 +7439,7 @@ static int tg3_nvram_write_block(struct
tg3_nvram_lock(tp);
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+ if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
u32 nvaccess = tr32(NVRAM_ACCESS);
tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
@@ -7473,8 +7464,7 @@ static int tg3_nvram_write_block(struct
grc_mode = tr32(GRC_MODE);
tw32(GRC_MODE, grc_mode & ~GRC_MODE_NVRAM_WR_ENABLE);
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+ if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
u32 nvaccess = tr32(NVRAM_ACCESS);
tw32(NVRAM_ACCESS, nvaccess & ~ACCESS_ENABLE);
@@ -7592,11 +7582,10 @@ static int __devinit tg3_phy_probe(struc
} else
eeprom_phy_id = 0;
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752) {
+ if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
led_cfg = cfg2 & (NIC_SRAM_DATA_CFG_LED_MODE_MASK |
SHASTA_EXT_LED_MODE_MASK);
- } else
+ else
led_cfg = nic_cfg & NIC_SRAM_DATA_CFG_LED_MODE_MASK;
switch (led_cfg) {
@@ -7646,8 +7635,7 @@ static int __devinit tg3_phy_probe(struc
if (nic_cfg & NIC_SRAM_DATA_CFG_ASF_ENABLE) {
tp->tg3_flags |= TG3_FLAG_ENABLE_ASF;
- if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
- GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
+ if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS)
tp->tg3_flags2 |= TG3_FLG2_ASF_NEW_HANDSHAKE;
}
if (nic_cfg & NIC_SRAM_DATA_CFG_FIBER_WOL)
On Wed, 13 Apr 2005 19:38:43 -0400
"John W. Linville" <[email protected]> wrote:
> Track-down all references to ASIC_REV_5750 and mirror them with
> references to the newly defined ASIC_REV_5752.
>
> Signed-off-by: John W. Linville <[email protected]>
You don't actually add the ASIC_REV_5752 definition to tg3.h,
but I took care of that for you when checking this patch in.
Applied, thanks.
On Wed, 13 Apr 2005 19:38:44 -0400
"John W. Linville" <[email protected]> wrote:
> Add hard-coded definition of bcm5752 PCI ID to tg3_pci_tbl.
>
> Signed-off-by: John W. Linville <[email protected]>
> ---
> Next patch will change entry to use pci_ids.h-based definition.
Applied, thanks.
On Wed, 13 Apr 2005 19:38:44 -0400
"John W. Linville" <[email protected]> wrote:
> Add proper entry for bcm5752 PCI ID to pci_ids.h, and use it in tg3.
>
> Signed-off-by: John W. Linville <[email protected]>
> ---
> I did this separately in case patches like this (i.e. new PCI IDs)
> need to come from more "official" sources.
Applied, thanks. Don't we need a drivers/pci/pci.ids update as
well?
On Wed, 13 Apr 2005 19:38:45 -0400
"John W. Linville" <[email protected]> wrote:
> Define TG3_FLG2_5750_PLUS flag and set it in tg3_get_invariants for
> ASIC_REV_5750 or ASIC_REV_5752.
>
> Signed-off-by: John W. Linville <[email protected]>
Applied, thanks.
On Wed, 13 Apr 2005 19:38:44 -0400
"John W. Linville" <[email protected]> wrote:
> Replace a number of three-way if statements checking for 5705, 5750,
> and 5752 to reference the equivalent TG3_FLG2_5705_PLUS flag instead.
>
> Signed-off-by: John W. Linville <[email protected]>
Applied.
On Wed, 13 Apr 2005 19:38:45 -0400
"John W. Linville" <[email protected]> wrote:
> Replace a number of two-way if statements checking for 5750, and/or
> 5752 to reference the newly-defined TG3_FLG2_5750_PLUS flag instead.
>
> Signed-off-by: John W. Linville <[email protected]>
Applied.
On Wed, 13 Apr 2005 19:38:45 -0400
"John W. Linville" <[email protected]> wrote:
> Rewrite checks in tg3_get_invariants to use TG3_FLG2_5705_PLUS and
> TG3_FLG2_5750_PLUS flags.
>
> Signed-off-by: John W. Linville <[email protected]>
Applied.
On Wed, 13 Apr 2005 19:38:46 -0400
"John W. Linville" <[email protected]> wrote:
> Use check of TG3_FLG2_5750_PLUS in tg3_get_invariants to set
> TG3_FLG2_5705_PLUS flag.
>
> Signed-off-by: John W. Linville <[email protected]>
Applied.
On Wed, 13 Apr 2005 19:38:46 -0400
"John W. Linville" <[email protected]> wrote:
> Replace existing ASIC_REV_5752 definition with ASIC_REV_5752_A0,
> and add definition for ASIC_REV_5752_A1. Then, add ASIC_REV_5752_A1
> to check for setting TG3_FLG2_5750_PLUS in tg3_get_invariants.
>
> Signed-off-by: John W. Linville <[email protected]>
Applied, now off to Michael's additions :-)
On Wed, 13 Apr 2005 19:38:45 -0400
"John W. Linville" <[email protected]> wrote:
> Rewrite of a couple of troublesome multi-way if statements to use
> TG3_FLG2_5705_PLUS flag.
>
> Signed-off-by: John W. Linville <[email protected]>
Applied.
Update pci.ids for BCM5752
Signed-off-by: John W. Linville <[email protected]>
---
drivers/pci/pci.ids | 1 +
1 files changed, 1 insertion(+)
--- tg3-pci/drivers/pci/pci.ids.orig 2005-05-27 14:41:25.243607911 -0400
+++ tg3-pci/drivers/pci/pci.ids 2005-05-27 14:43:45.553326412 -0400
@@ -7173,6 +7173,7 @@
080f Sentry5 DDR/SDR RAM Controller
0811 Sentry5 External Interface Core
0816 BCM3302 Sentry5 MIPS32 CPU
+ 1600 NetXtreme BCM5752 Gigabit Ethernet PCI Express
1644 NetXtreme BCM5700 Gigabit Ethernet
1014 0277 Broadcom Vigil B5700 1000Base-T
1028 00d1 Broadcom BCM5700
--
John W. Linville
[email protected]
On Fri, May 27, 2005 at 02:47:52PM -0400, John W. Linville wrote:
> Update pci.ids for BCM5752
>
> Signed-off-by: John W. Linville <[email protected]>
> ---
>
> drivers/pci/pci.ids | 1 +
> 1 files changed, 1 insertion(+)
>
> --- tg3-pci/drivers/pci/pci.ids.orig 2005-05-27 14:41:25.243607911 -0400
> +++ tg3-pci/drivers/pci/pci.ids 2005-05-27 14:43:45.553326412 -0400
> @@ -7173,6 +7173,7 @@
> 080f Sentry5 DDR/SDR RAM Controller
> 0811 Sentry5 External Interface Core
> 0816 BCM3302 Sentry5 MIPS32 CPU
> + 1600 NetXtreme BCM5752 Gigabit Ethernet PCI Express
I don't think you should mention "PCI Express" here. That can trivially
befound it looking at the configuration header.
On Fri, May 27, 2005 at 07:53:35PM +0100, Christoph Hellwig wrote:
> On Fri, May 27, 2005 at 02:47:52PM -0400, John W. Linville wrote:
> > + 1600 NetXtreme BCM5752 Gigabit Ethernet PCI Express
>
> I don't think you should mention "PCI Express" here. That can trivially
> befound it looking at the configuration header.
I'm just following what is at pciids.sourceforge.net. Plus, it is
already like that for nine other IDs:
1659 NetXtreme BCM5721 Gigabit Ethernet PCI Express
1677 NetXtreme BCM5751 Gigabit Ethernet PCI Express
167d NetXtreme BCM5751M Gigabit Ethernet PCI Express
167e NetXtreme BCM5751F Fast Ethernet PCI Express
169d NetLink BCM5789 Gigabit Ethernet PCI Express
16dd NetLink BCM5781 Gigabit Ethernet PCI Express
16f7 NetXtreme BCM5753 Gigabit Ethernet PCI Express
16fd NetXtreme BCM5753M Gigabit Ethernet PCI Express
16fe NetXtreme BCM5753F Fast Ethernet PCI Express
The Broadcom guys can speak-up, but I figure they know if "PCI Express"
is appropriate for their device... :-)
John
--
John W. Linville
[email protected]
On Fri, May 27, 2005 at 03:00:00PM -0400, John W. Linville wrote:
> On Fri, May 27, 2005 at 07:53:35PM +0100, Christoph Hellwig wrote:
> > On Fri, May 27, 2005 at 02:47:52PM -0400, John W. Linville wrote:
>
> > > + 1600 NetXtreme BCM5752 Gigabit Ethernet PCI Express
> >
> > I don't think you should mention "PCI Express" here. That can trivially
> > befound it looking at the configuration header.
>
> I'm just following what is at pciids.sourceforge.net. Plus, it is
> already like that for nine other IDs:
>
> 1659 NetXtreme BCM5721 Gigabit Ethernet PCI Express
> 1677 NetXtreme BCM5751 Gigabit Ethernet PCI Express
> 167d NetXtreme BCM5751M Gigabit Ethernet PCI Express
> 167e NetXtreme BCM5751F Fast Ethernet PCI Express
> 169d NetLink BCM5789 Gigabit Ethernet PCI Express
> 16dd NetLink BCM5781 Gigabit Ethernet PCI Express
> 16f7 NetXtreme BCM5753 Gigabit Ethernet PCI Express
> 16fd NetXtreme BCM5753M Gigabit Ethernet PCI Express
> 16fe NetXtreme BCM5753F Fast Ethernet PCI Express
>
> The Broadcom guys can speak-up, but I figure they know if "PCI Express"
> is appropriate for their device... :-)
ok, it should be an all or nothing. I still think it's more than silly..
On Fri, 2005-05-27 at 15:00 -0400, John W. Linville wrote:
> On Fri, May 27, 2005 at 07:53:35PM +0100, Christoph Hellwig wrote:
> > On Fri, May 27, 2005 at 02:47:52PM -0400, John W. Linville wrote:
>
> > > + 1600 NetXtreme BCM5752 Gigabit Ethernet PCI Express
> >
> > I don't think you should mention "PCI Express" here. That can trivially
> > befound it looking at the configuration header.
>
> I'm just following what is at pciids.sourceforge.net. Plus, it is
> already like that for nine other IDs:
>
> 1659 NetXtreme BCM5721 Gigabit Ethernet PCI Express
> 1677 NetXtreme BCM5751 Gigabit Ethernet PCI Express
> 167d NetXtreme BCM5751M Gigabit Ethernet PCI Express
> 167e NetXtreme BCM5751F Fast Ethernet PCI Express
> 169d NetLink BCM5789 Gigabit Ethernet PCI Express
> 16dd NetLink BCM5781 Gigabit Ethernet PCI Express
> 16f7 NetXtreme BCM5753 Gigabit Ethernet PCI Express
> 16fd NetXtreme BCM5753M Gigabit Ethernet PCI Express
> 16fe NetXtreme BCM5753F Fast Ethernet PCI Express
>
> The Broadcom guys can speak-up, but I figure they know if "PCI Express"
> is appropriate for their device... :-)
>
Yes, "PCI Express" is appropriate. Thanks John.
From: "John W. Linville" <[email protected]>
Date: Fri, 27 May 2005 14:47:52 -0400
> Update pci.ids for BCM5752
>
> Signed-off-by: John W. Linville <[email protected]>
I'll apply this, thanks John.
pci.ids needs several updates for tg3 in fact, and it
also now needs entries for bnx2 as well.
On Fri, 2005-05-27 at 12:30 -0700, David S. Miller wrote:
> I'll apply this, thanks John.
>
> pci.ids needs several updates for tg3 in fact, and it
> also now needs entries for bnx2 as well.
>
The bnx2 IDs are already in, probably from sourceforge. And the tg3 IDs
look reasonably complete to me.
So in the future, do we need to patch this file or just let sourceforge
take care of it?
From: "Michael Chan" <[email protected]>
Date: Fri, 27 May 2005 12:24:19 -0700
> So in the future, do we need to patch this file or just let sourceforge
> take care of it?
I think the proper procedure is to send it to sourceforge.
But there is some latency in the changes making it back
into the kernel.
Either way, if it is submitted to the kernel or sourceforge (or even
both), it ends up getting merged together in the end.
Michael Chan wrote:
> On Fri, 2005-05-27 at 12:30 -0700, David S. Miller wrote:
>
>
>>I'll apply this, thanks John.
>>
>>pci.ids needs several updates for tg3 in fact, and it
>>also now needs entries for bnx2 as well.
>>
>
>
> The bnx2 IDs are already in, probably from sourceforge. And the tg3 IDs
> look reasonably complete to me.
>
> So in the future, do we need to patch this file or just let sourceforge
> take care of it?
Honestly, pci.ids is such a non-critical file, unless DaveM disagrees I
would strongly encourage people to -only- send pci.ids updates to
sourceforge.
pci.ids is only used in one location -- deprecated /proc/pci -- and will
be removed in the next year or so, I imagine. Further, pci.ids is
periodically sync'd en masse from sourceforge into the kernel by janitors.
Users should be using 'lspci' not /proc/pci, and lspci takes it data
from sourceforge database not the kernel.
Jeff
From: Jeff Garzik <[email protected]>
Date: Fri, 27 May 2005 16:40:21 -0400
> pci.ids is only used in one location -- deprecated /proc/pci -- and will
> be removed in the next year or so, I imagine. Further, pci.ids is
> periodically sync'd en masse from sourceforge into the kernel by janitors.
Good point.
On Fri, May 27, 2005 at 01:40:32PM -0700, David S. Miller wrote:
> From: "Michael Chan" <[email protected]>
> Date: Fri, 27 May 2005 12:24:19 -0700
>
> > So in the future, do we need to patch this file or just let sourceforge
> > take care of it?
>
> I think the proper procedure is to send it to sourceforge.
> But there is some latency in the changes making it back
> into the kernel.
The latest diff vs mainline is always available at http://www.codemonkey.org.uk/projects/pci/
(Comedy aside, I dont even remember which box is running the cronjob that
generates those files any more, good that its still ticking :-)
Greg did a sync up a while ago, but didn't seem too enthusiastic about
doing it regularly, due to the fact that /proc/pci is aparently going away.
Dave