LinuxLists.cc - [PATCH 1/5] sata, highbank: fix ordering of SGPIO signals

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Subject: [PATCH 4/5] sata, highbank: set tx_atten override bits

Some board designs do not drive the SATA transmit lines within the
specification. The ECME can provide override settings, on a per board
basis, to bring the transmit lines within spec. Read those settings
from the DTB and program them in.

Signed-off-by: Mark Langsdorf <[email protected]>
---
.../devicetree/bindings/ata/sata_highbank.txt | 2 +
drivers/ata/sata_highbank.c | 57 +++++++++++++++++-----
2 files changed, 47 insertions(+), 12 deletions(-)

diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.txt b/Documentation/devicetree/bindings/ata/sata_highbank.txt
index aa1b798..d692e9e 100644
--- a/Documentation/devicetree/bindings/ata/sata_highbank.txt
+++ b/Documentation/devicetree/bindings/ata/sata_highbank.txt
@@ -20,6 +20,8 @@ Optional properties:
indicator lights using the indicated GPIOs
- calxeda,led-order : a u32 array that map port numbers to offsets within the
SGPIO bitstream.
+- calxeda,tx-atten : a u8 array that contains TX attenuation override
+ codes, one per port.

Example:
sata@ffe08000 {
diff --git a/drivers/ata/sata_highbank.c b/drivers/ata/sata_highbank.c
index 8b40025..4c8444f 100644
--- a/drivers/ata/sata_highbank.c
+++ b/drivers/ata/sata_highbank.c
@@ -46,14 +46,19 @@
#define CR_BUSY 0x0001
#define CR_START 0x0001
#define CR_WR_RDN 0x0002
+#define CPHY_TX_INPUT_STS 0x2001
#define CPHY_RX_INPUT_STS 0x2002
-#define CPHY_SATA_OVERRIDE 0x4000
-#define CPHY_OVERRIDE 0x2005
+#define CPHY_SATA_TX_OVERRIDE 0x8000
+#define CPHY_SATA_RX_OVERRIDE 0x4000
+#define CPHY_TX_OVERRIDE 0x2004
+#define CPHY_RX_OVERRIDE 0x2005
#define SPHY_LANE 0x100
#define SPHY_HALF_RATE 0x0001
#define CPHY_SATA_DPLL_MODE 0x0700
#define CPHY_SATA_DPLL_SHIFT 8
#define CPHY_SATA_DPLL_RESET (1 << 11)
+#define CPHY_SATA_TX_ATTEN 0x1c00
+#define CPHY_SATA_TX_ATTEN_SHIFT 10
#define CPHY_PHY_COUNT 6
#define CPHY_LANE_COUNT 4
#define CPHY_PORT_COUNT (CPHY_PHY_COUNT * CPHY_LANE_COUNT)
@@ -66,6 +71,7 @@ struct phy_lane_info {
void __iomem *phy_base;
u8 lane_mapping;
u8 phy_devs;
+ u8 tx_atten;
};
static struct phy_lane_info port_data[CPHY_PORT_COUNT];

@@ -259,8 +265,27 @@ static void highbank_cphy_disable_overrides(u8 sata_port)
if (unlikely(port_data[sata_port].phy_base == NULL))
return;
tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
- tmp &= ~CPHY_SATA_OVERRIDE;
- combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
+ tmp &= ~CPHY_SATA_RX_OVERRIDE;
+ combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
+}
+
+static void cphy_override_tx_attenuation(u8 sata_port, u32 val)
+{
+ u8 lane = port_data[sata_port].lane_mapping;
+ u32 tmp;
+
+ if (val & 0x8)
+ return;
+
+ tmp = combo_phy_read(sata_port, CPHY_TX_INPUT_STS + lane * SPHY_LANE);
+ tmp &= ~CPHY_SATA_TX_OVERRIDE;
+ combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);
+
+ tmp |= CPHY_SATA_TX_OVERRIDE;
+ combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);
+
+ tmp |= (val << CPHY_SATA_TX_ATTEN_SHIFT) & CPHY_SATA_TX_ATTEN;
+ combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);
}

static void cphy_override_rx_mode(u8 sata_port, u32 val)
@@ -268,21 +293,21 @@ static void cphy_override_rx_mode(u8 sata_port, u32 val)
u8 lane = port_data[sata_port].lane_mapping;
u32 tmp;
tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
- tmp &= ~CPHY_SATA_OVERRIDE;
- combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
+ tmp &= ~CPHY_SATA_RX_OVERRIDE;
+ combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);

- tmp |= CPHY_SATA_OVERRIDE;
- combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
+ tmp |= CPHY_SATA_RX_OVERRIDE;
+ combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);

tmp &= ~CPHY_SATA_DPLL_MODE;
tmp |= val << CPHY_SATA_DPLL_SHIFT;
- combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
+ combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);

tmp |= CPHY_SATA_DPLL_RESET;
- combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
+ combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);

tmp &= ~CPHY_SATA_DPLL_RESET;
- combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
+ combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);

msleep(15);
}
@@ -299,16 +324,20 @@ static void highbank_cphy_override_lane(u8 sata_port)
lane * SPHY_LANE);
} while ((tmp & SPHY_HALF_RATE) && (k++ < 1000));
cphy_override_rx_mode(sata_port, 3);
+ cphy_override_tx_attenuation(sata_port, port_data[sata_port].tx_atten);
}

static int highbank_initialize_phys(struct device *dev, void __iomem *addr)
{
struct device_node *sata_node = dev->of_node;
- int phy_count = 0, phy, port = 0;
+ int phy_count = 0, phy, port = 0, i;
void __iomem *cphy_base[CPHY_PHY_COUNT];
struct device_node *phy_nodes[CPHY_PHY_COUNT];
+ u32 tx_atten[CPHY_PORT_COUNT];
+
memset(port_data, 0, sizeof(struct phy_lane_info) * CPHY_PORT_COUNT);
memset(phy_nodes, 0, sizeof(struct device_node*) * CPHY_PHY_COUNT);
+ memset(tx_atten, 0xff, CPHY_PORT_COUNT);

do {
u32 tmp;
@@ -336,6 +365,10 @@ static int highbank_initialize_phys(struct device *dev, void __iomem *addr)
of_node_put(phy_data.np);
port += 1;
} while (port < CPHY_PORT_COUNT);
+ of_property_read_u32_array(sata_node, "calxeda,tx-atten",
+ tx_atten, port);
+ for (i = 0; i < port; i++)
+ port_data[i].tx_atten = (u8) tx_atten[i];
return 0;
}

--
1.8.1.2

2013-07-26 15:22:23

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Subject: [PATCH 2/5] sata highbank: enable 64-bit DMA mask when using LPAE

From: Rob Herring <[email protected]>

Signed-off-by: Rob Herring <[email protected]>
Signed-off-by: Mark Langsdorf <[email protected]>
---
drivers/ata/sata_highbank.c | 3 +++
1 file changed, 3 insertions(+)

diff --git a/drivers/ata/sata_highbank.c b/drivers/ata/sata_highbank.c
index e9a4f46..8b40025 100644
--- a/drivers/ata/sata_highbank.c
+++ b/drivers/ata/sata_highbank.c
@@ -479,6 +479,9 @@ static int ahci_highbank_probe(struct platform_device *pdev)
if (hpriv->cap & HOST_CAP_PMP)
pi.flags |= ATA_FLAG_PMP;

+ if (hpriv->cap & HOST_CAP_64)
+ dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
+
/* CAP.NP sometimes indicate the index of the last enabled
* port, at other times, that of the last possible port, so
* determining the maximum port number requires looking at
--
1.8.1.2

2013-07-26 15:23:07

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Subject: [PATCH 3/5] devicetree: create a separate binding description for sata_highbank

The Calxeda sata_highbank driver has been adding its descriptions to the
ahci driver. Separate them properly.

Signed-off-by: Mark Langsdorf <[email protected]>
---
.../devicetree/bindings/ata/ahci-platform.txt | 14 ++--------
.../devicetree/bindings/ata/sata_highbank.txt | 32 ++++++++++++++++++++++
2 files changed, 34 insertions(+), 12 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ata/sata_highbank.txt

diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
index 3ec0c5c..14d7b22 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
@@ -4,27 +4,17 @@ SATA nodes are defined to describe on-chip Serial ATA controllers.
Each SATA controller should have its own node.

Required properties:
-- compatible : compatible list, contains "calxeda,hb-ahci" or "snps,spear-ahci"
+- compatible : compatible list, contains "snps,spear-ahci"
- interrupts : <interrupt mapping for SATA IRQ>
- reg : <registers mapping>

Optional properties:
-- calxeda,port-phys: phandle-combophy and lane assignment, which maps each
- SATA port to a combophy and a lane within that
- combophy
-- calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off,
- which indicates that the driver supports SGPIO
- indicator lights using the indicated GPIOs
-- calxeda,led-order : a u32 array that map port numbers to offsets within the
- SGPIO bitstream.
- dma-coherent : Present if dma operations are coherent

Example:
sata@ffe08000 {
- compatible = "calxeda,hb-ahci";
+ compatible = "snps,spear-ahci";
reg = <0xffe08000 0x1000>;
interrupts = <115>;
- calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1
- &combophy0 2 &combophy0 3>;

};
diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.txt b/Documentation/devicetree/bindings/ata/sata_highbank.txt
new file mode 100644
index 0000000..aa1b798
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/sata_highbank.txt
@@ -0,0 +1,32 @@
+* Calxeda AHCI SATA Controller
+
+SATA nodes are defined to describe on-chip Serial ATA controllers.
+The Calxeda SATA controller mostly conforms to the AHCI interface
+with some special extensions to add functionality.
+Each SATA controller should have its own node.
+
+Required properties:
+- compatible : compatible list, contains "calxeda,hb-ahci"
+- interrupts : <interrupt mapping for SATA IRQ>
+- reg : <registers mapping>
+
+Optional properties:
+- dma-coherent : Present if dma operations are coherent
+- calxeda,port-phys: phandle-combophy and lane assignment, which maps each
+ SATA port to a combophy and a lane within that
+ combophy
+- calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off,
+ which indicates that the driver supports SGPIO
+ indicator lights using the indicated GPIOs
+- calxeda,led-order : a u32 array that map port numbers to offsets within the
+ SGPIO bitstream.
+
+Example:
+ sata@ffe08000 {
+ compatible = "calxeda,hb-ahci";
+ reg = <0xffe08000 0x1000>;
+ interrupts = <115>;
+ calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1
+ &combophy0 2 &combophy0 3>;
+
+ };
--
1.8.1.2

2013-07-26 15:27:23

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Subject: [PATCH 5/5] sata, highbank: send extra clock cycles in SGPIO patterns

Some SGPIO PICs don't follow the standard very well and expect a
certain number of clock cycles or port frames in each SGPIO pattern.
Add two optional parameters in the DTB that can provide the number of
extra clock cycles to be sent before and after each SGPIO pattern.
Read those parameters from the DTB and send the extra clock cycles.

Signed-off-by: Mark Langsdorf <[email protected]>
---
Documentation/devicetree/bindings/ata/sata_highbank.txt | 4 ++++
drivers/ata/sata_highbank.c | 16 +++++++++++++---
2 files changed, 17 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.txt b/Documentation/devicetree/bindings/ata/sata_highbank.txt
index d692e9e..a05eb92 100644
--- a/Documentation/devicetree/bindings/ata/sata_highbank.txt
+++ b/Documentation/devicetree/bindings/ata/sata_highbank.txt
@@ -22,6 +22,10 @@ Optional properties:
SGPIO bitstream.
- calxeda,tx-atten : a u8 array that contains TX attenuation override
codes, one per port.
+- calxeda,pre-clocks : a u32 that indicates the number of additional clock
+ cycles to transmit before sending an SGPIO pattern
+- calxeda,post-clocks: a u32 that indicates the number of additional clock
+ cycles to transmit after sending an SGPIO pattern

Example:
sata@ffe08000 {
diff --git a/drivers/ata/sata_highbank.c b/drivers/ata/sata_highbank.c
index 4c8444f..0ca27fe 100644
--- a/drivers/ata/sata_highbank.c
+++ b/drivers/ata/sata_highbank.c
@@ -82,9 +82,11 @@ static DEFINE_SPINLOCK(sgpio_lock);
#define SGPIO_PINS 3
#define SGPIO_PORTS 8

-/* can be cast as an ahci_host_priv for compatibility with most functions */
struct ecx_plat_data {
u32 n_ports;
+ /* number of extra clocks that the SGPIO PIC controller expects */
+ u32 pre_clocks;
+ u32 post_clocks;
unsigned sgpio_gpio[SGPIO_PINS];
u32 sgpio_pattern;
u32 port_to_sgpio[SGPIO_PORTS];
@@ -144,7 +146,7 @@ static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
struct ecx_plat_data *pdata = (struct ecx_plat_data *) hpriv->plat_data;
struct ahci_port_priv *pp = ap->private_data;
unsigned long flags;
- int pmp, i;
+ int pmp, i, patt_len;
struct ahci_em_priv *emp;
u32 sgpio_out;

@@ -161,6 +163,9 @@ static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
spin_lock_irqsave(&sgpio_lock, flags);
ecx_parse_sgpio(pdata, ap->port_no, state);
sgpio_out = pdata->sgpio_pattern;
+ for (i = 0; i < pdata->pre_clocks; i++)
+ ecx_led_cycle_clock(pdata);
+
gpio_set_value(pdata->sgpio_gpio[SLOAD], 1);
ecx_led_cycle_clock(pdata);
gpio_set_value(pdata->sgpio_gpio[SLOAD], 0);
@@ -168,11 +173,14 @@ static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
* bit-bang out the SGPIO pattern, by consuming a bit and then
* clocking it out.
*/
- for (i = 0; i < (SGPIO_SIGNALS * pdata->n_ports); i++) {
+ patt_len = SGPIO_SIGNALS * pdata->n_ports;
+ for (i = 0; i < patt_len; i++) {
gpio_set_value(pdata->sgpio_gpio[SDATA], sgpio_out & 1);
sgpio_out >>= 1;
ecx_led_cycle_clock(pdata);
}
+ for (i = 0; i < pdata->post_clocks; i++)
+ ecx_led_cycle_clock(pdata);

/* save off new led state for port/slot */
emp->led_state = state;
@@ -207,6 +215,8 @@ static void highbank_set_em_messages(struct device *dev,
of_property_read_u32_array(np, "calxeda,led-order",
pdata->port_to_sgpio,
pdata->n_ports);
+ of_property_read_u32(np, "calxeda,pre-clocks", &pdata->pre_clocks);
+ of_property_read_u32(np, "calxeda,post-clocks", &pdata->post_clocks);

/* store em_loc */
hpriv->em_loc = 0;
--
1.8.1.2

2013-07-26 15:45:22

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Subject: Re: [PATCH 3/5] devicetree: create a separate binding description for sata_highbank

On 07/26/2013 10:11 AM, Mark Langsdorf wrote:
> The Calxeda sata_highbank driver has been adding its descriptions to the
> ahci driver. Separate them properly.
>
> Signed-off-by: Mark Langsdorf <[email protected]>

Acked-by: Rob Herring <[email protected]>

Rob

> ---
> .../devicetree/bindings/ata/ahci-platform.txt | 14 ++--------
> .../devicetree/bindings/ata/sata_highbank.txt | 32 ++++++++++++++++++++++
> 2 files changed, 34 insertions(+), 12 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/ata/sata_highbank.txt
>
> diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
> index 3ec0c5c..14d7b22 100644
> --- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
> +++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
> @@ -4,27 +4,17 @@ SATA nodes are defined to describe on-chip Serial ATA controllers.
> Each SATA controller should have its own node.
>
> Required properties:
> -- compatible : compatible list, contains "calxeda,hb-ahci" or "snps,spear-ahci"
> +- compatible : compatible list, contains "snps,spear-ahci"
> - interrupts : <interrupt mapping for SATA IRQ>
> - reg : <registers mapping>
>
> Optional properties:
> -- calxeda,port-phys: phandle-combophy and lane assignment, which maps each
> - SATA port to a combophy and a lane within that
> - combophy
> -- calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off,
> - which indicates that the driver supports SGPIO
> - indicator lights using the indicated GPIOs
> -- calxeda,led-order : a u32 array that map port numbers to offsets within the
> - SGPIO bitstream.
> - dma-coherent : Present if dma operations are coherent
>
> Example:
> sata@ffe08000 {
> - compatible = "calxeda,hb-ahci";
> + compatible = "snps,spear-ahci";
> reg = <0xffe08000 0x1000>;
> interrupts = <115>;
> - calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1
> - &combophy0 2 &combophy0 3>;
>
> };
> diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.txt b/Documentation/devicetree/bindings/ata/sata_highbank.txt
> new file mode 100644
> index 0000000..aa1b798
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ata/sata_highbank.txt
> @@ -0,0 +1,32 @@
> +* Calxeda AHCI SATA Controller
> +
> +SATA nodes are defined to describe on-chip Serial ATA controllers.
> +The Calxeda SATA controller mostly conforms to the AHCI interface
> +with some special extensions to add functionality.
> +Each SATA controller should have its own node.
> +
> +Required properties:
> +- compatible : compatible list, contains "calxeda,hb-ahci"
> +- interrupts : <interrupt mapping for SATA IRQ>
> +- reg : <registers mapping>
> +
> +Optional properties:
> +- dma-coherent : Present if dma operations are coherent
> +- calxeda,port-phys: phandle-combophy and lane assignment, which maps each
> + SATA port to a combophy and a lane within that
> + combophy
> +- calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off,
> + which indicates that the driver supports SGPIO
> + indicator lights using the indicated GPIOs
> +- calxeda,led-order : a u32 array that map port numbers to offsets within the
> + SGPIO bitstream.
> +
> +Example:
> + sata@ffe08000 {
> + compatible = "calxeda,hb-ahci";
> + reg = <0xffe08000 0x1000>;
> + interrupts = <115>;
> + calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1
> + &combophy0 2 &combophy0 3>;
> +
> + };
>

2013-07-26 15:48:34

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Subject: Re: [PATCH 5/5] sata, highbank: send extra clock cycles in SGPIO patterns

On 07/26/2013 10:11 AM, Mark Langsdorf wrote:
> Some SGPIO PICs don't follow the standard very well and expect a
> certain number of clock cycles or port frames in each SGPIO pattern.
> Add two optional parameters in the DTB that can provide the number of
> extra clock cycles to be sent before and after each SGPIO pattern.
> Read those parameters from the DTB and send the extra clock cycles.
>
> Signed-off-by: Mark Langsdorf <[email protected]>

Acked-by: Rob Herring <[email protected]>

> ---
> Documentation/devicetree/bindings/ata/sata_highbank.txt | 4 ++++
> drivers/ata/sata_highbank.c | 16 +++++++++++++---
> 2 files changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.txt b/Documentation/devicetree/bindings/ata/sata_highbank.txt
> index d692e9e..a05eb92 100644
> --- a/Documentation/devicetree/bindings/ata/sata_highbank.txt
> +++ b/Documentation/devicetree/bindings/ata/sata_highbank.txt
> @@ -22,6 +22,10 @@ Optional properties:
> SGPIO bitstream.
> - calxeda,tx-atten : a u8 array that contains TX attenuation override
> codes, one per port.
> +- calxeda,pre-clocks : a u32 that indicates the number of additional clock
> + cycles to transmit before sending an SGPIO pattern
> +- calxeda,post-clocks: a u32 that indicates the number of additional clock
> + cycles to transmit after sending an SGPIO pattern
>
> Example:
> sata@ffe08000 {
> diff --git a/drivers/ata/sata_highbank.c b/drivers/ata/sata_highbank.c
> index 4c8444f..0ca27fe 100644
> --- a/drivers/ata/sata_highbank.c
> +++ b/drivers/ata/sata_highbank.c
> @@ -82,9 +82,11 @@ static DEFINE_SPINLOCK(sgpio_lock);
> #define SGPIO_PINS 3
> #define SGPIO_PORTS 8
>
> -/* can be cast as an ahci_host_priv for compatibility with most functions */
> struct ecx_plat_data {
> u32 n_ports;
> + /* number of extra clocks that the SGPIO PIC controller expects */
> + u32 pre_clocks;
> + u32 post_clocks;
> unsigned sgpio_gpio[SGPIO_PINS];
> u32 sgpio_pattern;
> u32 port_to_sgpio[SGPIO_PORTS];
> @@ -144,7 +146,7 @@ static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
> struct ecx_plat_data *pdata = (struct ecx_plat_data *) hpriv->plat_data;
> struct ahci_port_priv *pp = ap->private_data;
> unsigned long flags;
> - int pmp, i;
> + int pmp, i, patt_len;
> struct ahci_em_priv *emp;
> u32 sgpio_out;
>
> @@ -161,6 +163,9 @@ static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
> spin_lock_irqsave(&sgpio_lock, flags);
> ecx_parse_sgpio(pdata, ap->port_no, state);
> sgpio_out = pdata->sgpio_pattern;
> + for (i = 0; i < pdata->pre_clocks; i++)
> + ecx_led_cycle_clock(pdata);
> +
> gpio_set_value(pdata->sgpio_gpio[SLOAD], 1);
> ecx_led_cycle_clock(pdata);
> gpio_set_value(pdata->sgpio_gpio[SLOAD], 0);
> @@ -168,11 +173,14 @@ static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
> * bit-bang out the SGPIO pattern, by consuming a bit and then
> * clocking it out.
> */
> - for (i = 0; i < (SGPIO_SIGNALS * pdata->n_ports); i++) {
> + patt_len = SGPIO_SIGNALS * pdata->n_ports;
> + for (i = 0; i < patt_len; i++) {
> gpio_set_value(pdata->sgpio_gpio[SDATA], sgpio_out & 1);
> sgpio_out >>= 1;
> ecx_led_cycle_clock(pdata);
> }
> + for (i = 0; i < pdata->post_clocks; i++)
> + ecx_led_cycle_clock(pdata);
>
> /* save off new led state for port/slot */
> emp->led_state = state;
> @@ -207,6 +215,8 @@ static void highbank_set_em_messages(struct device *dev,
> of_property_read_u32_array(np, "calxeda,led-order",
> pdata->port_to_sgpio,
> pdata->n_ports);
> + of_property_read_u32(np, "calxeda,pre-clocks", &pdata->pre_clocks);
> + of_property_read_u32(np, "calxeda,post-clocks", &pdata->post_clocks);
>
> /* store em_loc */
> hpriv->em_loc = 0;
>

2013-07-26 16:22:42

by Mark Rutland

[permalink] [raw]

Subject: Re: [PATCH 4/5] sata, highbank: set tx_atten override bits

On Fri, Jul 26, 2013 at 04:11:57PM +0100, Mark Langsdorf wrote:
> Some board designs do not drive the SATA transmit lines within the
> specification. The ECME can provide override settings, on a per board
> basis, to bring the transmit lines within spec. Read those settings
> from the DTB and program them in.

How variable is the use of this property going to be? Would it instead
be possible to decide that this was necessary, and choose the
appropriate values based on a compatible property?

>
> Signed-off-by: Mark Langsdorf <[email protected]>
> ---
> .../devicetree/bindings/ata/sata_highbank.txt | 2 +
> drivers/ata/sata_highbank.c | 57 +++++++++++++++++-----
> 2 files changed, 47 insertions(+), 12 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.txt b/Documentation/devicetree/bindings/ata/sata_highbank.txt
> index aa1b798..d692e9e 100644
> --- a/Documentation/devicetree/bindings/ata/sata_highbank.txt
> +++ b/Documentation/devicetree/bindings/ata/sata_highbank.txt
> @@ -20,6 +20,8 @@ Optional properties:
> indicator lights using the indicated GPIOs
> - calxeda,led-order : a u32 array that map port numbers to offsets within the
> SGPIO bitstream.
> +- calxeda,tx-atten : a u8 array that contains TX attenuation override
> + codes, one per port.

Is this a u8 array / binary string, or is this an array of u32 cells, of
which only 8 bits are used in each cell? The code seems to suggest the
latter.

Which of the follwoing do you expect?

calxeda,tx-atten = [ 0x00 0x01 0x02 0x03 ];
calxeda,tx-atten = < 0x00 0x01 0x02 0x03 >;

Thanks,
Mark.

>
> Example:
> sata@ffe08000 {

Please amend the example.

> diff --git a/drivers/ata/sata_highbank.c b/drivers/ata/sata_highbank.c
> index 8b40025..4c8444f 100644
> --- a/drivers/ata/sata_highbank.c
> +++ b/drivers/ata/sata_highbank.c
> @@ -46,14 +46,19 @@
> #define CR_BUSY 0x0001
> #define CR_START 0x0001
> #define CR_WR_RDN 0x0002
> +#define CPHY_TX_INPUT_STS 0x2001
> #define CPHY_RX_INPUT_STS 0x2002
> -#define CPHY_SATA_OVERRIDE 0x4000
> -#define CPHY_OVERRIDE 0x2005
> +#define CPHY_SATA_TX_OVERRIDE 0x8000
> +#define CPHY_SATA_RX_OVERRIDE 0x4000
> +#define CPHY_TX_OVERRIDE 0x2004
> +#define CPHY_RX_OVERRIDE 0x2005
> #define SPHY_LANE 0x100
> #define SPHY_HALF_RATE 0x0001
> #define CPHY_SATA_DPLL_MODE 0x0700
> #define CPHY_SATA_DPLL_SHIFT 8
> #define CPHY_SATA_DPLL_RESET (1 << 11)
> +#define CPHY_SATA_TX_ATTEN 0x1c00
> +#define CPHY_SATA_TX_ATTEN_SHIFT 10
> #define CPHY_PHY_COUNT 6
> #define CPHY_LANE_COUNT 4
> #define CPHY_PORT_COUNT (CPHY_PHY_COUNT * CPHY_LANE_COUNT)
> @@ -66,6 +71,7 @@ struct phy_lane_info {
> void __iomem *phy_base;
> u8 lane_mapping;
> u8 phy_devs;
> + u8 tx_atten;
> };
> static struct phy_lane_info port_data[CPHY_PORT_COUNT];
>
> @@ -259,8 +265,27 @@ static void highbank_cphy_disable_overrides(u8 sata_port)
> if (unlikely(port_data[sata_port].phy_base == NULL))
> return;
> tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
> - tmp &= ~CPHY_SATA_OVERRIDE;
> - combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
> + tmp &= ~CPHY_SATA_RX_OVERRIDE;
> + combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
> +}
> +
> +static void cphy_override_tx_attenuation(u8 sata_port, u32 val)
> +{
> + u8 lane = port_data[sata_port].lane_mapping;
> + u32 tmp;
> +
> + if (val & 0x8)
> + return;
> +
> + tmp = combo_phy_read(sata_port, CPHY_TX_INPUT_STS + lane * SPHY_LANE);
> + tmp &= ~CPHY_SATA_TX_OVERRIDE;
> + combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);
> +
> + tmp |= CPHY_SATA_TX_OVERRIDE;
> + combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);
> +
> + tmp |= (val << CPHY_SATA_TX_ATTEN_SHIFT) & CPHY_SATA_TX_ATTEN;
> + combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);
> }
>
> static void cphy_override_rx_mode(u8 sata_port, u32 val)
> @@ -268,21 +293,21 @@ static void cphy_override_rx_mode(u8 sata_port, u32 val)
> u8 lane = port_data[sata_port].lane_mapping;
> u32 tmp;
> tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
> - tmp &= ~CPHY_SATA_OVERRIDE;
> - combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
> + tmp &= ~CPHY_SATA_RX_OVERRIDE;
> + combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
>
> - tmp |= CPHY_SATA_OVERRIDE;
> - combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
> + tmp |= CPHY_SATA_RX_OVERRIDE;
> + combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
>
> tmp &= ~CPHY_SATA_DPLL_MODE;
> tmp |= val << CPHY_SATA_DPLL_SHIFT;
> - combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
> + combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
>
> tmp |= CPHY_SATA_DPLL_RESET;
> - combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
> + combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
>
> tmp &= ~CPHY_SATA_DPLL_RESET;
> - combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
> + combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
>
> msleep(15);
> }
> @@ -299,16 +324,20 @@ static void highbank_cphy_override_lane(u8 sata_port)
> lane * SPHY_LANE);
> } while ((tmp & SPHY_HALF_RATE) && (k++ < 1000));
> cphy_override_rx_mode(sata_port, 3);
> + cphy_override_tx_attenuation(sata_port, port_data[sata_port].tx_atten);
> }
>
> static int highbank_initialize_phys(struct device *dev, void __iomem *addr)
> {
> struct device_node *sata_node = dev->of_node;
> - int phy_count = 0, phy, port = 0;
> + int phy_count = 0, phy, port = 0, i;
> void __iomem *cphy_base[CPHY_PHY_COUNT];
> struct device_node *phy_nodes[CPHY_PHY_COUNT];
> + u32 tx_atten[CPHY_PORT_COUNT];
> +
> memset(port_data, 0, sizeof(struct phy_lane_info) * CPHY_PORT_COUNT);
> memset(phy_nodes, 0, sizeof(struct device_node*) * CPHY_PHY_COUNT);
> + memset(tx_atten, 0xff, CPHY_PORT_COUNT);
>
> do {
> u32 tmp;
> @@ -336,6 +365,10 @@ static int highbank_initialize_phys(struct device *dev, void __iomem *addr)
> of_node_put(phy_data.np);
> port += 1;
> } while (port < CPHY_PORT_COUNT);
> + of_property_read_u32_array(sata_node, "calxeda,tx-atten",
> + tx_atten, port);
> + for (i = 0; i < port; i++)
> + port_data[i].tx_atten = (u8) tx_atten[i];
> return 0;
> }
>
> --
> 1.8.1.2
>
>

2013-07-26 16:26:16

by Mark Rutland

[permalink] [raw]

Subject: Re: [PATCH 5/5] sata, highbank: send extra clock cycles in SGPIO patterns

On Fri, Jul 26, 2013 at 04:11:58PM +0100, Mark Langsdorf wrote:
> Some SGPIO PICs don't follow the standard very well and expect a
> certain number of clock cycles or port frames in each SGPIO pattern.
> Add two optional parameters in the DTB that can provide the number of
> extra clock cycles to be sent before and after each SGPIO pattern.
> Read those parameters from the DTB and send the extra clock cycles.

Is this likely to be very variable, or something we can device based on
a compatible string?

>
> Signed-off-by: Mark Langsdorf <[email protected]>
> ---
> Documentation/devicetree/bindings/ata/sata_highbank.txt | 4 ++++
> drivers/ata/sata_highbank.c | 16 +++++++++++++---
> 2 files changed, 17 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.txt b/Documentation/devicetree/bindings/ata/sata_highbank.txt
> index d692e9e..a05eb92 100644
> --- a/Documentation/devicetree/bindings/ata/sata_highbank.txt
> +++ b/Documentation/devicetree/bindings/ata/sata_highbank.txt
> @@ -22,6 +22,10 @@ Optional properties:
> SGPIO bitstream.
> - calxeda,tx-atten : a u8 array that contains TX attenuation override
> codes, one per port.
> +- calxeda,pre-clocks : a u32 that indicates the number of additional clock
> + cycles to transmit before sending an SGPIO pattern
> +- calxeda,post-clocks: a u32 that indicates the number of additional clock
> + cycles to transmit after sending an SGPIO pattern
>
> Example:
> sata@ffe08000 {
> diff --git a/drivers/ata/sata_highbank.c b/drivers/ata/sata_highbank.c
> index 4c8444f..0ca27fe 100644
> --- a/drivers/ata/sata_highbank.c
> +++ b/drivers/ata/sata_highbank.c
> @@ -82,9 +82,11 @@ static DEFINE_SPINLOCK(sgpio_lock);
> #define SGPIO_PINS 3
> #define SGPIO_PORTS 8
>
> -/* can be cast as an ahci_host_priv for compatibility with most functions */
> struct ecx_plat_data {
> u32 n_ports;
> + /* number of extra clocks that the SGPIO PIC controller expects */
> + u32 pre_clocks;
> + u32 post_clocks;
> unsigned sgpio_gpio[SGPIO_PINS];
> u32 sgpio_pattern;
> u32 port_to_sgpio[SGPIO_PORTS];
> @@ -144,7 +146,7 @@ static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
> struct ecx_plat_data *pdata = (struct ecx_plat_data *) hpriv->plat_data;
> struct ahci_port_priv *pp = ap->private_data;
> unsigned long flags;
> - int pmp, i;
> + int pmp, i, patt_len;
> struct ahci_em_priv *emp;
> u32 sgpio_out;
>
> @@ -161,6 +163,9 @@ static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
> spin_lock_irqsave(&sgpio_lock, flags);
> ecx_parse_sgpio(pdata, ap->port_no, state);
> sgpio_out = pdata->sgpio_pattern;
> + for (i = 0; i < pdata->pre_clocks; i++)
> + ecx_led_cycle_clock(pdata);
> +
> gpio_set_value(pdata->sgpio_gpio[SLOAD], 1);
> ecx_led_cycle_clock(pdata);
> gpio_set_value(pdata->sgpio_gpio[SLOAD], 0);
> @@ -168,11 +173,14 @@ static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
> * bit-bang out the SGPIO pattern, by consuming a bit and then
> * clocking it out.
> */
> - for (i = 0; i < (SGPIO_SIGNALS * pdata->n_ports); i++) {
> + patt_len = SGPIO_SIGNALS * pdata->n_ports;
> + for (i = 0; i < patt_len; i++) {
> gpio_set_value(pdata->sgpio_gpio[SDATA], sgpio_out & 1);
> sgpio_out >>= 1;
> ecx_led_cycle_clock(pdata);
> }
> + for (i = 0; i < pdata->post_clocks; i++)
> + ecx_led_cycle_clock(pdata);
>
> /* save off new led state for port/slot */
> emp->led_state = state;
> @@ -207,6 +215,8 @@ static void highbank_set_em_messages(struct device *dev,
> of_property_read_u32_array(np, "calxeda,led-order",
> pdata->port_to_sgpio,
> pdata->n_ports);
> + of_property_read_u32(np, "calxeda,pre-clocks", &pdata->pre_clocks);
> + of_property_read_u32(np, "calxeda,post-clocks", &pdata->post_clocks);

Are the pdata values initialised anywhere if those dt properties aren't
present? It's not clear from the patch context.

Thanks,
Mark.

2013-07-26 18:34:23

[permalink] [raw]

Subject: Re: [PATCH 5/5] sata, highbank: send extra clock cycles in SGPIO patterns

On 07/26/2013 11:26 AM, Mark Rutland wrote:
> On Fri, Jul 26, 2013 at 04:11:58PM +0100, Mark Langsdorf wrote:
>> Some SGPIO PICs don't follow the standard very well and expect a
>> certain number of clock cycles or port frames in each SGPIO pattern.
>> Add two optional parameters in the DTB that can provide the number of
>> extra clock cycles to be sent before and after each SGPIO pattern.
>> Read those parameters from the DTB and send the extra clock cycles.
>
> Is this likely to be very variable, or something we can device based on
> a compatible string?

We have a sample size of 2 to base it on, so there is no way to know.
One slave requires some extra clocks and one doesn't.

The compatible string is based on the SOC block. These properties are
based on the board design.

Rob

>
>>
>> Signed-off-by: Mark Langsdorf <[email protected]>
>> ---
>> Documentation/devicetree/bindings/ata/sata_highbank.txt | 4 ++++
>> drivers/ata/sata_highbank.c | 16 +++++++++++++---
>> 2 files changed, 17 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.txt b/Documentation/devicetree/bindings/ata/sata_highbank.txt
>> index d692e9e..a05eb92 100644
>> --- a/Documentation/devicetree/bindings/ata/sata_highbank.txt
>> +++ b/Documentation/devicetree/bindings/ata/sata_highbank.txt
>> @@ -22,6 +22,10 @@ Optional properties:
>> SGPIO bitstream.
>> - calxeda,tx-atten : a u8 array that contains TX attenuation override
>> codes, one per port.
>> +- calxeda,pre-clocks : a u32 that indicates the number of additional clock
>> + cycles to transmit before sending an SGPIO pattern
>> +- calxeda,post-clocks: a u32 that indicates the number of additional clock
>> + cycles to transmit after sending an SGPIO pattern
>>
>> Example:
>> sata@ffe08000 {
>> diff --git a/drivers/ata/sata_highbank.c b/drivers/ata/sata_highbank.c
>> index 4c8444f..0ca27fe 100644
>> --- a/drivers/ata/sata_highbank.c
>> +++ b/drivers/ata/sata_highbank.c
>> @@ -82,9 +82,11 @@ static DEFINE_SPINLOCK(sgpio_lock);
>> #define SGPIO_PINS 3
>> #define SGPIO_PORTS 8
>>
>> -/* can be cast as an ahci_host_priv for compatibility with most functions */
>> struct ecx_plat_data {
>> u32 n_ports;
>> + /* number of extra clocks that the SGPIO PIC controller expects */
>> + u32 pre_clocks;
>> + u32 post_clocks;
>> unsigned sgpio_gpio[SGPIO_PINS];
>> u32 sgpio_pattern;
>> u32 port_to_sgpio[SGPIO_PORTS];
>> @@ -144,7 +146,7 @@ static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
>> struct ecx_plat_data *pdata = (struct ecx_plat_data *) hpriv->plat_data;
>> struct ahci_port_priv *pp = ap->private_data;
>> unsigned long flags;
>> - int pmp, i;
>> + int pmp, i, patt_len;
>> struct ahci_em_priv *emp;
>> u32 sgpio_out;
>>
>> @@ -161,6 +163,9 @@ static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
>> spin_lock_irqsave(&sgpio_lock, flags);
>> ecx_parse_sgpio(pdata, ap->port_no, state);
>> sgpio_out = pdata->sgpio_pattern;
>> + for (i = 0; i < pdata->pre_clocks; i++)
>> + ecx_led_cycle_clock(pdata);
>> +
>> gpio_set_value(pdata->sgpio_gpio[SLOAD], 1);
>> ecx_led_cycle_clock(pdata);
>> gpio_set_value(pdata->sgpio_gpio[SLOAD], 0);
>> @@ -168,11 +173,14 @@ static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
>> * bit-bang out the SGPIO pattern, by consuming a bit and then
>> * clocking it out.
>> */
>> - for (i = 0; i < (SGPIO_SIGNALS * pdata->n_ports); i++) {
>> + patt_len = SGPIO_SIGNALS * pdata->n_ports;
>> + for (i = 0; i < patt_len; i++) {
>> gpio_set_value(pdata->sgpio_gpio[SDATA], sgpio_out & 1);
>> sgpio_out >>= 1;
>> ecx_led_cycle_clock(pdata);
>> }
>> + for (i = 0; i < pdata->post_clocks; i++)
>> + ecx_led_cycle_clock(pdata);
>>
>> /* save off new led state for port/slot */
>> emp->led_state = state;
>> @@ -207,6 +215,8 @@ static void highbank_set_em_messages(struct device *dev,
>> of_property_read_u32_array(np, "calxeda,led-order",
>> pdata->port_to_sgpio,
>> pdata->n_ports);
>> + of_property_read_u32(np, "calxeda,pre-clocks", &pdata->pre_clocks);
>> + of_property_read_u32(np, "calxeda,post-clocks", &pdata->post_clocks);
>
> Are the pdata values initialised anywhere if those dt properties aren't
> present? It's not clear from the patch context.
>
> Thanks,
> Mark.
>

2013-07-26 18:38:30

[permalink] [raw]

Subject: Re: [PATCH 4/5] sata, highbank: set tx_atten override bits

On 07/26/2013 11:22 AM, Mark Rutland wrote:
> On Fri, Jul 26, 2013 at 04:11:57PM +0100, Mark Langsdorf wrote:
>> Some board designs do not drive the SATA transmit lines within the
>> specification. The ECME can provide override settings, on a per board
>> basis, to bring the transmit lines within spec. Read those settings
>> from the DTB and program them in.
>
> How variable is the use of this property going to be? Would it instead
> be possible to decide that this was necessary, and choose the
> appropriate values based on a compatible property?

It is based on compliance testing of the particular board design. Basing
on a compatible property would not work in this case.

Rob

2013-07-29 16:55:38

[permalink] [raw]

Subject: Re: [PATCH 1/5] sata, highbank: fix ordering of SGPIO signals

On Fri, Jul 26, 2013 at 10:11:54AM -0500, Mark Langsdorf wrote:
> The ACTIVITY and ERROR signals were reversed in the original commit.
> Fix that.

And what's the implication of this change? Does this change the
behavior of the driver? If so, how? If not, why not? *Please* be
more descriptive in patch descriptions and explain *why* the changes
are being made.

Thanks.

--
tejun

2013-07-30 16:42:47

by Mark Rutland

[permalink] [raw]

Subject: Re: [PATCH 4/5] sata, highbank: set tx_atten override bits

On Fri, Jul 26, 2013 at 07:38:24PM +0100, Rob Herring wrote:
> On 07/26/2013 11:22 AM, Mark Rutland wrote:
> > On Fri, Jul 26, 2013 at 04:11:57PM +0100, Mark Langsdorf wrote:
> >> Some board designs do not drive the SATA transmit lines within the
> >> specification. The ECME can provide override settings, on a per board
> >> basis, to bring the transmit lines within spec. Read those settings
> >> from the DTB and program them in.
> >
> > How variable is the use of this property going to be? Would it instead
> > be possible to decide that this was necessary, and choose the
> > appropriate values based on a compatible property?
>
> It is based on compliance testing of the particular board design. Basing
> on a compatible property would not work in this case.

Ok. Could you clarify the u8/cell usage in the binding and amend the
example please?

Cheers,
Mark.

2013-08-02 15:24:53

[permalink] [raw]

Subject: Re: [PATCH 1/5] sata, highbank: fix ordering of SGPIO signals

On 07/29/2013 11:55 AM, Tejun Heo wrote:
> On Fri, Jul 26, 2013 at 10:11:54AM -0500, Mark Langsdorf wrote:
>> The ACTIVITY and ERROR signals were reversed in the original commit.
>> Fix that.
>
> And what's the implication of this change? Does this change the
> behavior of the driver? If so, how? If not, why not? *Please* be
> more descriptive in patch descriptions and explain *why* the changes
> are being made.

I didn't think I needed more of an explanation than "this is completely
wrong per the spec" but I'll revise and resubmit.

--Mark Langsdorf
Calxeda, Inc.

2013-08-02 15:25:21

[permalink] [raw]

Subject: Re: [PATCH 4/5] sata, highbank: set tx_atten override bits

On 07/30/2013 11:42 AM, Mark Rutland wrote:
> On Fri, Jul 26, 2013 at 07:38:24PM +0100, Rob Herring wrote:
>> On 07/26/2013 11:22 AM, Mark Rutland wrote:
>>> On Fri, Jul 26, 2013 at 04:11:57PM +0100, Mark Langsdorf wrote:
>>>> Some board designs do not drive the SATA transmit lines within the
>>>> specification. The ECME can provide override settings, on a per board
>>>> basis, to bring the transmit lines within spec. Read those settings
>>>> from the DTB and program them in.
>>>
>>> How variable is the use of this property going to be? Would it instead
>>> be possible to decide that this was necessary, and choose the
>>> appropriate values based on a compatible property?
>>
>> It is based on compliance testing of the particular board design. Basing
>> on a compatible property would not work in this case.
>
> Ok. Could you clarify the u8/cell usage in the binding and amend the
> example please?

Yes, I'll do that. Thanks for the review.

--Mark Langsdorf
Calxeda, Inc.

2013-08-02 19:29:37

[permalink] [raw]

Subject: Re: [PATCH 1/5] sata, highbank: fix ordering of SGPIO signals

Hello,

On Fri, Aug 02, 2013 at 10:23:49AM -0500, Mark Langsdorf wrote:
> I didn't think I needed more of an explanation than "this is completely
> wrong per the spec" but I'll revise and resubmit.

Of course you always need to explain the implications as the result of
"being completely wrong per the spec" can range from no actual effect
at all to massive data corruption. In general, it's a good idea for a
patch descrpition to describe why the change is an improvement and how
it changes the behavior. The former provides the rationale for
inclusion and the latter helps various people including the subsystem,
-stable and distro kernel maintainers to assess the risk involved in
taking the change.

Thanks.

--
tejun

2013-08-14 18:23:38

[permalink] [raw]

Subject: [PATCH v4 2/3] sata, highbank: set tx_atten override bits

Some board designs do not drive the SATA transmit lines within the
specification. The ECME can provide override settings, on a per board
basis, to bring the transmit lines within spec. Read those settings
from the DTB and program them in.

At the time of submission, no production hardware requires this patch.

Signed-off-by: Mark Langsdorf <[email protected]>
---
Changes from v3
Edited the commit message to describe the hardware impact.
Renumbered the patch series since the first two got accepted.
Changes from v2
None.
Changes from v1
Clarified that the array is a u32 array.
Added an example in the bindings.

.../devicetree/bindings/ata/sata_highbank.txt | 4 ++
drivers/ata/sata_highbank.c | 58 +++++++++++++++++-----
2 files changed, 49 insertions(+), 13 deletions(-)

diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.txt b/Documentation/devicetree/bindings/ata/sata_highbank.txt
index e7a6f28..c84833e 100644
--- a/Documentation/devicetree/bindings/ata/sata_highbank.txt
+++ b/Documentation/devicetree/bindings/ata/sata_highbank.txt
@@ -20,6 +20,9 @@ Optional properties:
indicator lights using the indicated GPIOs
- calxeda,led-order : a u32 array that map port numbers to offsets within the
SGPIO bitstream.
+- calxeda,tx-atten : a u32 array that contains TX attenuation override
+ codes, one per port. The upper 3 bytes are always
+ 0 and thus ignored.

Example:
sata@ffe08000 {
@@ -31,4 +34,5 @@ Example:
&combophy0 2 &combophy0 3>;
calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
calxeda,led-order = <4 0 1 2 3>;
+ calxeda,tx-atten = <0xff 22 0xff 0xff 23>;
};
diff --git a/drivers/ata/sata_highbank.c b/drivers/ata/sata_highbank.c
index 8b40025..a7c8038 100644
--- a/drivers/ata/sata_highbank.c
+++ b/drivers/ata/sata_highbank.c
@@ -46,14 +46,19 @@
#define CR_BUSY 0x0001
#define CR_START 0x0001
#define CR_WR_RDN 0x0002
+#define CPHY_TX_INPUT_STS 0x2001
#define CPHY_RX_INPUT_STS 0x2002
-#define CPHY_SATA_OVERRIDE 0x4000
-#define CPHY_OVERRIDE 0x2005
+#define CPHY_SATA_TX_OVERRIDE 0x8000
+#define CPHY_SATA_RX_OVERRIDE 0x4000
+#define CPHY_TX_OVERRIDE 0x2004
+#define CPHY_RX_OVERRIDE 0x2005
#define SPHY_LANE 0x100
#define SPHY_HALF_RATE 0x0001
#define CPHY_SATA_DPLL_MODE 0x0700
#define CPHY_SATA_DPLL_SHIFT 8
#define CPHY_SATA_DPLL_RESET (1 << 11)
+#define CPHY_SATA_TX_ATTEN 0x1c00
+#define CPHY_SATA_TX_ATTEN_SHIFT 10
#define CPHY_PHY_COUNT 6
#define CPHY_LANE_COUNT 4
#define CPHY_PORT_COUNT (CPHY_PHY_COUNT * CPHY_LANE_COUNT)
@@ -66,6 +71,7 @@ struct phy_lane_info {
void __iomem *phy_base;
u8 lane_mapping;
u8 phy_devs;
+ u8 tx_atten;
};
static struct phy_lane_info port_data[CPHY_PORT_COUNT];

@@ -76,7 +82,6 @@ static DEFINE_SPINLOCK(sgpio_lock);
#define SGPIO_PINS 3
#define SGPIO_PORTS 8

-/* can be cast as an ahci_host_priv for compatibility with most functions */
struct ecx_plat_data {
u32 n_ports;
unsigned sgpio_gpio[SGPIO_PINS];
@@ -259,8 +264,27 @@ static void highbank_cphy_disable_overrides(u8 sata_port)
if (unlikely(port_data[sata_port].phy_base == NULL))
return;
tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
- tmp &= ~CPHY_SATA_OVERRIDE;
- combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
+ tmp &= ~CPHY_SATA_RX_OVERRIDE;
+ combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
+}
+
+static void cphy_override_tx_attenuation(u8 sata_port, u32 val)
+{
+ u8 lane = port_data[sata_port].lane_mapping;
+ u32 tmp;
+
+ if (val & 0x8)
+ return;
+
+ tmp = combo_phy_read(sata_port, CPHY_TX_INPUT_STS + lane * SPHY_LANE);
+ tmp &= ~CPHY_SATA_TX_OVERRIDE;
+ combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);
+
+ tmp |= CPHY_SATA_TX_OVERRIDE;
+ combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);
+
+ tmp |= (val << CPHY_SATA_TX_ATTEN_SHIFT) & CPHY_SATA_TX_ATTEN;
+ combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);
}

static void cphy_override_rx_mode(u8 sata_port, u32 val)
@@ -268,21 +292,21 @@ static void cphy_override_rx_mode(u8 sata_port, u32 val)
u8 lane = port_data[sata_port].lane_mapping;
u32 tmp;
tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
- tmp &= ~CPHY_SATA_OVERRIDE;
- combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
+ tmp &= ~CPHY_SATA_RX_OVERRIDE;
+ combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);

- tmp |= CPHY_SATA_OVERRIDE;
- combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
+ tmp |= CPHY_SATA_RX_OVERRIDE;
+ combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);

tmp &= ~CPHY_SATA_DPLL_MODE;
tmp |= val << CPHY_SATA_DPLL_SHIFT;
- combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
+ combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);

tmp |= CPHY_SATA_DPLL_RESET;
- combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
+ combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);

tmp &= ~CPHY_SATA_DPLL_RESET;
- combo_phy_write(sata_port, CPHY_OVERRIDE + lane * SPHY_LANE, tmp);
+ combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);

msleep(15);
}
@@ -299,16 +323,20 @@ static void highbank_cphy_override_lane(u8 sata_port)
lane * SPHY_LANE);
} while ((tmp & SPHY_HALF_RATE) && (k++ < 1000));
cphy_override_rx_mode(sata_port, 3);
+ cphy_override_tx_attenuation(sata_port, port_data[sata_port].tx_atten);
}

static int highbank_initialize_phys(struct device *dev, void __iomem *addr)
{
struct device_node *sata_node = dev->of_node;
- int phy_count = 0, phy, port = 0;
+ int phy_count = 0, phy, port = 0, i;
void __iomem *cphy_base[CPHY_PHY_COUNT];
struct device_node *phy_nodes[CPHY_PHY_COUNT];
+ u32 tx_atten[CPHY_PORT_COUNT];
+
memset(port_data, 0, sizeof(struct phy_lane_info) * CPHY_PORT_COUNT);
memset(phy_nodes, 0, sizeof(struct device_node*) * CPHY_PHY_COUNT);
+ memset(tx_atten, 0xff, CPHY_PORT_COUNT);

do {
u32 tmp;
@@ -336,6 +364,10 @@ static int highbank_initialize_phys(struct device *dev, void __iomem *addr)
of_node_put(phy_data.np);
port += 1;
} while (port < CPHY_PORT_COUNT);
+ of_property_read_u32_array(sata_node, "calxeda,tx-atten",
+ tx_atten, port);
+ for (i = 0; i < port; i++)
+ port_data[i].tx_atten = (u8) tx_atten[i];
return 0;
}

--
1.8.1.2

2013-08-14 18:23:37

[permalink] [raw]

Subject: [PATCH v4 1/3] devicetree: create a separate binding description for sata_highbank

2013-08-14 18:24:39

[permalink] [raw]

Subject: [PATCH v4 3/3] sata, highbank: send extra clock cycles in SGPIO patterns

Some SGPIO PICs don't follow the standard very well and expect a certain
number of clock cycles or port frames in each SGPIO pattern. Add two
optional parameters in the DTB that can provide the number of extra
clock cycles to be sent before and after SGPIO pattern. Read those
parameters from the DTB and send the extra clock cycles.

Signed-off-by: Mark Langsdorf <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
Changes from v3
Renumbered the patch series since the first two got accepted.
Changes from v2
None.
Changes from v1
Added an example to the bindings.
Forced the pre-clocks and post-clocks values to 0 if there is an
error while reading them or the values aren't in the DTB.

Documentation/devicetree/bindings/ata/sata_highbank.txt | 6 ++++++
drivers/ata/sata_highbank.c | 13 +++++++++++++
2 files changed, 19 insertions(+)

diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.txt b/Documentation/devicetree/bindings/ata/sata_highbank.txt
index c84833e..aa83407 100644
--- a/Documentation/devicetree/bindings/ata/sata_highbank.txt
+++ b/Documentation/devicetree/bindings/ata/sata_highbank.txt
@@ -23,6 +23,10 @@ Optional properties:
- calxeda,tx-atten : a u32 array that contains TX attenuation override
codes, one per port. The upper 3 bytes are always
0 and thus ignored.
+- calxeda,pre-clocks : a u32 that indicates the number of additional clock
+ cycles to transmit before sending an SGPIO pattern
+- calxeda,post-clocks: a u32 that indicates the number of additional clock
+ cycles to transmit after sending an SGPIO pattern

Example:
sata@ffe08000 {
@@ -35,4 +39,6 @@ Example:
calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
calxeda,led-order = <4 0 1 2 3>;
calxeda,tx-atten = <0xff 22 0xff 0xff 23>;
+ calxeda,pre-clocks = <10>;
+ calxeda,post-clocks = <0>;
};
diff --git a/drivers/ata/sata_highbank.c b/drivers/ata/sata_highbank.c
index a7c8038..7f5e5d9 100644
--- a/drivers/ata/sata_highbank.c
+++ b/drivers/ata/sata_highbank.c
@@ -84,6 +84,9 @@ static DEFINE_SPINLOCK(sgpio_lock);

struct ecx_plat_data {
u32 n_ports;
+ /* number of extra clocks that the SGPIO PIC controller expects */
+ u32 pre_clocks;
+ u32 post_clocks;
unsigned sgpio_gpio[SGPIO_PINS];
u32 sgpio_pattern;
u32 port_to_sgpio[SGPIO_PORTS];
@@ -160,6 +163,9 @@ static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
spin_lock_irqsave(&sgpio_lock, flags);
ecx_parse_sgpio(pdata, ap->port_no, state);
sgpio_out = pdata->sgpio_pattern;
+ for (i = 0; i < pdata->pre_clocks; i++)
+ ecx_led_cycle_clock(pdata);
+
gpio_set_value(pdata->sgpio_gpio[SLOAD], 1);
ecx_led_cycle_clock(pdata);
gpio_set_value(pdata->sgpio_gpio[SLOAD], 0);
@@ -172,6 +178,8 @@ static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
sgpio_out >>= 1;
ecx_led_cycle_clock(pdata);
}
+ for (i = 0; i < pdata->post_clocks; i++)
+ ecx_led_cycle_clock(pdata);

/* save off new led state for port/slot */
emp->led_state = state;
@@ -206,6 +214,11 @@ static void highbank_set_em_messages(struct device *dev,
of_property_read_u32_array(np, "calxeda,led-order",
pdata->port_to_sgpio,
pdata->n_ports);
+ if (of_property_read_u32(np, "calxeda,pre-clocks", &pdata->pre_clocks))
+ pdata->pre_clocks = 0;
+ if (of_property_read_u32(np, "calxeda,post-clocks",
+ &pdata->post_clocks))
+ pdata->post_clocks = 0;

/* store em_loc */
hpriv->em_loc = 0;
--
1.8.1.2

2013-08-14 20:27:35

[permalink] [raw]

Subject: Re: [PATCH v4 1/3] devicetree: create a separate binding description for sata_highbank

Hello,

On Wed, Aug 14, 2013 at 01:23:30PM -0500, Mark Langsdorf wrote:
> Documentation/devicetree/bindings/ata/sata_highbank.txt | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)

Any ideas on how these should be routed? The above doesn't apply to
libata or master as the file doesn't exist there yet.

Thanks.

--
tejun

2013-08-14 20:36:27

[permalink] [raw]

Subject: Re: [PATCH v4 1/3] devicetree: create a separate binding description for sata_highbank

On 08/14/2013 03:27 PM, Tejun Heo wrote:
> Hello,
>
> On Wed, Aug 14, 2013 at 01:23:30PM -0500, Mark Langsdorf wrote:
>> Documentation/devicetree/bindings/ata/sata_highbank.txt | 6 ++++--
>> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> Any ideas on how these should be routed? The above doesn't apply to
> libata or master as the file doesn't exist there yet.

I accidentally introduced a new commit while cleaning up the patch. The
correct patch text should have been as follows. Do you want me to resubmit?

--Mark Langsdorf
Calxeda, Inc.

---
.../devicetree/bindings/ata/ahci-platform.txt | 18 +++---------
.../devicetree/bindings/ata/sata_highbank.txt | 34
++++++++++++++++++++++
2 files changed, 38 insertions(+), 14 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ata/sata_highbank.txt

diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt
b/Documentation/devicetree/bindings/ata/ahci-platform.txt
index 3ec0c5c..89de156 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
@@ -4,27 +4,17 @@ SATA nodes are defined to describe on-chip Serial ATA
controllers.
Each SATA controller should have its own node.

Required properties:
-- compatible : compatible list, contains "calxeda,hb-ahci" or
"snps,spear-ahci"
+- compatible : compatible list, contains "snps,spear-ahci"
- interrupts : <interrupt mapping for SATA IRQ>
- reg : <registers mapping>

Optional properties:
-- calxeda,port-phys: phandle-combophy and lane assignment, which maps each
- SATA port to a combophy and a lane within that
- combophy
-- calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off,
- which indicates that the driver supports SGPIO
- indicator lights using the indicated GPIOs
-- calxeda,led-order : a u32 array that map port numbers to offsets
within the
- SGPIO bitstream.
- dma-coherent : Present if dma operations are coherent

Example:
sata@ffe08000 {
- compatible = "calxeda,hb-ahci";
- reg = <0xffe08000 0x1000>;
- interrupts = <115>;
- calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1
- &combophy0 2 &combophy0 3>;
+ compatible = "snps,spear-ahci";
+ reg = <0xffe08000 0x1000>;
+ interrupts = <115>;

};
diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.txt
b/Documentation/devicetree/bindings/ata/sata_highbank.txt
new file mode 100644
index 0000000..e7a6f28
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/sata_highbank.txt
@@ -0,0 +1,34 @@
+* Calxeda AHCI SATA Controller
+
+SATA nodes are defined to describe on-chip Serial ATA controllers.
+The Calxeda SATA controller mostly conforms to the AHCI interface
+with some special extensions to add functionality.
+Each SATA controller should have its own node.
+
+Required properties:
+- compatible : compatible list, contains "calxeda,hb-ahci"
+- interrupts : <interrupt mapping for SATA IRQ>
+- reg : <registers mapping>
+
+Optional properties:
+- dma-coherent : Present if dma operations are coherent
+- calxeda,port-phys : phandle-combophy and lane assignment, which maps each
+ SATA port to a combophy and a lane within that
+ combophy
+- calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off,
+ which indicates that the driver supports SGPIO
+ indicator lights using the indicated GPIOs
+- calxeda,led-order : a u32 array that map port numbers to offsets
within the
+ SGPIO bitstream.
+
+Example:
+ sata@ffe08000 {
+ compatible = "calxeda,hb-ahci";
+ reg = <0xffe08000 0x1000>;
+ interrupts = <115>;
+ dma-coherent;
+ calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1
+ &combophy0 2 &combophy0 3>;
+ calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
+ calxeda,led-order = <4 0 1 2 3>;
+ };
--
1.8.1.2

2013-08-14 20:37:16

[permalink] [raw]

Subject: Re: [PATCH v4 1/3] devicetree: create a separate binding description for sata_highbank

On Wed, Aug 14, 2013 at 03:36:11PM -0500, Mark Langsdorf wrote:
> On 08/14/2013 03:27 PM, Tejun Heo wrote:
> > Hello,
> >
> > On Wed, Aug 14, 2013 at 01:23:30PM -0500, Mark Langsdorf wrote:
> >> Documentation/devicetree/bindings/ata/sata_highbank.txt | 6 ++++--
> >> 1 file changed, 4 insertions(+), 2 deletions(-)
> >
> > Any ideas on how these should be routed? The above doesn't apply to
> > libata or master as the file doesn't exist there yet.
>
> I accidentally introduced a new commit while cleaning up the patch. The
> correct patch text should have been as follows. Do you want me to resubmit?

Can you please just re-send the corrupt patch?

Thanks.

--
tejun

2013-08-14 20:40:15

[permalink] [raw]

Subject: [PATCH v4 1/3] devicetree: create a separate binding description for sata_highbank

The Calxeda sata_highbank driver has been adding its descriptions to the
ahci driver. Separate them properly. This patch only affects
documentation and has no functional component.

Signed-off-by: Mark Langsdorf <[email protected]>
Acked-by: Rob Herring <[email protected]>
---
Changes from v3
Added all optional properties to the example.
Expanded the description.
Renumbered the patch series since the first two got accepted.
Changes from v2
Fixed some indenting.
Changes from v1
None.

---
.../devicetree/bindings/ata/ahci-platform.txt | 18 +++---------
.../devicetree/bindings/ata/sata_highbank.txt | 34 ++++++++++++++++++++++
2 files changed, 38 insertions(+), 14 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ata/sata_highbank.txt

diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt b/Documentation/devicetree/bindings/ata/ahci-platform.txt
index 3ec0c5c..89de156 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
@@ -4,27 +4,17 @@ SATA nodes are defined to describe on-chip Serial ATA controllers.
Each SATA controller should have its own node.

Required properties:
-- compatible : compatible list, contains "calxeda,hb-ahci" or "snps,spear-ahci"
+- compatible : compatible list, contains "snps,spear-ahci"
- interrupts : <interrupt mapping for SATA IRQ>
- reg : <registers mapping>

Optional properties:
-- calxeda,port-phys: phandle-combophy and lane assignment, which maps each
- SATA port to a combophy and a lane within that
- combophy
-- calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off,
- which indicates that the driver supports SGPIO
- indicator lights using the indicated GPIOs
-- calxeda,led-order : a u32 array that map port numbers to offsets within the
- SGPIO bitstream.
- dma-coherent : Present if dma operations are coherent

Example:
sata@ffe08000 {
- compatible = "calxeda,hb-ahci";
- reg = <0xffe08000 0x1000>;
- interrupts = <115>;
- calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1
- &combophy0 2 &combophy0 3>;
+ compatible = "snps,spear-ahci";
+ reg = <0xffe08000 0x1000>;
+ interrupts = <115>;

};
diff --git a/Documentation/devicetree/bindings/ata/sata_highbank.txt b/Documentation/devicetree/bindings/ata/sata_highbank.txt
new file mode 100644
index 0000000..e7a6f28
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/sata_highbank.txt
@@ -0,0 +1,34 @@
+* Calxeda AHCI SATA Controller
+
+SATA nodes are defined to describe on-chip Serial ATA controllers.
+The Calxeda SATA controller mostly conforms to the AHCI interface
+with some special extensions to add functionality.
+Each SATA controller should have its own node.
+
+Required properties:
+- compatible : compatible list, contains "calxeda,hb-ahci"
+- interrupts : <interrupt mapping for SATA IRQ>
+- reg : <registers mapping>
+
+Optional properties:
+- dma-coherent : Present if dma operations are coherent
+- calxeda,port-phys : phandle-combophy and lane assignment, which maps each
+ SATA port to a combophy and a lane within that
+ combophy
+- calxeda,sgpio-gpio: phandle-gpio bank, bit offset, and default on or off,
+ which indicates that the driver supports SGPIO
+ indicator lights using the indicated GPIOs
+- calxeda,led-order : a u32 array that map port numbers to offsets within the
+ SGPIO bitstream.
+
+Example:
+ sata@ffe08000 {
+ compatible = "calxeda,hb-ahci";
+ reg = <0xffe08000 0x1000>;
+ interrupts = <115>;
+ dma-coherent;
+ calxeda,port-phys = <&combophy5 0 &combophy0 0 &combophy0 1
+ &combophy0 2 &combophy0 3>;
+ calxeda,sgpio-gpio =<&gpioh 5 1 &gpioh 6 1 &gpioh 7 1>;
+ calxeda,led-order = <4 0 1 2 3>;
+ };
--
1.8.1.2

2013-08-14 20:44:09