Hi,
This series adds the required device tree nodes to enable the usb2/1.1 phy
and usb2/1.1 controllers on the stih416-b2120 board.
It additionally re-works and adds support for the new stih410 SoC which is
very similar to the stih407 SoC, by abstracting out the common parts
into common dt files. It also then adds the dt nodes to enable usb2/1.1
for the stih410 platform as well.
As well as adding dt nodes it also enables the relevant drivers in the
mult7_v7_defconfig.
Finally we update the default bootargs for stih407-b2120 and stih410-b2120
to boot with the clk_ignore_unused kernel parameter so as not to hang
the SoC when the (as yet) unreferenced interconnect clocks get disabled
by CCF (this is a tempoary solution).
This series has been tested on stih416-b2020 and stih410-b2120 SoC/boards.
regards,
Peter.
Peter Griffin (13):
ARM: STi: DT: STiH416: Add pinctl setup for usb controllers.
ARM: STi: DT: STiH416: Add DT node for the stih415/6 usb2 phy
ARM: STi: DT: STiH416: Add DT nodes for the ehci and ohci usb
controllers.
ARM: multi_v7_defconfig: Enable st ohci and ehci HCD drivers.
ARM: multi_v7_defconfig: Enable stih415/6 usb2 phy driver.
ARM: multi_v7_defconfig: Enable stih407 usb picophy
ARM: STi: DT: STiH407: Add usb2 picophy dt nodes
ARM: STi: DT: STiH410: Add defines for STiH410 DT clocks
ARM: STi: DT: STiH410: Add pinctl config for usb controllers.
ARM: STi: DT: STih410: Add dt nodes for the ehci / ohci usb
controllers.
ARM: STi: DT: STih407: Abstract common dt nodes into shared files.
ARM: STi: DT: STiH410: Add STiH410 SoC clock support.
ARM: STi: DT: STih407: Add clk_ignore_unused to kernel bootargs
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/stih407-b2120.dts | 67 +-----
arch/arm/boot/dts/stih407-family.dtsi | 384 +++++++++++++++++++++++++++++++
arch/arm/boot/dts/stih407-pinctrl.dtsi | 18 ++
arch/arm/boot/dts/stih407.dtsi | 279 ----------------------
arch/arm/boot/dts/stih410-b2120.dts | 42 ++++
arch/arm/boot/dts/stih410-clock.dtsi | 338 +++++++++++++++++++++++++++
arch/arm/boot/dts/stih416-b2020.dts | 4 +
arch/arm/boot/dts/stih416-b2020e.dts | 4 +
arch/arm/boot/dts/stih416-pinctrl.dtsi | 34 +++
arch/arm/boot/dts/stih416.dtsi | 153 ++++++++++++
arch/arm/boot/dts/stih41x-b2020.dtsi | 12 +
arch/arm/boot/dts/stihxxx-b2120.dtsi | 73 ++++++
arch/arm/configs/multi_v7_defconfig | 4 +
include/dt-bindings/clock/stih410-clks.h | 24 ++
15 files changed, 1094 insertions(+), 343 deletions(-)
create mode 100644 arch/arm/boot/dts/stih407-family.dtsi
delete mode 100644 arch/arm/boot/dts/stih407.dtsi
create mode 100644 arch/arm/boot/dts/stih410-b2120.dts
create mode 100644 arch/arm/boot/dts/stih410-clock.dtsi
create mode 100644 arch/arm/boot/dts/stihxxx-b2120.dtsi
create mode 100644 include/dt-bindings/clock/stih410-clks.h
--
1.9.1
This patch adds the required pin config for all usb controllers
on the stih416.
Signed-off-by: Peter Griffin <[email protected]>
---
arch/arm/boot/dts/stih416-pinctrl.dtsi | 34 ++++++++++++++++++++++++++++++++++
1 file changed, 34 insertions(+)
diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
index c2025bc..9cccf2d 100644
--- a/arch/arm/boot/dts/stih416-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
@@ -147,6 +147,15 @@
};
};
+ usb {
+ pinctrl_usb3: usb3 {
+ st,pins {
+ oc-detect = <&pio40 0 ALT1 IN>;
+ pwr-enable = <&pio40 1 ALT1 OUT>;
+ };
+ };
+ };
+
sbc_i2c1 {
pinctrl_sbc_i2c1_default: sbc_i2c1-default {
st,pins {
@@ -318,6 +327,16 @@
};
};
+ usb {
+ pinctrl_usb0: usb0 {
+ st,pins {
+ oc-detect = <&pio9 4 ALT1 IN>;
+ pwr-enable = <&pio9 5 ALT1 OUT>;
+ };
+ };
+ };
+
+
i2c1 {
pinctrl_i2c1_default: i2c1-default {
st,pins {
@@ -506,6 +525,21 @@
};
};
};
+
+ usb {
+ pinctrl_usb1: usb1 {
+ st,pins {
+ oc-detect = <&pio18 0 ALT1 IN>;
+ pwr-enable = <&pio18 1 ALT1 OUT>;
+ };
+ };
+ pinctrl_usb2: usb2 {
+ st,pins {
+ oc-detect = <&pio18 2 ALT1 IN>;
+ pwr-enable = <&pio18 3 ALT1 OUT>;
+ };
+ };
+ };
};
pin-controller-fvdp-fe {
--
1.9.1
This driver is used by the ehci / ohci usb controllers on stih415/6 SoCs.
Signed-off-by: Peter Griffin <[email protected]>
Acked-by: Kishon Vijay Abraham I <[email protected]>
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index c7a9517..e13ab7e 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -426,6 +426,7 @@ CONFIG_PWM_VT8500=y
CONFIG_OMAP_USB2=y
CONFIG_TI_PIPE3=y
CONFIG_PHY_MIPHY365X=y
+CONFIG_PHY_STIH41X_USB=y
CONFIG_PHY_SUN4I_USB=y
CONFIG_EXT4_FS=y
CONFIG_VFAT_FS=y
--
1.9.1
Although most clock outputs are the same as stih407 SoC, stih410
also has some additional new clock outputs.
Signed-off-by: Peter Griffin <[email protected]>
---
include/dt-bindings/clock/stih410-clks.h | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
create mode 100644 include/dt-bindings/clock/stih410-clks.h
diff --git a/include/dt-bindings/clock/stih410-clks.h b/include/dt-bindings/clock/stih410-clks.h
new file mode 100644
index 0000000..2c5d6ff
--- /dev/null
+++ b/include/dt-bindings/clock/stih410-clks.h
@@ -0,0 +1,24 @@
+/*
+ * This header provides constants clk index STMicroelectronics
+ * STiH410 SoC.
+ */
+#ifndef _DT_BINDINGS_CLK_STIH410
+#define _DT_BINDINGS_CLK_STIH410
+#include "stih407-clks.h"
+
+/* STiH410 introduces new clock outputs compared to STiH407 */
+
+/* CLOCKGEN C0 */
+#define CLK_TX_ICN_HADES 32
+#define CLK_RX_ICN_HADES 33
+#define CLK_ICN_REG_16 34
+#define CLK_PP_HADES 35
+#define CLK_CLUST_HADES 36
+#define CLK_HWPE_HADES 37
+#define CLK_FC_HADES 38
+
+/* CLOCKGEN D0 */
+#define CLK_PCMR10_MASTER 4
+#define CLK_USB2_PHY 5
+
+#endif
--
1.9.1
The stih410 has some additional usb controllers. This patch adds the
dt nodes which will enabled them to function correctly.
Signed-off-by: Peter Griffin <[email protected]>
---
arch/arm/boot/dts/stih407.dtsi | 60 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi
index 967ec39..5e01db2 100644
--- a/arch/arm/boot/dts/stih407.dtsi
+++ b/arch/arm/boot/dts/stih407.dtsi
@@ -321,5 +321,65 @@
reset-names = "global",
"port";
};
+
+ ohci0: usb@9a03c00 {
+ compatible = "st,st-ohci-300x";
+ status = "disabled";
+ reg = <0x9a03c00 0x100>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
+ clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
+ resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
+ <&softreset STIH407_USB2_PORT0_SOFTRESET>;
+ reset-names = "power", "softreset";
+
+ phys = <&usb2_picophy0>;
+ phy-names = "usb";
+ };
+
+ ehci0: usb@9a03e00 {
+ compatible = "st,st-ehci-300x";
+ status = "disabled";
+ reg = <0x9a03e00 0x100>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
+ resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
+ <&softreset STIH407_USB2_PORT0_SOFTRESET>;
+ reset-names = "power", "softreset";
+
+ phys = <&usb2_picophy0>;
+ phy-names = "usb";
+ };
+
+ ohci1: usb@9a83c00 {
+ compatible = "st,st-ohci-300x";
+ status = "disabled";
+ reg = <0x9a83c00 0x100>;
+ interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
+ clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
+ resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
+ <&softreset STIH407_USB2_PORT1_SOFTRESET>;
+ reset-names = "power", "softreset";
+
+ phys = <&usb2_picophy1>;
+ phy-names = "usb";
+ };
+
+ ehci1: usb@9a83e00 {
+ compatible = "st,st-ehci-300x";
+ status = "disabled";
+ reg = <0x9a83e00 0x100>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
+ resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
+ <&softreset STIH407_USB2_PORT1_SOFTRESET>;
+ reset-names = "power", "softreset";
+
+ phys = <&usb2_picophy1>;
+ phy-names = "usb";
+ };
};
};
--
1.9.1
The STiH410 is an advanced multi-HD AVC processor with 3D graphics acceleration
and 1.5-GHz ARM Cortex-A9 SMP CPU part of the stih407 family.
It has wide connectivity including USB 3.0, PCI-e, SATA and gigabit ethernet.
Signed-off-by: Peter Griffin <[email protected]>
---
arch/arm/boot/dts/Makefile | 1 +
arch/arm/boot/dts/stih410-b2120.dts | 42 +++++
arch/arm/boot/dts/stih410-clock.dtsi | 338 +++++++++++++++++++++++++++++++++++
3 files changed, 381 insertions(+)
create mode 100644 arch/arm/boot/dts/stih410-b2120.dts
create mode 100644 arch/arm/boot/dts/stih410-clock.dtsi
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 38c89ca..04cf4a4 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -409,6 +409,7 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
spear320-hmi.dtb
dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \
+ stih410-b2120.dtb \
stih415-b2000.dtb \
stih415-b2020.dtb \
stih416-b2000.dtb \
diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts
new file mode 100644
index 0000000..06ee73b
--- /dev/null
+++ b/arch/arm/boot/dts/stih410-b2120.dts
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics (R&D) Limited.
+ * Author: Peter Griffin <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/dts-v1/;
+#include "stih407-clock.dtsi"
+#include "stih407-family.dtsi"
+#include "stihxxx-b2120.dtsi"
+/ {
+ model = "STiH410 B2120";
+ compatible = "st,stih410-b2120", "st,stih410";
+
+ aliases {
+ ohci0 = &ohci0;
+ ehci0 = &ehci0;
+ ohci1 = &ohci1;
+ ehci1 = &ehci1;
+ };
+
+ soc {
+
+ ohci0: usb@9a03c00 {
+ status = "okay";
+ };
+
+ ehci0: usb@9a03e00 {
+ status = "okay";
+ };
+
+ ohci1: usb@9a83c00 {
+ status = "okay";
+ };
+
+ ehci1: usb@9a83e00 {
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi b/arch/arm/boot/dts/stih410-clock.dtsi
new file mode 100644
index 0000000..6b5803a
--- /dev/null
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -0,0 +1,338 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics R&D Limited
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <dt-bindings/clock/stih410-clks.h>
+/ {
+ clocks {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ compatible = "st,stih410-clk", "simple-bus";
+
+ /*
+ * Fixed 30MHz oscillator inputs to SoC
+ */
+ clk_sysin: clk-sysin {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <30000000>;
+ clock-output-names = "CLK_SYSIN";
+ };
+
+ /*
+ * ARM Peripheral clock for timers
+ */
+ arm_periph_clk: clk-m-a9-periphs {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&clk_m_a9>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ /*
+ * A9 PLL.
+ */
+ clockgen-a9@92b0000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x92b0000 0xffff>;
+
+ clockgen_a9_pll: clockgen-a9-pll {
+ #clock-cells = <1>;
+ compatible = "st,stih407-plls-c32-a9", "st,clkgen-plls-c32";
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clockgen-a9-pll-odf";
+ };
+ };
+
+ /*
+ * ARM CPU related clocks.
+ */
+ clk_m_a9: clk-m-a9@92b0000 {
+ #clock-cells = <0>;
+ compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux";
+ reg = <0x92b0000 0x10000>;
+
+ clocks = <&clockgen_a9_pll 0>,
+ <&clockgen_a9_pll 0>,
+ <&clk_s_c0_flexgen 13>,
+ <&clk_m_a9_ext2f_div2>;
+ };
+
+ /*
+ * ARM Peripheral clock for timers
+ */
+ clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+
+ clocks = <&clk_s_c0_flexgen 13>;
+
+ clock-output-names = "clk-m-a9-ext2f-div2";
+
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ /*
+ * Bootloader initialized system infrastructure clock for
+ * serial devices.
+ */
+ clk_ext2f_a9: clockgen-c0@13 {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <200000000>;
+ clock-output-names = "clk-s-icn-reg-0";
+ };
+
+ clockgen-a@090ff000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x90ff000 0x1000>;
+
+ clk_s_a0_pll: clk-s-a0-pll {
+ #clock-cells = <1>;
+ compatible = "st,stih407-plls-c32-a0", "st,clkgen-plls-c32";
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-a0-pll-ofd-0";
+ };
+
+ clk_s_a0_flexgen: clk-s-a0-flexgen {
+ compatible = "st,flexgen";
+
+ #clock-cells = <1>;
+
+ clocks = <&clk_s_a0_pll 0>,
+ <&clk_sysin>;
+
+ clock-output-names = "clk-ic-lmi0",
+ "clk-ic-lmi1";
+ };
+ };
+
+ clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 {
+ #clock-cells = <1>;
+ compatible = "st,stih407-quadfs660-C", "st,quadfs";
+ reg = <0x9103000 0x1000>;
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-c0-fs0-ch0",
+ "clk-s-c0-fs0-ch1",
+ "clk-s-c0-fs0-ch2",
+ "clk-s-c0-fs0-ch3";
+ };
+
+ clk_s_c0: clockgen-c@09103000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x9103000 0x1000>;
+
+ clk_s_c0_pll0: clk-s-c0-pll0 {
+ #clock-cells = <1>;
+ compatible = "st,stih407-plls-c32-c0_0", "st,clkgen-plls-c32";
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-c0-pll0-odf-0";
+ };
+
+ clk_s_c0_pll1: clk-s-c0-pll1 {
+ #clock-cells = <1>;
+ compatible = "st,stih407-plls-c32-c0_1", "st,clkgen-plls-c32";
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-c0-pll1-odf-0";
+ };
+
+ clk_s_c0_flexgen: clk-s-c0-flexgen {
+ #clock-cells = <1>;
+ compatible = "st,flexgen";
+
+ clocks = <&clk_s_c0_pll0 0>,
+ <&clk_s_c0_pll1 0>,
+ <&clk_s_c0_quadfs 0>,
+ <&clk_s_c0_quadfs 1>,
+ <&clk_s_c0_quadfs 2>,
+ <&clk_s_c0_quadfs 3>,
+ <&clk_sysin>;
+
+ clock-output-names = "clk-icn-gpu",
+ "clk-fdma",
+ "clk-nand",
+ "clk-hva",
+ "clk-proc-stfe",
+ "clk-proc-tp",
+ "clk-rx-icn-dmu",
+ "clk-rx-icn-hva",
+ "clk-icn-cpu",
+ "clk-tx-icn-dmu",
+ "clk-mmc-0",
+ "clk-mmc-1",
+ "clk-jpegdec",
+ "clk-ext2fa9",
+ "clk-ic-bdisp-0",
+ "clk-ic-bdisp-1",
+ "clk-pp-dmu",
+ "clk-vid-dmu",
+ "clk-dss-lpc",
+ "clk-st231-aud-0",
+ "clk-st231-gp-1",
+ "clk-st231-dmu",
+ "clk-icn-lmi",
+ "clk-tx-icn-disp-1",
+ "clk-icn-sbc",
+ "clk-stfe-frc2",
+ "clk-eth-phy",
+ "clk-eth-ref-phyclk",
+ "clk-flash-promip",
+ "clk-main-disp",
+ "clk-aux-disp",
+ "clk-compo-dvp",
+ "clk-tx-icn-hades",
+ "clk-rx-icn-hades",
+ "clk-icn-reg-16",
+ "clk-pp-hades",
+ "clk-clust-hades",
+ "clk-hwpe-hades",
+ "clk-fc-hades";
+ };
+ };
+
+ clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
+ #clock-cells = <1>;
+ compatible = "st,stih407-quadfs660-D", "st,quadfs";
+ reg = <0x9104000 0x1000>;
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-d0-fs0-ch0",
+ "clk-s-d0-fs0-ch1",
+ "clk-s-d0-fs0-ch2",
+ "clk-s-d0-fs0-ch3";
+ };
+
+ clockgen-d0@09104000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x9104000 0x1000>;
+
+ clk_s_d0_flexgen: clk-s-d0-flexgen {
+ #clock-cells = <1>;
+ compatible = "st,flexgen";
+
+ clocks = <&clk_s_d0_quadfs 0>,
+ <&clk_s_d0_quadfs 1>,
+ <&clk_s_d0_quadfs 2>,
+ <&clk_s_d0_quadfs 3>,
+ <&clk_sysin>;
+
+ clock-output-names = "clk-pcm-0",
+ "clk-pcm-1",
+ "clk-pcm-2",
+ "clk-spdiff",
+ "clk-pcmr10-master",
+ "clk-usb2-phy";
+ };
+ };
+
+ clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
+ #clock-cells = <1>;
+ compatible = "st,stih407-quadfs660-D", "st,quadfs";
+ reg = <0x9106000 0x1000>;
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-d2-fs0-ch0",
+ "clk-s-d2-fs0-ch1",
+ "clk-s-d2-fs0-ch2",
+ "clk-s-d2-fs0-ch3";
+ };
+
+ clk_tmdsout_hdmi: clk-tmdsout-hdmi {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+
+ clockgen-d2@x9106000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x9106000 0x1000>;
+
+ clk_s_d2_flexgen: clk-s-d2-flexgen {
+ #clock-cells = <1>;
+ compatible = "st,flexgen";
+
+ clocks = <&clk_s_d2_quadfs 0>,
+ <&clk_s_d2_quadfs 1>,
+ <&clk_s_d2_quadfs 2>,
+ <&clk_s_d2_quadfs 3>,
+ <&clk_sysin>,
+ <&clk_sysin>,
+ <&clk_tmdsout_hdmi>;
+
+ clock-output-names = "clk-pix-main-disp",
+ "clk-pix-pip",
+ "clk-pix-gdp1",
+ "clk-pix-gdp2",
+ "clk-pix-gdp3",
+ "clk-pix-gdp4",
+ "clk-pix-aux-disp",
+ "clk-denc",
+ "clk-pix-hddac",
+ "clk-hddac",
+ "clk-sddac",
+ "clk-pix-dvo",
+ "clk-dvo",
+ "clk-pix-hdmi",
+ "clk-tmds-hdmi",
+ "clk-ref-hdmiphy";
+ };
+ };
+
+ clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
+ #clock-cells = <1>;
+ compatible = "st,stih407-quadfs660-D", "st,quadfs";
+ reg = <0x9107000 0x1000>;
+
+ clocks = <&clk_sysin>;
+
+ clock-output-names = "clk-s-d3-fs0-ch0",
+ "clk-s-d3-fs0-ch1",
+ "clk-s-d3-fs0-ch2",
+ "clk-s-d3-fs0-ch3";
+ };
+
+ clockgen-d3@9107000 {
+ compatible = "st,clkgen-c32";
+ reg = <0x9107000 0x1000>;
+
+ clk_s_d3_flexgen: clk-s-d3-flexgen {
+ #clock-cells = <1>;
+ compatible = "st,flexgen";
+
+ clocks = <&clk_s_d3_quadfs 0>,
+ <&clk_s_d3_quadfs 1>,
+ <&clk_s_d3_quadfs 2>,
+ <&clk_s_d3_quadfs 3>,
+ <&clk_sysin>;
+
+ clock-output-names = "clk-stfe-frc1",
+ "clk-tsout-0",
+ "clk-tsout-1",
+ "clk-mchi",
+ "clk-vsens-compo",
+ "clk-frc1-remote",
+ "clk-lpc-0",
+ "clk-lpc-1";
+ };
+ };
+ };
+};
--
1.9.1
At the moment we don't take a reference on some core interconnect
clocks which means when CCF turns off unused clocks the SoC will
hang. As a temp soltuion we will boot with clk_ignore_unused
parameter for all b2120 boards.
Signed-off-by: Peter Griffin <[email protected]>
---
arch/arm/boot/dts/stihxxx-b2120.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi
index 862bb2f..7280b6d 100644
--- a/arch/arm/boot/dts/stihxxx-b2120.dtsi
+++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
@@ -8,7 +8,7 @@
*/
/ {
chosen {
- bootargs = "console=ttyAS0,115200";
+ bootargs = "console=ttyAS0,115200 clk_ignore_unused";
linux,stdout-path = &sbc_serial0;
};
--
1.9.1
The stih410 soc which will be added in the following commit is very similar to
the stih407, to enable maximum re-use of the dt files this commit abstracts the
common parts into a shared dt file stihxxx-b2120 for the board, and also a shared
file stih407-family.dtsi for the SoC.
Signed-off-by: Peter Griffin <[email protected]>
---
arch/arm/boot/dts/stih407-b2120.dts | 67 +-----
arch/arm/boot/dts/stih407-family.dtsi | 384 +++++++++++++++++++++++++++++++++
arch/arm/boot/dts/stih407.dtsi | 385 ----------------------------------
arch/arm/boot/dts/stihxxx-b2120.dtsi | 73 +++++++
4 files changed, 460 insertions(+), 449 deletions(-)
create mode 100644 arch/arm/boot/dts/stih407-family.dtsi
delete mode 100644 arch/arm/boot/dts/stih407.dtsi
create mode 100644 arch/arm/boot/dts/stihxxx-b2120.dtsi
diff --git a/arch/arm/boot/dts/stih407-b2120.dts b/arch/arm/boot/dts/stih407-b2120.dts
index fe69f92..e0057bf 100644
--- a/arch/arm/boot/dts/stih407-b2120.dts
+++ b/arch/arm/boot/dts/stih407-b2120.dts
@@ -7,72 +7,11 @@
* published by the Free Software Foundation.
*/
/dts-v1/;
-#include "stih407.dtsi"
+#include "stih407-clock.dtsi"
+#include "stih407-family.dtsi"
+#include "stihxxx-b2120.dtsi"
/ {
model = "STiH407 B2120";
compatible = "st,stih407-b2120", "st,stih407";
- chosen {
- bootargs = "console=ttyAS0,115200";
- linux,stdout-path = &sbc_serial0;
- };
-
- memory {
- device_type = "memory";
- reg = <0x40000000 0x80000000>;
- };
-
- aliases {
- ttyAS0 = &sbc_serial0;
- };
-
- soc {
- sbc_serial0: serial@9530000 {
- status = "okay";
- };
-
- leds {
- compatible = "gpio-leds";
- red {
- #gpio-cells = <2>;
- label = "Front Panel LED";
- gpios = <&pio4 1 0>;
- linux,default-trigger = "heartbeat";
- };
- green {
- #gpio-cells = <2>;
- gpios = <&pio1 3 0>;
- default-state = "off";
- };
- };
-
- i2c@9842000 {
- status = "okay";
- };
-
- i2c@9843000 {
- status = "okay";
- };
-
- i2c@9844000 {
- status = "okay";
- };
-
- i2c@9845000 {
- status = "okay";
- };
-
- i2c@9540000 {
- status = "okay";
- };
-
- /* SSC11 to HDMI */
- i2c@9541000 {
- status = "okay";
- /* HDMI V1.3a supports Standard mode only */
- clock-frequency = <100000>;
- st,i2c-min-scl-pulse-width-us = <0>;
- st,i2c-min-sda-pulse-width-us = <5>;
- };
- };
};
diff --git a/arch/arm/boot/dts/stih407-family.dtsi b/arch/arm/boot/dts/stih407-family.dtsi
new file mode 100644
index 0000000..c15e65b
--- /dev/null
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -0,0 +1,384 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics Limited.
+ * Author: Giuseppe Cavallaro <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * publishhed by the Free Software Foundation.
+ */
+#include "stih407-pinctrl.dtsi"
+#include <dt-bindings/reset-controller/stih407-resets.h>
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <0>;
+ };
+ cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a9";
+ reg = <1>;
+ };
+ };
+
+ intc: interrupt-controller@08761000 {
+ compatible = "arm,cortex-a9-gic";
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ reg = <0x08761000 0x1000>, <0x08760100 0x100>;
+ };
+
+ scu@08760000 {
+ compatible = "arm,cortex-a9-scu";
+ reg = <0x08760000 0x1000>;
+ };
+
+ timer@08760200 {
+ interrupt-parent = <&intc>;
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x08760200 0x100>;
+ interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&arm_periph_clk>;
+ };
+
+ l2: cache-controller {
+ compatible = "arm,pl310-cache";
+ reg = <0x08762000 0x1000>;
+ arm,data-latency = <3 3 3>;
+ arm,tag-latency = <2 2 2>;
+ cache-unified;
+ cache-level = <2>;
+ };
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&intc>;
+ ranges;
+ compatible = "simple-bus";
+
+ powerdown: powerdown-controller {
+ compatible = "st,stih407-powerdown";
+ #reset-cells = <1>;
+ };
+
+ softreset: softreset-controller {
+ compatible = "st,stih407-softreset";
+ #reset-cells = <1>;
+ };
+
+ picophyreset: picophyreset-controller {
+ compatible = "st,stih407-picophyreset";
+ #reset-cells = <1>;
+ };
+
+ syscfg_sbc: sbc-syscfg@9620000 {
+ compatible = "st,stih407-sbc-syscfg", "syscon";
+ reg = <0x9620000 0x1000>;
+ };
+
+ syscfg_front: front-syscfg@9280000 {
+ compatible = "st,stih407-front-syscfg", "syscon";
+ reg = <0x9280000 0x1000>;
+ };
+
+ syscfg_rear: rear-syscfg@9290000 {
+ compatible = "st,stih407-rear-syscfg", "syscon";
+ reg = <0x9290000 0x1000>;
+ };
+
+ syscfg_flash: flash-syscfg@92a0000 {
+ compatible = "st,stih407-flash-syscfg", "syscon";
+ reg = <0x92a0000 0x1000>;
+ };
+
+ syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
+ compatible = "st,stih407-sbc-reg-syscfg", "syscon";
+ reg = <0x9600000 0x1000>;
+ };
+
+ syscfg_core: core-syscfg@92b0000 {
+ compatible = "st,stih407-core-syscfg", "syscon";
+ reg = <0x92b0000 0x1000>;
+ };
+
+ syscfg_lpm: lpm-syscfg@94b5100 {
+ compatible = "st,stih407-lpm-syscfg", "syscon";
+ reg = <0x94b5100 0x1000>;
+ };
+
+ serial@9830000 {
+ compatible = "st,asc";
+ reg = <0x9830000 0x2c>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_serial0>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+
+ status = "disabled";
+ };
+
+ serial@9831000 {
+ compatible = "st,asc";
+ reg = <0x9831000 0x2c>;
+ interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_serial1>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+
+ status = "disabled";
+ };
+
+ serial@9832000 {
+ compatible = "st,asc";
+ reg = <0x9832000 0x2c>;
+ interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_serial2>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+
+ status = "disabled";
+ };
+
+ /* SBC_ASC0 - UART10 */
+ sbc_serial0: serial@9530000 {
+ compatible = "st,asc";
+ reg = <0x9530000 0x2c>;
+ interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sbc_serial0>;
+ clocks = <&clk_sysin>;
+
+ status = "disabled";
+ };
+
+ serial@9531000 {
+ compatible = "st,asc";
+ reg = <0x9531000 0x2c>;
+ interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_sbc_serial1>;
+ clocks = <&clk_sysin>;
+
+ status = "disabled";
+ };
+
+ i2c@9840000 {
+ compatible = "st,comms-ssc4-i2c";
+ interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
+ reg = <0x9840000 0x110>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0_default>;
+
+ status = "disabled";
+ };
+
+ i2c@9841000 {
+ compatible = "st,comms-ssc4-i2c";
+ reg = <0x9841000 0x110>;
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1_default>;
+
+ status = "disabled";
+ };
+
+ i2c@9842000 {
+ compatible = "st,comms-ssc4-i2c";
+ reg = <0x9842000 0x110>;
+ interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c2_default>;
+
+ status = "disabled";
+ };
+
+ i2c@9843000 {
+ compatible = "st,comms-ssc4-i2c";
+ reg = <0x9843000 0x110>;
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c3_default>;
+
+ status = "disabled";
+ };
+
+ i2c@9844000 {
+ compatible = "st,comms-ssc4-i2c";
+ reg = <0x9844000 0x110>;
+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c4_default>;
+
+ status = "disabled";
+ };
+
+ i2c@9845000 {
+ compatible = "st,comms-ssc4-i2c";
+ reg = <0x9845000 0x110>;
+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c5_default>;
+
+ status = "disabled";
+ };
+
+
+ /* SSCs on SBC */
+ i2c@9540000 {
+ compatible = "st,comms-ssc4-i2c";
+ reg = <0x9540000 0x110>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_sysin>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c10_default>;
+
+ status = "disabled";
+ };
+
+ i2c@9541000 {
+ compatible = "st,comms-ssc4-i2c";
+ reg = <0x9541000 0x110>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk_sysin>;
+ clock-names = "ssc";
+ clock-frequency = <400000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c11_default>;
+
+ status = "disabled";
+ };
+
+ /* Generic picoPHY */
+ usb2_picophy0: usbpicophy@0 {
+ compatible = "st,stih407-usb2-phy";
+ reg = <0xf8 0x04>, /* syscfg 5062 */
+ <0xf4 0x04>; /* syscfg 5061 */
+ reg-names = "param",
+ "ctrl";
+ #phy-cells = <0>;
+
+ st,syscfg = <&syscfg_core>;
+ resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
+ <&picophyreset STIH407_PICOPHY0_RESET>;
+ reset-names = "global",
+ "port";
+ };
+
+ usb2_picophy1: usbpicophy@1 {
+ compatible = "st,stih407-usb2-phy";
+ #phy-cells = <0>;
+ reg = <0xfc 0x04>, /* syscfg 5063 */
+ <0xf4 0x04>; /* syscfg 5061 */
+ reg-names = "param",
+ "ctrl";
+
+ st,syscfg = <&syscfg_core>;
+ resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
+ <&picophyreset STIH407_PICOPHY1_RESET>;
+ reset-names = "global",
+ "port";
+ };
+
+ usb2_picophy2: usbpicophy@2 {
+ compatible = "st,stih407-usb2-phy";
+ #phy-cells = <0>;
+ reg = <0x100 0x04>, /* syscfg 5064 */
+ <0xf4 0x04>; /* syscfg 5061 */
+ reg-names = "param",
+ "ctrl";
+
+ st,syscfg = <&syscfg_core>;
+ resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
+ <&picophyreset STIH407_PICOPHY2_RESET>;
+ reset-names = "global",
+ "port";
+ };
+
+ ohci0: usb@9a03c00 {
+ compatible = "st,st-ohci-300x";
+ status = "disabled";
+ reg = <0x9a03c00 0x100>;
+ interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
+ clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
+ resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
+ <&softreset STIH407_USB2_PORT0_SOFTRESET>;
+ reset-names = "power", "softreset";
+
+ phys = <&usb2_picophy0>;
+ phy-names = "usb";
+ };
+
+ ehci0: usb@9a03e00 {
+ compatible = "st,st-ehci-300x";
+ status = "disabled";
+ reg = <0x9a03e00 0x100>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
+ resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
+ <&softreset STIH407_USB2_PORT0_SOFTRESET>;
+ reset-names = "power", "softreset";
+
+ phys = <&usb2_picophy0>;
+ phy-names = "usb";
+ };
+
+ ohci1: usb@9a83c00 {
+ compatible = "st,st-ohci-300x";
+ status = "disabled";
+ reg = <0x9a83c00 0x100>;
+ interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
+ clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
+ resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
+ <&softreset STIH407_USB2_PORT1_SOFTRESET>;
+ reset-names = "power", "softreset";
+
+ phys = <&usb2_picophy1>;
+ phy-names = "usb";
+ };
+
+ ehci1: usb@9a83e00 {
+ compatible = "st,st-ehci-300x";
+ status = "disabled";
+ reg = <0x9a83e00 0x100>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+ clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
+ resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
+ <&softreset STIH407_USB2_PORT1_SOFTRESET>;
+ reset-names = "power", "softreset";
+
+ phys = <&usb2_picophy1>;
+ phy-names = "usb";
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi
deleted file mode 100644
index 5e01db2..0000000
--- a/arch/arm/boot/dts/stih407.dtsi
+++ /dev/null
@@ -1,385 +0,0 @@
-/*
- * Copyright (C) 2014 STMicroelectronics Limited.
- * Author: Giuseppe Cavallaro <[email protected]>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * publishhed by the Free Software Foundation.
- */
-#include "stih407-clock.dtsi"
-#include "stih407-pinctrl.dtsi"
-#include <dt-bindings/reset-controller/stih407-resets.h>
-/ {
- #address-cells = <1>;
- #size-cells = <1>;
-
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <0>;
- };
- cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a9";
- reg = <1>;
- };
- };
-
- intc: interrupt-controller@08761000 {
- compatible = "arm,cortex-a9-gic";
- #interrupt-cells = <3>;
- interrupt-controller;
- reg = <0x08761000 0x1000>, <0x08760100 0x100>;
- };
-
- scu@08760000 {
- compatible = "arm,cortex-a9-scu";
- reg = <0x08760000 0x1000>;
- };
-
- timer@08760200 {
- interrupt-parent = <&intc>;
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x08760200 0x100>;
- interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&arm_periph_clk>;
- };
-
- l2: cache-controller {
- compatible = "arm,pl310-cache";
- reg = <0x08762000 0x1000>;
- arm,data-latency = <3 3 3>;
- arm,tag-latency = <2 2 2>;
- cache-unified;
- cache-level = <2>;
- };
-
- soc {
- #address-cells = <1>;
- #size-cells = <1>;
- interrupt-parent = <&intc>;
- ranges;
- compatible = "simple-bus";
-
- powerdown: powerdown-controller {
- compatible = "st,stih407-powerdown";
- #reset-cells = <1>;
- };
-
- softreset: softreset-controller {
- compatible = "st,stih407-softreset";
- #reset-cells = <1>;
- };
-
- picophyreset: picophyreset-controller {
- compatible = "st,stih407-picophyreset";
- #reset-cells = <1>;
- };
-
- syscfg_sbc: sbc-syscfg@9620000 {
- compatible = "st,stih407-sbc-syscfg", "syscon";
- reg = <0x9620000 0x1000>;
- };
-
- syscfg_front: front-syscfg@9280000 {
- compatible = "st,stih407-front-syscfg", "syscon";
- reg = <0x9280000 0x1000>;
- };
-
- syscfg_rear: rear-syscfg@9290000 {
- compatible = "st,stih407-rear-syscfg", "syscon";
- reg = <0x9290000 0x1000>;
- };
-
- syscfg_flash: flash-syscfg@92a0000 {
- compatible = "st,stih407-flash-syscfg", "syscon";
- reg = <0x92a0000 0x1000>;
- };
-
- syscfg_sbc_reg: fvdp-lite-syscfg@9600000 {
- compatible = "st,stih407-sbc-reg-syscfg", "syscon";
- reg = <0x9600000 0x1000>;
- };
-
- syscfg_core: core-syscfg@92b0000 {
- compatible = "st,stih407-core-syscfg", "syscon";
- reg = <0x92b0000 0x1000>;
- };
-
- syscfg_lpm: lpm-syscfg@94b5100 {
- compatible = "st,stih407-lpm-syscfg", "syscon";
- reg = <0x94b5100 0x1000>;
- };
-
- serial@9830000 {
- compatible = "st,asc";
- reg = <0x9830000 0x2c>;
- interrupts = <GIC_SPI 122 IRQ_TYPE_NONE>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_serial0>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
-
- status = "disabled";
- };
-
- serial@9831000 {
- compatible = "st,asc";
- reg = <0x9831000 0x2c>;
- interrupts = <GIC_SPI 123 IRQ_TYPE_NONE>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_serial1>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
-
- status = "disabled";
- };
-
- serial@9832000 {
- compatible = "st,asc";
- reg = <0x9832000 0x2c>;
- interrupts = <GIC_SPI 124 IRQ_TYPE_NONE>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_serial2>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
-
- status = "disabled";
- };
-
- /* SBC_ASC0 - UART10 */
- sbc_serial0: serial@9530000 {
- compatible = "st,asc";
- reg = <0x9530000 0x2c>;
- interrupts = <GIC_SPI 138 IRQ_TYPE_NONE>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sbc_serial0>;
- clocks = <&clk_sysin>;
-
- status = "disabled";
- };
-
- serial@9531000 {
- compatible = "st,asc";
- reg = <0x9531000 0x2c>;
- interrupts = <GIC_SPI 139 IRQ_TYPE_NONE>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_sbc_serial1>;
- clocks = <&clk_sysin>;
-
- status = "disabled";
- };
-
- i2c@9840000 {
- compatible = "st,comms-ssc4-i2c";
- interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
- reg = <0x9840000 0x110>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0_default>;
-
- status = "disabled";
- };
-
- i2c@9841000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9841000 0x110>;
- interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1_default>;
-
- status = "disabled";
- };
-
- i2c@9842000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9842000 0x110>;
- interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c2_default>;
-
- status = "disabled";
- };
-
- i2c@9843000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9843000 0x110>;
- interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c3_default>;
-
- status = "disabled";
- };
-
- i2c@9844000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9844000 0x110>;
- interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c4_default>;
-
- status = "disabled";
- };
-
- i2c@9845000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9845000 0x110>;
- interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c5_default>;
-
- status = "disabled";
- };
-
-
- /* SSCs on SBC */
- i2c@9540000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9540000 0x110>;
- interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_sysin>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c10_default>;
-
- status = "disabled";
- };
-
- i2c@9541000 {
- compatible = "st,comms-ssc4-i2c";
- reg = <0x9541000 0x110>;
- interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk_sysin>;
- clock-names = "ssc";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c11_default>;
-
- status = "disabled";
- };
-
- /* Generic picoPHY */
- usb2_picophy0: usbpicophy@0 {
- compatible = "st,stih407-usb2-phy";
- reg = <0xf8 0x04>, /* syscfg 5062 */
- <0xf4 0x04>; /* syscfg 5061 */
- reg-names = "param",
- "ctrl";
- #phy-cells = <0>;
-
- st,syscfg = <&syscfg_core>;
- resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
- <&picophyreset STIH407_PICOPHY0_RESET>;
- reset-names = "global",
- "port";
- };
-
- usb2_picophy1: usbpicophy@1 {
- compatible = "st,stih407-usb2-phy";
- #phy-cells = <0>;
- reg = <0xfc 0x04>, /* syscfg 5063 */
- <0xf4 0x04>; /* syscfg 5061 */
- reg-names = "param",
- "ctrl";
-
- st,syscfg = <&syscfg_core>;
- resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
- <&picophyreset STIH407_PICOPHY1_RESET>;
- reset-names = "global",
- "port";
- };
-
- usb2_picophy2: usbpicophy@2 {
- compatible = "st,stih407-usb2-phy";
- #phy-cells = <0>;
- reg = <0x100 0x04>, /* syscfg 5064 */
- <0xf4 0x04>; /* syscfg 5061 */
- reg-names = "param",
- "ctrl";
-
- st,syscfg = <&syscfg_core>;
- resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
- <&picophyreset STIH407_PICOPHY2_RESET>;
- reset-names = "global",
- "port";
- };
-
- ohci0: usb@9a03c00 {
- compatible = "st,st-ohci-300x";
- status = "disabled";
- reg = <0x9a03c00 0x100>;
- interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
- clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
- resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
- <&softreset STIH407_USB2_PORT0_SOFTRESET>;
- reset-names = "power", "softreset";
-
- phys = <&usb2_picophy0>;
- phy-names = "usb";
- };
-
- ehci0: usb@9a03e00 {
- compatible = "st,st-ehci-300x";
- status = "disabled";
- reg = <0x9a03e00 0x100>;
- interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb0>;
- clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
- resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
- <&softreset STIH407_USB2_PORT0_SOFTRESET>;
- reset-names = "power", "softreset";
-
- phys = <&usb2_picophy0>;
- phy-names = "usb";
- };
-
- ohci1: usb@9a83c00 {
- compatible = "st,st-ohci-300x";
- status = "disabled";
- reg = <0x9a83c00 0x100>;
- interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
- clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
- resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
- <&softreset STIH407_USB2_PORT1_SOFTRESET>;
- reset-names = "power", "softreset";
-
- phys = <&usb2_picophy1>;
- phy-names = "usb";
- };
-
- ehci1: usb@9a83e00 {
- compatible = "st,st-ehci-300x";
- status = "disabled";
- reg = <0x9a83e00 0x100>;
- interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_usb1>;
- clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
- resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
- <&softreset STIH407_USB2_PORT1_SOFTRESET>;
- reset-names = "power", "softreset";
-
- phys = <&usb2_picophy1>;
- phy-names = "usb";
- };
- };
-};
diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi
new file mode 100644
index 0000000..862bb2f
--- /dev/null
+++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
@@ -0,0 +1,73 @@
+/*
+ * Copyright (C) 2014 STMicroelectronics (R&D) Limited.
+ * Author: Giuseppe Cavallaro <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+/ {
+ chosen {
+ bootargs = "console=ttyAS0,115200";
+ linux,stdout-path = &sbc_serial0;
+ };
+
+ memory {
+ device_type = "memory";
+ reg = <0x40000000 0x80000000>;
+ };
+
+ aliases {
+ ttyAS0 = &sbc_serial0;
+ };
+
+ soc {
+ sbc_serial0: serial@9530000 {
+ status = "okay";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ red {
+ #gpio-cells = <2>;
+ label = "Front Panel LED";
+ gpios = <&pio4 1 0>;
+ linux,default-trigger = "heartbeat";
+ };
+ green {
+ #gpio-cells = <2>;
+ gpios = <&pio1 3 0>;
+ default-state = "off";
+ };
+ };
+
+ i2c@9842000 {
+ status = "okay";
+ };
+
+ i2c@9843000 {
+ status = "okay";
+ };
+
+ i2c@9844000 {
+ status = "okay";
+ };
+
+ i2c@9845000 {
+ status = "okay";
+ };
+
+ i2c@9540000 {
+ status = "okay";
+ };
+
+ /* SSC11 to HDMI */
+ i2c@9541000 {
+ status = "okay";
+ /* HDMI V1.3a supports Standard mode only */
+ clock-frequency = <100000>;
+ st,i2c-min-scl-pulse-width-us = <0>;
+ st,i2c-min-sda-pulse-width-us = <5>;
+ };
+ };
+};
--
1.9.1
This patch adds the required pin configiguration for the extra usb
controllers found on the stih410 device.
Signed-off-by: Peter Griffin <[email protected]>
---
arch/arm/boot/dts/stih407-pinctrl.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
index 402844c..fdaad5d 100644
--- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
@@ -539,6 +539,24 @@
};
};
+ usb0 {
+ pinctrl_usb0: usb2-0 {
+ st,pins {
+ usb-oc-detect = <&pio35 0 ALT1 IN>;
+ usb-pwr-enable = <&pio35 1 ALT1 OUT>;
+ };
+ };
+ };
+
+ usb1 {
+ pinctrl_usb1: usb2-1 {
+ st,pins {
+ usb-oc-detect = <&pio35 2 ALT1 IN>;
+ usb-pwr-enable = <&pio35 3 ALT1 OUT>;
+ };
+ };
+ };
+
usb3 {
pinctrl_usb3: usb3-2 {
st,pins {
--
1.9.1
This patch adds the dt nodes for the usb2 picophy found on the stih407
family of devices. It is used on stih410 and later devices with the ehci/ohci usb
controller, and is also used as the usb2 phy with the dwc3 usb3 controller.
Signed-off-by: Peter Griffin <[email protected]>
---
arch/arm/boot/dts/stih407.dtsi | 46 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi
index 50637f5..967ec39 100644
--- a/arch/arm/boot/dts/stih407.dtsi
+++ b/arch/arm/boot/dts/stih407.dtsi
@@ -275,5 +275,51 @@
status = "disabled";
};
+
+ /* Generic picoPHY */
+ usb2_picophy0: usbpicophy@0 {
+ compatible = "st,stih407-usb2-phy";
+ reg = <0xf8 0x04>, /* syscfg 5062 */
+ <0xf4 0x04>; /* syscfg 5061 */
+ reg-names = "param",
+ "ctrl";
+ #phy-cells = <0>;
+
+ st,syscfg = <&syscfg_core>;
+ resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
+ <&picophyreset STIH407_PICOPHY0_RESET>;
+ reset-names = "global",
+ "port";
+ };
+
+ usb2_picophy1: usbpicophy@1 {
+ compatible = "st,stih407-usb2-phy";
+ #phy-cells = <0>;
+ reg = <0xfc 0x04>, /* syscfg 5063 */
+ <0xf4 0x04>; /* syscfg 5061 */
+ reg-names = "param",
+ "ctrl";
+
+ st,syscfg = <&syscfg_core>;
+ resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
+ <&picophyreset STIH407_PICOPHY1_RESET>;
+ reset-names = "global",
+ "port";
+ };
+
+ usb2_picophy2: usbpicophy@2 {
+ compatible = "st,stih407-usb2-phy";
+ #phy-cells = <0>;
+ reg = <0x100 0x04>, /* syscfg 5064 */
+ <0xf4 0x04>; /* syscfg 5061 */
+ reg-names = "param",
+ "ctrl";
+
+ st,syscfg = <&syscfg_core>;
+ resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
+ <&picophyreset STIH407_PICOPHY2_RESET>;
+ reset-names = "global",
+ "port";
+ };
};
};
--
1.9.1
This usb picophy is found on stih415/6 SoC.
Signed-off-by: Peter Griffin <[email protected]>
---
arch/arm/boot/dts/stih416.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 1137bdf..0f3019a 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -316,5 +316,14 @@
status = "disabled";
};
+
+ usb2_phy: usb2phy@0 {
+ compatible = "st,stih416-usb-phy";
+ #phy-cells = <0>;
+ st,syscfg = <&syscfg_rear>;
+ clocks = <&clk_sysin>;
+ clock-names = "osc_phy";
+
+ };
};
};
--
1.9.1
This patch adds the DT nodes for the 4 usb ehci and ohci usb controllers
on the stih416 SoC.
Signed-off-by: Peter Griffin <[email protected]>
---
arch/arm/boot/dts/stih416-b2020.dts | 4 +
arch/arm/boot/dts/stih416-b2020e.dts | 4 +
arch/arm/boot/dts/stih416.dtsi | 144 +++++++++++++++++++++++++++++++++++
arch/arm/boot/dts/stih41x-b2020.dtsi | 12 +++
4 files changed, 164 insertions(+)
diff --git a/arch/arm/boot/dts/stih416-b2020.dts b/arch/arm/boot/dts/stih416-b2020.dts
index 5d1543b..c75b632 100644
--- a/arch/arm/boot/dts/stih416-b2020.dts
+++ b/arch/arm/boot/dts/stih416-b2020.dts
@@ -33,5 +33,9 @@
sata0: sata@fe380000{
status = "okay";
};
+
+ usb3: usb@fe340000 {
+ status = "okay";
+ };
};
};
diff --git a/arch/arm/boot/dts/stih416-b2020e.dts b/arch/arm/boot/dts/stih416-b2020e.dts
index 956fab8..9768503 100644
--- a/arch/arm/boot/dts/stih416-b2020e.dts
+++ b/arch/arm/boot/dts/stih416-b2020e.dts
@@ -51,5 +51,9 @@
sata0: sata@fe380000{
status = "okay";
};
+
+ usb3: usb@fe340000 {
+ status = "okay";
+ };
};
};
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 0f3019a..6238d9e 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -325,5 +325,149 @@
clock-names = "osc_phy";
};
+
+ ehci0: usb@0xfe1ffe00 {
+ compatible = "st,st-ehci-300x";
+ reg = <0xfe1ffe00 0x100>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb0>;
+ clocks = <&clk_s_a1_ls 0>,
+ <&clockgen_b0 0>;
+ clock-names = "ic", "clk48";
+
+ phys = <&usb2_phy>;
+ phy-names = "usb";
+ status = "okay";
+
+ resets = <&powerdown STIH416_USB0_POWERDOWN>,
+ <&softreset STIH416_USB0_SOFTRESET>;
+ reset-names = "power", "softreset";
+ };
+
+ ohci0: usb@0xfe1ffc00 {
+ compatible = "st,st-ohci-300x";
+ reg = <0xfe1ffc00 0x100>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_NONE>;
+ clocks = <&clk_s_a1_ls 0>,
+ <&clockgen_b0 0>;
+ clock-names = "ic", "clk48";
+ phys = <&usb2_phy>;
+ phy-names = "usb";
+ status = "okay";
+
+ resets = <&powerdown STIH416_USB0_POWERDOWN>,
+ <&softreset STIH416_USB0_SOFTRESET>;
+ reset-names = "power", "softreset";
+ };
+
+ ehci1: usb@0xfe203e00 {
+ compatible = "st,st-ehci-300x";
+ reg = <0xfe203e00 0x100>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb1>;
+
+ clocks = <&clk_s_a1_ls 0>,
+ <&clockgen_b0 0>;
+ clock-names = "ic", "clk48";
+
+ phys = <&usb2_phy>;
+ phy-names = "usb";
+ status = "okay";
+
+ resets = <&powerdown STIH416_USB1_POWERDOWN>,
+ <&softreset STIH416_USB1_SOFTRESET>;
+ reset-names = "power", "softreset";
+ };
+
+ ohci1: usb@0xfe203c00 {
+ compatible = "st,st-ohci-300x";
+ reg = <0xfe203c00 0x100>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
+
+ clocks = <&clk_s_a1_ls 0>,
+ <&clockgen_b0 0>;
+ clock-names = "ic", "clk48";
+ phys = <&usb2_phy>;
+ phy-names = "usb";
+ status = "okay";
+
+ resets = <&powerdown STIH416_USB1_POWERDOWN>,
+ <&softreset STIH416_USB1_SOFTRESET>;
+ reset-names = "power", "softreset";
+ };
+
+ ehci2: usb@0xfe303e00 {
+ compatible = "st,st-ehci-300x";
+ reg = <0xfe303e00 0x100>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb2>;
+
+ clocks = <&clk_s_a1_ls 0>,
+ <&clockgen_b0 0>;
+ clock-names = "ic", "clk48";
+
+ phys = <&usb2_phy>;
+ phy-names = "usb";
+ status = "okay";
+
+ resets = <&powerdown STIH416_USB2_POWERDOWN>,
+ <&softreset STIH416_USB2_SOFTRESET>;
+ reset-names = "power", "softreset";
+ };
+
+ ohci2: usb@0xfe303c00 {
+ compatible = "st,st-ohci-300x";
+ reg = <0xfe303c00 0x100>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
+ clocks = <&clk_s_a1_ls 0>,
+ <&clockgen_b0 0>;
+ clock-names = "ic", "clk48";
+ phys = <&usb2_phy>;
+ phy-names = "usb";
+ status = "okay";
+
+ resets = <&powerdown STIH416_USB2_POWERDOWN>,
+ <&softreset STIH416_USB2_SOFTRESET>;
+ reset-names = "power", "softreset";
+ };
+
+ ehci3: usb@0xfe343e00 {
+ compatible = "st,st-ehci-300x";
+ reg = <0xfe343e00 0x100>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_NONE>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usb3>;
+
+ clocks = <&clk_s_a1_ls 0>,
+ <&clockgen_b0 0>;
+ clock-names = "ic", "clk48";
+
+ phys = <&usb2_phy>;
+ phy-names = "usb";
+ status = "okay";
+
+ resets = <&powerdown STIH416_USB3_POWERDOWN>,
+ <&softreset STIH416_USB3_SOFTRESET>;
+ reset-names = "power", "softreset";
+ };
+
+ ohci3: usb@0xfe343c00 {
+ compatible = "st,st-ohci-300x";
+ reg = <0xfe343c00 0x100>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_NONE>;
+ clocks = <&clk_s_a1_ls 0>,
+ <&clockgen_b0 0>;
+ clock-names = "ic", "clk48";
+ phys = <&usb2_phy>;
+ phy-names = "usb";
+ status = "okay";
+
+ resets = <&powerdown STIH416_USB3_POWERDOWN>,
+ <&softreset STIH416_USB3_SOFTRESET>;
+ reset-names = "power", "softreset";
+ };
};
};
diff --git a/arch/arm/boot/dts/stih41x-b2020.dtsi b/arch/arm/boot/dts/stih41x-b2020.dtsi
index 487d7d8..005ab38 100644
--- a/arch/arm/boot/dts/stih41x-b2020.dtsi
+++ b/arch/arm/boot/dts/stih41x-b2020.dtsi
@@ -78,5 +78,17 @@
mmc0: sdhci@fe81e000 {
bus-width = <8>;
};
+
+ usb0: usb@fe100000 {
+ status = "okay";
+ };
+
+ usb1: usb@fe200000 {
+ status = "okay";
+ };
+
+ usb2: usb@fe300000 {
+ status = "okay";
+ };
};
};
--
1.9.1
Enable the ehci and ohci drivers in the multi_v7_defconfig so that
the USB controllers on stih41x work by default.
Signed-off-by: Peter Griffin <[email protected]>
---
arch/arm/configs/multi_v7_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index 491b7d5..c7a9517 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -318,9 +318,11 @@ CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_MVEBU=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_TEGRA=y
+CONFIG_USB_EHCI_HCD_STI=y
CONFIG_USB_EHCI_HCD_PLATFORM=y
CONFIG_USB_ISP1760_HCD=y
CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_OHCI_HCD_STI=y
CONFIG_USB_OHCI_HCD_PLATFORM=y
CONFIG_USB_STORAGE=y
CONFIG_USB_CHIPIDEA=y
--
1.9.1
This patch enables the picoPHY usb phy which is used by
the usb2 and usb3 host controllers when controlling usb2/1.1
devices. It is found in stih407 family SoC's from STMicroelectronics.
Signed-off-by: Peter Griffin <[email protected]>
---
arch/arm/configs/multi_v7_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index e13ab7e..ac7b536 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -427,6 +427,7 @@ CONFIG_OMAP_USB2=y
CONFIG_TI_PIPE3=y
CONFIG_PHY_MIPHY365X=y
CONFIG_PHY_STIH41X_USB=y
+CONFIG_PHY_STIH407_USB=y
CONFIG_PHY_SUN4I_USB=y
CONFIG_EXT4_FS=y
CONFIG_VFAT_FS=y
--
1.9.1
On Friday 07 November 2014 11:57:45 Peter Griffin wrote:
> diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
> index 0f3019a..6238d9e 100644
> --- a/arch/arm/boot/dts/stih416.dtsi
> +++ b/arch/arm/boot/dts/stih416.dtsi
> @@ -325,5 +325,149 @@
> clock-names = "osc_phy";
>
> };
> +
> + ehci0: usb@0xfe1ffe00 {
Please drop the '0x' from the unit address in all instances.
> + compatible = "st,st-ehci-300x";
> + reg = <0xfe1ffe00 0x100>;
> + interrupts = <GIC_SPI 148 IRQ_TYPE_NONE>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usb0>;
> + clocks = <&clk_s_a1_ls 0>,
> + <&clockgen_b0 0>;
> + clock-names = "ic", "clk48";
> +
> + phys = <&usb2_phy>;
> + phy-names = "usb";
> + status = "okay";
No need to list 'status="okay"', it's the default. It might
make sense to change this to 'status="disabled"' though, if the ports
might be unused on some boards.
> mmc0: sdhci@fe81e000 {
> bus-width = <8>;
> };
> +
> + usb0: usb@fe100000 {
> + status = "okay";
> + };
> +
> + usb1: usb@fe200000 {
> + status = "okay";
> + };
> +
> + usb2: usb@fe300000 {
> + status = "okay";
> + };
I don't understand this part: why do you add extra nodes here that only
contain a status property?
Note that if you add the devices to the per-soc file instead of the
per-board file, you can just access the nodes by label.
Arnd
On Friday 07 November 2014 11:57:53 Peter Griffin wrote:
> diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi
> new file mode 100644
> index 0000000..862bb2f
> --- /dev/null
> +++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
> @@ -0,0 +1,73 @@
> +/*
> + * Copyright (C) 2014 STMicroelectronics (R&D) Limited.
> + * Author: Giuseppe Cavallaro <[email protected]>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +/ {
> + chosen {
> + bootargs = "console=ttyAS0,115200";
> + linux,stdout-path = &sbc_serial0;
> + };
> +
> + memory {
> + device_type = "memory";
> + reg = <0x40000000 0x80000000>;
> + };
> +
> + aliases {
> + ttyAS0 = &sbc_serial0;
> + };
> +
>
Please leave these in the per-board file, each board would have different
values, so it makes no sense to have them in the shared file.
Arnd
On Friday 07 November 2014 11:57:54 Peter Griffin wrote:
> +
> + soc {
> +
> + ohci0: usb@9a03c00 {
> + status = "okay";
> + };
> +
> + ehci0: usb@9a03e00 {
> + status = "okay";
> + };
> +
> + ohci1: usb@9a83c00 {
> + status = "okay";
> + };
> +
> + ehci1: usb@9a83e00 {
> + status = "okay";
> + };
> + };
> +};
>
These seem to refer to an existing device in the base dtsi file. Just put the label
in the shared file and remove the exact names here. Alternatively, drop the labels
you don't use.
Arnd
Hi Peter,
On 11/07/2014 12:57 PM, Peter Griffin wrote:
> The STiH410 is an advanced multi-HD AVC processor with 3D graphics acceleration
> and 1.5-GHz ARM Cortex-A9 SMP CPU part of the stih407 family.
>
> It has wide connectivity including USB 3.0, PCI-e, SATA and gigabit ethernet.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> arch/arm/boot/dts/Makefile | 1 +
> arch/arm/boot/dts/stih410-b2120.dts | 42 +++++
> arch/arm/boot/dts/stih410-clock.dtsi | 338 +++++++++++++++++++++++++++++++++++
You are adding a new board also, not only clocks.
Please fix the commit title.
> 3 files changed, 381 insertions(+)
> create mode 100644 arch/arm/boot/dts/stih410-b2120.dts
> create mode 100644 arch/arm/boot/dts/stih410-clock.dtsi
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 38c89ca..04cf4a4 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -409,6 +409,7 @@ dtb-$(CONFIG_ARCH_SPEAR3XX)+= spear300-evb.dtb \
> spear320-hmi.dtb
> dtb-$(CONFIG_ARCH_SPEAR6XX)+= spear600-evb.dtb
> dtb-$(CONFIG_ARCH_STI)+= stih407-b2120.dtb \
> + stih410-b2120.dtb \
> stih415-b2000.dtb \
> stih415-b2020.dtb \
> stih416-b2000.dtb \
> diff --git a/arch/arm/boot/dts/stih410-b2120.dts b/arch/arm/boot/dts/stih410-b2120.dts
> new file mode 100644
> index 0000000..06ee73b
> --- /dev/null
> +++ b/arch/arm/boot/dts/stih410-b2120.dts
> @@ -0,0 +1,42 @@
> +/*
> + * Copyright (C) 2014 STMicroelectronics (R&D) Limited.
> + * Author: Peter Griffin <[email protected]>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + */
> +/dts-v1/;
> +#include "stih407-clock.dtsi"
This file should be included by a SoC dtsi file, not a board file, no?
> +#include "stih407-family.dtsi"
> +#include "stihxxx-b2120.dtsi"
> +/ {
> + model = "STiH410 B2120";
> + compatible = "st,stih410-b2120", "st,stih410";
> +
> + aliases {
> + ohci0 = &ohci0;
> + ehci0 = &ehci0;
> + ohci1 = &ohci1;
> + ehci1 = &ehci1;
> + };
> +
> + soc {
> +
> + ohci0: usb@9a03c00 {
> + status = "okay";
> + };
> +
> + ehci0: usb@9a03e00 {
> + status = "okay";
> + };
> +
> + ohci1: usb@9a83c00 {
> + status = "okay";
> + };
> +
> + ehci1: usb@9a83e00 {
> + status = "okay";
> + };
> + };
> +};
>
<snip>
Hi Peter,
On 11/07/2014 12:57 PM, Peter Griffin wrote:
> The stih410 has some additional usb controllers. This patch adds the
> dt nodes which will enabled them to function correctly.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> arch/arm/boot/dts/stih407.dtsi | 60 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi
> index 967ec39..5e01db2 100644
> --- a/arch/arm/boot/dts/stih407.dtsi
> +++ b/arch/arm/boot/dts/stih407.dtsi
Shouldn't you create a new stih410.dtsi file, to clearly highlight these
USB2 controller are not present on STiH407?
If you create this file, you could also include the stih410-clocks.dtsi
file in it.
> @@ -321,5 +321,65 @@
> reset-names = "global",
> "port";
> };
> +
> + ohci0: usb@9a03c00 {
> + compatible = "st,st-ohci-300x";
> + status = "disabled";
> + reg = <0x9a03c00 0x100>;
> + interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
> + clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
> + resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
> + <&softreset STIH407_USB2_PORT0_SOFTRESET>;
> + reset-names = "power", "softreset";
> +
> + phys = <&usb2_picophy0>;
> + phy-names = "usb";
> + };
> +
> + ehci0: usb@9a03e00 {
> + compatible = "st,st-ehci-300x";
> + status = "disabled";
> + reg = <0x9a03e00 0x100>;
> + interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usb0>;
> + clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
> + resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
> + <&softreset STIH407_USB2_PORT0_SOFTRESET>;
> + reset-names = "power", "softreset";
> +
> + phys = <&usb2_picophy0>;
> + phy-names = "usb";
> + };
> +
> + ohci1: usb@9a83c00 {
> + compatible = "st,st-ohci-300x";
> + status = "disabled";
> + reg = <0x9a83c00 0x100>;
> + interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
> + clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
> + resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
> + <&softreset STIH407_USB2_PORT1_SOFTRESET>;
> + reset-names = "power", "softreset";
> +
> + phys = <&usb2_picophy1>;
> + phy-names = "usb";
> + };
> +
> + ehci1: usb@9a83e00 {
> + compatible = "st,st-ehci-300x";
> + status = "disabled";
> + reg = <0x9a83e00 0x100>;
> + interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usb1>;
> + clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
> + resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
> + <&softreset STIH407_USB2_PORT1_SOFTRESET>;
> + reset-names = "power", "softreset";
> +
> + phys = <&usb2_picophy1>;
> + phy-names = "usb";
> + };
> };
> };
On Fri, 07 Nov 2014, Peter Griffin wrote:
> At the moment we don't take a reference on some core interconnect
> clocks which means when CCF turns off unused clocks the SoC will
> hang. As a temp soltuion we will boot with clk_ignore_unused
> parameter for all b2120 boards.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> arch/arm/boot/dts/stihxxx-b2120.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi
> index 862bb2f..7280b6d 100644
> --- a/arch/arm/boot/dts/stihxxx-b2120.dtsi
> +++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi
> @@ -8,7 +8,7 @@
> */
> / {
> chosen {
> - bootargs = "console=ttyAS0,115200";
> + bootargs = "console=ttyAS0,115200 clk_ignore_unused";
Acked-by: Lee Jones <[email protected]>
Although, hopefully we won't require this for too much longer.
> linux,stdout-path = &sbc_serial0;
> };
>
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
On Fri, 07 Nov 2014, Peter Griffin wrote:
> The stih410 has some additional usb controllers. This patch adds the
> dt nodes which will enabled them to function correctly.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> arch/arm/boot/dts/stih407.dtsi | 60 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi
> index 967ec39..5e01db2 100644
> --- a/arch/arm/boot/dts/stih407.dtsi
> +++ b/arch/arm/boot/dts/stih407.dtsi
> @@ -321,5 +321,65 @@
> reset-names = "global",
> "port";
> };
> +
> + ohci0: usb@9a03c00 {
> + compatible = "st,st-ohci-300x";
> + status = "disabled";
Being picky, I like to see the node status at the bottom in clear
view, but apart from that patch looks good:
Acked-by: Lee Jones <[email protected]>
> + reg = <0x9a03c00 0x100>;
> + interrupts = <GIC_SPI 180 IRQ_TYPE_NONE>;
> + clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
> + resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
> + <&softreset STIH407_USB2_PORT0_SOFTRESET>;
> + reset-names = "power", "softreset";
> +
> + phys = <&usb2_picophy0>;
> + phy-names = "usb";
> + };
> +
> + ehci0: usb@9a03e00 {
> + compatible = "st,st-ehci-300x";
> + status = "disabled";
> + reg = <0x9a03e00 0x100>;
> + interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usb0>;
> + clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
> + resets = <&powerdown STIH407_USB2_PORT0_POWERDOWN>,
> + <&softreset STIH407_USB2_PORT0_SOFTRESET>;
> + reset-names = "power", "softreset";
> +
> + phys = <&usb2_picophy0>;
> + phy-names = "usb";
> + };
> +
> + ohci1: usb@9a83c00 {
> + compatible = "st,st-ohci-300x";
> + status = "disabled";
> + reg = <0x9a83c00 0x100>;
> + interrupts = <GIC_SPI 181 IRQ_TYPE_NONE>;
> + clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
> + resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
> + <&softreset STIH407_USB2_PORT1_SOFTRESET>;
> + reset-names = "power", "softreset";
> +
> + phys = <&usb2_picophy1>;
> + phy-names = "usb";
> + };
> +
> + ehci1: usb@9a83e00 {
> + compatible = "st,st-ehci-300x";
> + status = "disabled";
> + reg = <0x9a83e00 0x100>;
> + interrupts = <GIC_SPI 153 IRQ_TYPE_NONE>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_usb1>;
> + clocks = <&clk_s_c0_flexgen CLK_TX_ICN_DISP_0>;
> + resets = <&powerdown STIH407_USB2_PORT1_POWERDOWN>,
> + <&softreset STIH407_USB2_PORT1_SOFTRESET>;
> + reset-names = "power", "softreset";
> +
> + phys = <&usb2_picophy1>;
> + phy-names = "usb";
> + };
> };
> };
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
On Fri, 07 Nov 2014, Peter Griffin wrote:
> This patch adds the required pin configiguration for the extra usb
> controllers found on the stih410 device.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> arch/arm/boot/dts/stih407-pinctrl.dtsi | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
Acked-by: Lee Jones <[email protected]>
> diff --git a/arch/arm/boot/dts/stih407-pinctrl.dtsi b/arch/arm/boot/dts/stih407-pinctrl.dtsi
> index 402844c..fdaad5d 100644
> --- a/arch/arm/boot/dts/stih407-pinctrl.dtsi
> +++ b/arch/arm/boot/dts/stih407-pinctrl.dtsi
> @@ -539,6 +539,24 @@
> };
> };
>
> + usb0 {
> + pinctrl_usb0: usb2-0 {
> + st,pins {
> + usb-oc-detect = <&pio35 0 ALT1 IN>;
> + usb-pwr-enable = <&pio35 1 ALT1 OUT>;
> + };
> + };
> + };
> +
> + usb1 {
> + pinctrl_usb1: usb2-1 {
> + st,pins {
> + usb-oc-detect = <&pio35 2 ALT1 IN>;
> + usb-pwr-enable = <&pio35 3 ALT1 OUT>;
> + };
> + };
> + };
> +
> usb3 {
> pinctrl_usb3: usb3-2 {
> st,pins {
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
On Fri, 07 Nov 2014, Peter Griffin wrote:
> Although most clock outputs are the same as stih407 SoC, stih410
> also has some additional new clock outputs.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> include/dt-bindings/clock/stih410-clks.h | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
> create mode 100644 include/dt-bindings/clock/stih410-clks.h
>
> diff --git a/include/dt-bindings/clock/stih410-clks.h b/include/dt-bindings/clock/stih410-clks.h
> new file mode 100644
> index 0000000..2c5d6ff
> --- /dev/null
> +++ b/include/dt-bindings/clock/stih410-clks.h
> @@ -0,0 +1,24 @@
> +/*
> + * This header provides constants clk index STMicroelectronics
> + * STiH410 SoC.
> + */
> +#ifndef _DT_BINDINGS_CLK_STIH410
> +#define _DT_BINDINGS_CLK_STIH410
> +#include "stih407-clks.h"
Nit: Please add a newline between the sentries and #include.
Apart from that, looks good:
Acked-by: Lee Jones <[email protected]>
> +/* STiH410 introduces new clock outputs compared to STiH407 */
> +
> +/* CLOCKGEN C0 */
> +#define CLK_TX_ICN_HADES 32
> +#define CLK_RX_ICN_HADES 33
> +#define CLK_ICN_REG_16 34
> +#define CLK_PP_HADES 35
> +#define CLK_CLUST_HADES 36
> +#define CLK_HWPE_HADES 37
> +#define CLK_FC_HADES 38
> +
> +/* CLOCKGEN D0 */
> +#define CLK_PCMR10_MASTER 4
> +#define CLK_USB2_PHY 5
> +
> +#endif
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
On Fri, 07 Nov 2014, Peter Griffin wrote:
> This patch adds the dt nodes for the usb2 picophy found on the stih407
> family of devices. It is used on stih410 and later devices with the ehci/ohci usb
> controller, and is also used as the usb2 phy with the dwc3 usb3 controller.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> arch/arm/boot/dts/stih407.dtsi | 46 ++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 46 insertions(+)
>
> diff --git a/arch/arm/boot/dts/stih407.dtsi b/arch/arm/boot/dts/stih407.dtsi
> index 50637f5..967ec39 100644
> --- a/arch/arm/boot/dts/stih407.dtsi
> +++ b/arch/arm/boot/dts/stih407.dtsi
> @@ -275,5 +275,51 @@
>
> status = "disabled";
> };
> +
> + /* Generic picoPHY */
> + usb2_picophy0: usbpicophy@0 {
> + compatible = "st,stih407-usb2-phy";
> + reg = <0xf8 0x04>, /* syscfg 5062 */
> + <0xf4 0x04>; /* syscfg 5061 */
Are there really only 2 32bit registers to control this h/w?
> + reg-names = "param",
> + "ctrl";
Superflous indentation after 'reg = ' and 'reg-names = '.
> + #phy-cells = <0>;
> +
> + st,syscfg = <&syscfg_core>;
> + resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
> + <&picophyreset STIH407_PICOPHY0_RESET>;
> + reset-names = "global",
> + "port";
May as well put these on the same line.
> + };
> +
> + usb2_picophy1: usbpicophy@1 {
> + compatible = "st,stih407-usb2-phy";
> + #phy-cells = <0>;
> + reg = <0xfc 0x04>, /* syscfg 5063 */
> + <0xf4 0x04>; /* syscfg 5061 */
> + reg-names = "param",
> + "ctrl";
> +
> + st,syscfg = <&syscfg_core>;
> + resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
> + <&picophyreset STIH407_PICOPHY1_RESET>;
> + reset-names = "global",
> + "port";
> + };
> +
> + usb2_picophy2: usbpicophy@2 {
> + compatible = "st,stih407-usb2-phy";
> + #phy-cells = <0>;
> + reg = <0x100 0x04>, /* syscfg 5064 */
> + <0xf4 0x04>; /* syscfg 5061 */
> + reg-names = "param",
> + "ctrl";
> +
> + st,syscfg = <&syscfg_core>;
> + resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
> + <&picophyreset STIH407_PICOPHY2_RESET>;
> + reset-names = "global",
> + "port";
> + };
> };
> };
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
On Fri, 07 Nov 2014, Peter Griffin wrote:
> This patch enables the picoPHY usb phy which is used by
> the usb2 and usb3 host controllers when controlling usb2/1.1
> devices. It is found in stih407 family SoC's from STMicroelectronics.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> arch/arm/configs/multi_v7_defconfig | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Lee Jones <[email protected]>
> diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
> index e13ab7e..ac7b536 100644
> --- a/arch/arm/configs/multi_v7_defconfig
> +++ b/arch/arm/configs/multi_v7_defconfig
> @@ -427,6 +427,7 @@ CONFIG_OMAP_USB2=y
> CONFIG_TI_PIPE3=y
> CONFIG_PHY_MIPHY365X=y
> CONFIG_PHY_STIH41X_USB=y
> +CONFIG_PHY_STIH407_USB=y
> CONFIG_PHY_SUN4I_USB=y
> CONFIG_EXT4_FS=y
> CONFIG_VFAT_FS=y
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
On Fri, 07 Nov 2014, Peter Griffin wrote:
> This driver is used by the ehci / ohci usb controllers on stih415/6 SoCs.
>
> Signed-off-by: Peter Griffin <[email protected]>
> Acked-by: Kishon Vijay Abraham I <[email protected]>
> ---
> arch/arm/configs/multi_v7_defconfig | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Lee Jones <[email protected]>
> diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
> index c7a9517..e13ab7e 100644
> --- a/arch/arm/configs/multi_v7_defconfig
> +++ b/arch/arm/configs/multi_v7_defconfig
> @@ -426,6 +426,7 @@ CONFIG_PWM_VT8500=y
> CONFIG_OMAP_USB2=y
> CONFIG_TI_PIPE3=y
> CONFIG_PHY_MIPHY365X=y
> +CONFIG_PHY_STIH41X_USB=y
> CONFIG_PHY_SUN4I_USB=y
> CONFIG_EXT4_FS=y
> CONFIG_VFAT_FS=y
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
On Fri, 07 Nov 2014, Peter Griffin wrote:
> Enable the ehci and ohci drivers in the multi_v7_defconfig so that
> the USB controllers on stih41x work by default.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> arch/arm/configs/multi_v7_defconfig | 2 ++
> 1 file changed, 2 insertions(+)
Acked-by: Lee Jones <[email protected]>
> diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
> index 491b7d5..c7a9517 100644
> --- a/arch/arm/configs/multi_v7_defconfig
> +++ b/arch/arm/configs/multi_v7_defconfig
> @@ -318,9 +318,11 @@ CONFIG_USB_XHCI_HCD=y
> CONFIG_USB_XHCI_MVEBU=y
> CONFIG_USB_EHCI_HCD=y
> CONFIG_USB_EHCI_TEGRA=y
> +CONFIG_USB_EHCI_HCD_STI=y
> CONFIG_USB_EHCI_HCD_PLATFORM=y
> CONFIG_USB_ISP1760_HCD=y
> CONFIG_USB_OHCI_HCD=y
> +CONFIG_USB_OHCI_HCD_STI=y
> CONFIG_USB_OHCI_HCD_PLATFORM=y
> CONFIG_USB_STORAGE=y
> CONFIG_USB_CHIPIDEA=y
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
On Fri, 07 Nov 2014, Peter Griffin wrote:
> This usb picophy is found on stih415/6 SoC.
Then shouldn't it live in stih41x.dtsi?
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> arch/arm/boot/dts/stih416.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
> index 1137bdf..0f3019a 100644
> --- a/arch/arm/boot/dts/stih416.dtsi
> +++ b/arch/arm/boot/dts/stih416.dtsi
> @@ -316,5 +316,14 @@
>
> status = "disabled";
> };
> +
> + usb2_phy: usb2phy@0 {
> + compatible = "st,stih416-usb-phy";
> + #phy-cells = <0>;
> + st,syscfg = <&syscfg_rear>;
> + clocks = <&clk_sysin>;
> + clock-names = "osc_phy";
> +
Remove this '\n'.
> + };
> };
> };
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
On Fri, 07 Nov 2014, Peter Griffin wrote:
> This patch adds the required pin config for all usb controllers
> on the stih416.
>
> Signed-off-by: Peter Griffin <[email protected]>
> ---
> arch/arm/boot/dts/stih416-pinctrl.dtsi | 34 ++++++++++++++++++++++++++++++++++
> 1 file changed, 34 insertions(+)
Acked-by: Lee Jones <[email protected]>
> diff --git a/arch/arm/boot/dts/stih416-pinctrl.dtsi b/arch/arm/boot/dts/stih416-pinctrl.dtsi
> index c2025bc..9cccf2d 100644
> --- a/arch/arm/boot/dts/stih416-pinctrl.dtsi
> +++ b/arch/arm/boot/dts/stih416-pinctrl.dtsi
> @@ -147,6 +147,15 @@
> };
> };
>
> + usb {
> + pinctrl_usb3: usb3 {
> + st,pins {
> + oc-detect = <&pio40 0 ALT1 IN>;
> + pwr-enable = <&pio40 1 ALT1 OUT>;
> + };
> + };
> + };
> +
> sbc_i2c1 {
> pinctrl_sbc_i2c1_default: sbc_i2c1-default {
> st,pins {
> @@ -318,6 +327,16 @@
> };
> };
>
> + usb {
> + pinctrl_usb0: usb0 {
> + st,pins {
> + oc-detect = <&pio9 4 ALT1 IN>;
> + pwr-enable = <&pio9 5 ALT1 OUT>;
> + };
> + };
> + };
> +
> +
> i2c1 {
> pinctrl_i2c1_default: i2c1-default {
> st,pins {
> @@ -506,6 +525,21 @@
> };
> };
> };
> +
> + usb {
> + pinctrl_usb1: usb1 {
> + st,pins {
> + oc-detect = <&pio18 0 ALT1 IN>;
> + pwr-enable = <&pio18 1 ALT1 OUT>;
> + };
> + };
> + pinctrl_usb2: usb2 {
> + st,pins {
> + oc-detect = <&pio18 2 ALT1 IN>;
> + pwr-enable = <&pio18 3 ALT1 OUT>;
> + };
> + };
> + };
> };
>
> pin-controller-fvdp-fe {
--
Lee Jones
Linaro STMicroelectronics Landing Team Lead
Linaro.org │ Open source software for ARM SoCs
Follow Linaro: Facebook | Twitter | Blog
Hi Arnd,
Thanks for reviewing.
On Fri, 07 Nov 2014, Arnd Bergmann wrote:
> > + ehci0: usb@0xfe1ffe00 {
>
> Please drop the '0x' from the unit address in all instances.
Ok, fixed in v2
>
> > + compatible = "st,st-ehci-300x";
> > + reg = <0xfe1ffe00 0x100>;
> > + interrupts = <GIC_SPI 148 IRQ_TYPE_NONE>;
> > + pinctrl-names = "default";
> > + pinctrl-0 = <&pinctrl_usb0>;
> > + clocks = <&clk_s_a1_ls 0>,
> > + <&clockgen_b0 0>;
> > + clock-names = "ic", "clk48";
> > +
> > + phys = <&usb2_phy>;
> > + phy-names = "usb";
> > + status = "okay";
>
> No need to list 'status="okay"', it's the default. It might
> make sense to change this to 'status="disabled"' though, if the ports
> might be unused on some boards.
ok, removed in v2
>
> > mmc0: sdhci@fe81e000 {
> > bus-width = <8>;
> > };
> > +
> > + usb0: usb@fe100000 {
> > + status = "okay";
> > + };
> > +
> > + usb1: usb@fe200000 {
> > + status = "okay";
> > + };
> > +
> > + usb2: usb@fe300000 {
> > + status = "okay";
> > + };
>
> I don't understand this part: why do you add extra nodes here that only
> contain a status property?
Good spot, this is a bit of legacy code which I should have removed before submitting.
It's removed in v2.
regards,
Peter.
Hi Arnd,
Thanks for reviewing.
> On Friday 07 November 2014 11:57:54 Peter Griffin wrote:
> > +
> > + soc {
> > +
> > + ohci0: usb@9a03c00 {
> > + status = "okay";
> > + };
> > +
> > + ehci0: usb@9a03e00 {
> > + status = "okay";
> > + };
> > +
> > + ohci1: usb@9a83c00 {
> > + status = "okay";
> > + };
> > +
> > + ehci1: usb@9a83e00 {
> > + status = "okay";
> > + };
> > + };
> > +};
> >
>
> These seem to refer to an existing device in the base dtsi file. Just put the label
> in the shared file and remove the exact names here. Alternatively, drop the labels
> you don't use.
Based on Maximes feedback in V2 I've created a seperate stih410.dtsi file
which has the extra ehci / ohci device nodes in it. This means they don't need to be
enabled in the board file any more.
regards,
Peter.
Hi Lee,
Thanks for reviewing.
On Mon, 10 Nov 2014, Lee Jones wrote:
> On Fri, 07 Nov 2014, Peter Griffin wrote:
>
> > This usb picophy is found on stih415/6 SoC.
>
> Then shouldn't it live in stih41x.dtsi?
No, it is the same ip block, and underlying driver, but needs a different
compatible string as it's wired up to different sysconfig registers on the SoC.
>
> > Signed-off-by: Peter Griffin <[email protected]>
> > ---
> > arch/arm/boot/dts/stih416.dtsi | 9 +++++++++
> > 1 file changed, 9 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
> > index 1137bdf..0f3019a 100644
> > --- a/arch/arm/boot/dts/stih416.dtsi
> > +++ b/arch/arm/boot/dts/stih416.dtsi
> > @@ -316,5 +316,14 @@
> >
> > status = "disabled";
> > };
> > +
> > + usb2_phy: usb2phy@0 {
> > + compatible = "st,stih416-usb-phy";
> > + #phy-cells = <0>;
> > + st,syscfg = <&syscfg_rear>;
> > + clocks = <&clk_sysin>;
> > + clock-names = "osc_phy";
> > +
>
> Remove this '\n'.
Fixed in v2.
regards,
Peter.
Hi Lee,
Thanks for reviewing.
On Mon, 10 Nov 2014, Lee Jones wrote:
> > + reg = <0xf8 0x04>, /* syscfg 5062 */
> > + <0xf4 0x04>; /* syscfg 5061 */
>
> Are there really only 2 32bit registers to control this h/w?
Yes
>
> > + reg-names = "param",
> > + "ctrl";
>
> Superflous indentation after 'reg = ' and 'reg-names = '.
Fixed in v2.
> > + st,syscfg = <&syscfg_core>;
> > + resets = <&softreset STIH407_PICOPHY_SOFTRESET>,
> > + <&picophyreset STIH407_PICOPHY0_RESET>;
> > + reset-names = "global",
> > + "port";
>
> May as well put these on the same line.
Fixed in v2.
regards,
Peter.