This series of patches fixes several discrepancies between the
AM57/DRA7 clock tree description and the actual hardware behavior and
frequencies. With these changes a more complete picture of the clock
tree is represented for a few of the clocks and their resulting
frequencies.
From: "J.D. Schroeder" <[email protected]>
This commit fixes the clock data inside the DRA7xx clocks device tree
structure for the gmac_gmii_ref_clk_div clock. This clock is actually
the GMAC_MAIN_CLK and has nothing to do with the register at address
0x4a0093d0. If CLKSEL_REF bit 24 inside of CM_GMAC_GMAC_CLKCTRL, is
set to 1 in order to use the GMAC_RMII_CLK instead of the
GMAC_RMII_HS_CLK, the kernel generates a clock divider warning:
WARNING: CPU: 0 PID: 0 at drivers/clk/clk-divider.c:129 clk_divider_recalc_rate+0xa8/0xe0()
gmac_gmii_ref_clk_div: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set
By properly configuring the gmac_gmii_ref_clk_div (GMAC_MAIN_CLK) to
have the parent of dpll_gmac_m2_ck always divided by 2 the warning is
resolved and the clock tree is fixed up.
Additionally, a new clock called rmii_50mhz_clk_mux is defined that
does utilize CM_GMAC_GMAC_CLKCTRL[24] CLKSEL_REF to configure the
source clock for the RMII_50MHZ_CLK.
Signed-off-by: J.D. Schroeder <[email protected]>
Reviewed-by: Trenton Andres <[email protected]>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index d0bae06..9d1a583 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -1710,13 +1710,20 @@
reg = <0x0c00>;
};
- gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
+ rmii_50mhz_clk_mux: rmii_50mhz_clk_mux {
#clock-cells = <0>;
- compatible = "ti,divider-clock";
- clocks = <&dpll_gmac_m2_ck>;
+ compatible = "ti,mux-clock";
+ clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>;
ti,bit-shift = <24>;
reg = <0x13d0>;
- ti,dividers = <2>;
+ };
+
+ gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&dpll_gmac_m2_ck>;
+ clock-mult = <1>;
+ clock-div = <2>;
};
gmac_rft_clk_mux: gmac_rft_clk_mux {
--
1.9.1
From: "J.D. Schroeder" <[email protected]>
This commit fixes the 32kHz clock (sys_32k_ck) calculation to be
correctly based on the SYS_CLK1 (sys_clkin1) frequency. Based on the
TRM CTRL_CORE_BOOTSTRAP[9:8] SPEEDSELECT, set by the SYSBOOT[9:8]
board jumpers according to the SYS_CLK1 frequency, the frequency of
the 32kHz FUNC_32K_CLK is set to SYS_CLK1/610. The following
sys_32k_ck frequencies get used for different SYS_CLK1 frequencies:
0b00: Unknown -> 32768 Hz crystal from CLKIN_32K pin
0b01: 20 MHz -> 32787 Hz clock (SYS_CLK1/610)
0b10: 27 MHz -> 44262 Hz clock (SYS_CLK1/610)
0b11: 19.2 MHz -> 31475 Hz clock (SYS_CLK1/610)
Signed-off-by: J.D. Schroeder <[email protected]>
Reviewed-by: Ben McCauley <[email protected]>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 28 ++++++++++++++++++++++------
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index 9d1a583..a514fc3 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -98,12 +98,6 @@
clock-frequency = <32768>;
};
- sys_32k_ck: sys_32k_ck {
- #clock-cells = <0>;
- compatible = "fixed-clock";
- clock-frequency = <32768>;
- };
-
virt_12000000_ck: virt_12000000_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
@@ -2177,4 +2171,26 @@
ti,bit-shift = <22>;
reg = <0x0558>;
};
+
+ sys_32kin: sys_32kin {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ };
+
+ sys_clkin1_32k_div: sys_clkin1_32k_div {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&sys_clkin1>;
+ clock-mult = <1>;
+ clock-div = <610>;
+ };
+
+ sys_32k_ck: sys_32k_ck {
+ #clock-cells = <0>;
+ compatible = "ti,mux-clock";
+ clocks = <&sys_32kin>, <&sys_clkin1_32k_div>, <&sys_clkin1_32k_div>, <&sys_clkin1_32k_div>;
+ ti,bit-shift = <8>;
+ reg = <0x06c4>;
+ };
};
--
1.9.1
From: "J.D. Schroeder" <[email protected]>
This commit updates the OSC_32K_CLK (secure_32k_clk_src_ck) frequency
from the precise 32kHz frequency (i.e., 32.768 kHz) to the more
accurate frequency of ~34.6 kHz. Actual measured frequencies of the
clock vary from board to board anywhere from 34.4 kHz up to 34.8 kHz.
Signed-off-by: J.D. Schroeder <[email protected]>
Reviewed-by: Trenton Andres <[email protected]>
---
arch/arm/boot/dts/dra7xx-clocks.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
index a514fc3..4501140 100644
--- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
+++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
@@ -95,7 +95,7 @@
secure_32k_clk_src_ck: secure_32k_clk_src_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
- clock-frequency = <32768>;
+ clock-frequency = <34600>; /* approximate frequency */
};
virt_12000000_ck: virt_12000000_ck {
--
1.9.1
Hi,
* J.D. Schroeder <[email protected]> [160426 10:57]:
> This series of patches fixes several discrepancies between the
> AM57/DRA7 clock tree description and the actual hardware behavior and
> frequencies. With these changes a more complete picture of the clock
> tree is represented for a few of the clocks and their resulting
> frequencies.
Are any of these needed for the v4.6-rc cycle?
Adding Tero to Cc so he can review the changes.
Regards,
Tony
On 04/26/2016 01:13 PM, Tony Lindgren wrote:
> Are any of these needed for the v4.6-rc cycle?
I understand that these are arriving a little late especially if we don't get to rc7. However, it would be great if these could get in the v4.6 kernel release. They shouldn't be too risky to anyone, but I understand if the logistics prevent that from happening.
Thanks,
JD
On 26/04/16 20:54, J.D. Schroeder wrote:
> From: "J.D. Schroeder" <[email protected]>
>
> This commit fixes the clock data inside the DRA7xx clocks device tree
> structure for the gmac_gmii_ref_clk_div clock. This clock is actually
> the GMAC_MAIN_CLK and has nothing to do with the register at address
> 0x4a0093d0. If CLKSEL_REF bit 24 inside of CM_GMAC_GMAC_CLKCTRL, is
> set to 1 in order to use the GMAC_RMII_CLK instead of the
> GMAC_RMII_HS_CLK, the kernel generates a clock divider warning:
> WARNING: CPU: 0 PID: 0 at drivers/clk/clk-divider.c:129 clk_divider_recalc_rate+0xa8/0xe0()
> gmac_gmii_ref_clk_div: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set
>
> By properly configuring the gmac_gmii_ref_clk_div (GMAC_MAIN_CLK) to
> have the parent of dpll_gmac_m2_ck always divided by 2 the warning is
> resolved and the clock tree is fixed up.
>
> Additionally, a new clock called rmii_50mhz_clk_mux is defined that
> does utilize CM_GMAC_GMAC_CLKCTRL[24] CLKSEL_REF to configure the
> source clock for the RMII_50MHZ_CLK.
>
> Signed-off-by: J.D. Schroeder <[email protected]>
> Reviewed-by: Trenton Andres <[email protected]>
Looks like something weird happened with the clock data conversion tool
with this specific clock. Seems to be the only buggy instance in our
clock data across SoCs. Good catch.
Acked-by: Tero Kristo <[email protected]>
> ---
> arch/arm/boot/dts/dra7xx-clocks.dtsi | 15 +++++++++++----
> 1 file changed, 11 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
> index d0bae06..9d1a583 100644
> --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
> +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
> @@ -1710,13 +1710,20 @@
> reg = <0x0c00>;
> };
>
> - gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
> + rmii_50mhz_clk_mux: rmii_50mhz_clk_mux {
> #clock-cells = <0>;
> - compatible = "ti,divider-clock";
> - clocks = <&dpll_gmac_m2_ck>;
> + compatible = "ti,mux-clock";
> + clocks = <&dpll_gmac_h11x2_ck>, <&rmii_clk_ck>;
> ti,bit-shift = <24>;
> reg = <0x13d0>;
> - ti,dividers = <2>;
> + };
> +
> + gmac_gmii_ref_clk_div: gmac_gmii_ref_clk_div {
> + #clock-cells = <0>;
> + compatible = "fixed-factor-clock";
> + clocks = <&dpll_gmac_m2_ck>;
> + clock-mult = <1>;
> + clock-div = <2>;
> };
>
> gmac_rft_clk_mux: gmac_rft_clk_mux {
>
On 26/04/16 20:54, J.D. Schroeder wrote:
> From: "J.D. Schroeder" <[email protected]>
>
> This commit fixes the 32kHz clock (sys_32k_ck) calculation to be
> correctly based on the SYS_CLK1 (sys_clkin1) frequency. Based on the
> TRM CTRL_CORE_BOOTSTRAP[9:8] SPEEDSELECT, set by the SYSBOOT[9:8]
> board jumpers according to the SYS_CLK1 frequency, the frequency of
> the 32kHz FUNC_32K_CLK is set to SYS_CLK1/610. The following
> sys_32k_ck frequencies get used for different SYS_CLK1 frequencies:
> 0b00: Unknown -> 32768 Hz crystal from CLKIN_32K pin
> 0b01: 20 MHz -> 32787 Hz clock (SYS_CLK1/610)
> 0b10: 27 MHz -> 44262 Hz clock (SYS_CLK1/610)
> 0b11: 19.2 MHz -> 31475 Hz clock (SYS_CLK1/610)
>
> Signed-off-by: J.D. Schroeder <[email protected]>
> Reviewed-by: Ben McCauley <[email protected]>
A patch doing the same thing is already in mainline, see:
commit eea08802f586acd6aef377d1b4a541821013cc0b
Author: Keerthy <[email protected]>
Date: Mon Apr 4 11:07:15 2016 +0530
ARM: dts: dra7: Correct clock tree for sys_32k_ck
So, this one can be ignored.
-Tero
> ---
> arch/arm/boot/dts/dra7xx-clocks.dtsi | 28 ++++++++++++++++++++++------
> 1 file changed, 22 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
> index 9d1a583..a514fc3 100644
> --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
> +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
> @@ -98,12 +98,6 @@
> clock-frequency = <32768>;
> };
>
> - sys_32k_ck: sys_32k_ck {
> - #clock-cells = <0>;
> - compatible = "fixed-clock";
> - clock-frequency = <32768>;
> - };
> -
> virt_12000000_ck: virt_12000000_ck {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> @@ -2177,4 +2171,26 @@
> ti,bit-shift = <22>;
> reg = <0x0558>;
> };
> +
> + sys_32kin: sys_32kin {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + };
> +
> + sys_clkin1_32k_div: sys_clkin1_32k_div {
> + #clock-cells = <0>;
> + compatible = "fixed-factor-clock";
> + clocks = <&sys_clkin1>;
> + clock-mult = <1>;
> + clock-div = <610>;
> + };
> +
> + sys_32k_ck: sys_32k_ck {
> + #clock-cells = <0>;
> + compatible = "ti,mux-clock";
> + clocks = <&sys_32kin>, <&sys_clkin1_32k_div>, <&sys_clkin1_32k_div>, <&sys_clkin1_32k_div>;
> + ti,bit-shift = <8>;
> + reg = <0x06c4>;
> + };
> };
>
On 26/04/16 20:54, J.D. Schroeder wrote:
> From: "J.D. Schroeder" <[email protected]>
>
> This commit updates the OSC_32K_CLK (secure_32k_clk_src_ck) frequency
> from the precise 32kHz frequency (i.e., 32.768 kHz) to the more
> accurate frequency of ~34.6 kHz. Actual measured frequencies of the
> clock vary from board to board anywhere from 34.4 kHz up to 34.8 kHz.
Uhm, if you have a board specific, accurate value for this clock, you
should update it in the board file itself. This definition is going to
be used across all the DRA7 / AM57xx boards, which can very likely have
different crystal accuracies.
So, NAK.
-Tero
>
> Signed-off-by: J.D. Schroeder <[email protected]>
> Reviewed-by: Trenton Andres <[email protected]>
> ---
> arch/arm/boot/dts/dra7xx-clocks.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/dra7xx-clocks.dtsi b/arch/arm/boot/dts/dra7xx-clocks.dtsi
> index a514fc3..4501140 100644
> --- a/arch/arm/boot/dts/dra7xx-clocks.dtsi
> +++ b/arch/arm/boot/dts/dra7xx-clocks.dtsi
> @@ -95,7 +95,7 @@
> secure_32k_clk_src_ck: secure_32k_clk_src_ck {
> #clock-cells = <0>;
> compatible = "fixed-clock";
> - clock-frequency = <32768>;
> + clock-frequency = <34600>; /* approximate frequency */
> };
>
> virt_12000000_ck: virt_12000000_ck {
>
On 04/27/2016 06:40 AM, Tero Kristo wrote:
> On 26/04/16 20:54, J.D. Schroeder wrote:
>> This commit fixes the 32kHz clock (sys_32k_ck) calculation to be
>> correctly based on the SYS_CLK1 (sys_clkin1) frequency. Based on the
>> TRM CTRL_CORE_BOOTSTRAP[9:8] SPEEDSELECT, set by the SYSBOOT[9:8]
>> board jumpers according to the SYS_CLK1 frequency, the frequency of
>> the 32kHz FUNC_32K_CLK is set to SYS_CLK1/610. The following
>> sys_32k_ck frequencies get used for different SYS_CLK1 frequencies:
>> 0b00: Unknown -> 32768 Hz crystal from CLKIN_32K pin
>> 0b01: 20 MHz -> 32787 Hz clock (SYS_CLK1/610)
>> 0b10: 27 MHz -> 44262 Hz clock (SYS_CLK1/610)
>> 0b11: 19.2 MHz -> 31475 Hz clock (SYS_CLK1/610)
>
> A patch doing the same thing is already in mainline, see:
>
> commit eea08802f586acd6aef377d1b4a541821013cc0b
> Author: Keerthy <[email protected]>
> Date: Mon Apr 4 11:07:15 2016 +0530
>
> ARM: dts: dra7: Correct clock tree for sys_32k_ck
>
> So, this one can be ignored.
My change had no issue when applying to the tip of master and I'm not seeing
that SHA1 in mainline. Are you saying it is in another repo ready to be sent
to mainline for the next release cycle?
On 04/27/2016 06:49 AM, Tero Kristo wrote:
> On 26/04/16 20:54, J.D. Schroeder wrote:
>> From: "J.D. Schroeder" <[email protected]>
>>
>> This commit updates the OSC_32K_CLK (secure_32k_clk_src_ck) frequency
>> from the precise 32kHz frequency (i.e., 32.768 kHz) to the more
>> accurate frequency of ~34.6 kHz. Actual measured frequencies of the
>> clock vary from board to board anywhere from 34.4 kHz up to 34.8 kHz.
>
> Uhm, if you have a board specific, accurate value for this clock, you should
> update it in the board file itself. This definition is going to be used across
> all the DRA7 / AM57xx boards, which can very likely have different crystal
> accuracies.
>
> So, NAK.
The source of this clock is internal to the processor and not specific to how
the processor is configured or what clocks are coming in. The approximate
frequency of 34.4-34.8 kHz is generated internal to the processor through some
type of oscillator, not external. The problem is that the clock tree gives the
impression that this is a 32.768 kHz clock source, when in fact it is *not*
that. Both the name and the frequency are misleading. My change is an attempt
to clarify the actual behavior of the clock and keep someone else from using
the clock as a true 32.768 kHz clock when it is more than 5% off that
particular frequency. I would even consider changing the name of the clock as
that too is misleading, but opted not to since that would be more disruptive.
If you are seeing 32.768 kHz come out of this clock source then I must have an
issue with my silicon and we can discuss off line. However, if you configure
this as one of the clock out sources and see something in the range of ~34
kHz, I still think the change is a valid change as it clarifies the true
behavior of the hardware. Am I missing something?
* Tero Kristo <[email protected]> [160427 04:22]:
> On 26/04/16 20:54, J.D. Schroeder wrote:
> >From: "J.D. Schroeder" <[email protected]>
> >
> >This commit fixes the clock data inside the DRA7xx clocks device tree
> >structure for the gmac_gmii_ref_clk_div clock. This clock is actually
> >the GMAC_MAIN_CLK and has nothing to do with the register at address
> >0x4a0093d0. If CLKSEL_REF bit 24 inside of CM_GMAC_GMAC_CLKCTRL, is
> >set to 1 in order to use the GMAC_RMII_CLK instead of the
> >GMAC_RMII_HS_CLK, the kernel generates a clock divider warning:
> > WARNING: CPU: 0 PID: 0 at drivers/clk/clk-divider.c:129 clk_divider_recalc_rate+0xa8/0xe0()
> > gmac_gmii_ref_clk_div: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set
> >
> >By properly configuring the gmac_gmii_ref_clk_div (GMAC_MAIN_CLK) to
> >have the parent of dpll_gmac_m2_ck always divided by 2 the warning is
> >resolved and the clock tree is fixed up.
> >
> >Additionally, a new clock called rmii_50mhz_clk_mux is defined that
> >does utilize CM_GMAC_GMAC_CLKCTRL[24] CLKSEL_REF to configure the
> >source clock for the RMII_50MHZ_CLK.
> >
> >Signed-off-by: J.D. Schroeder <[email protected]>
> >Reviewed-by: Trenton Andres <[email protected]>
>
> Looks like something weird happened with the clock data conversion tool with
> this specific clock. Seems to be the only buggy instance in our clock data
> across SoCs. Good catch.
>
> Acked-by: Tero Kristo <[email protected]>
Applying into omap-for-v4.6/fixes thanks.
Tony
* Tony Lindgren <[email protected]> [160427 09:39]:
> * Tero Kristo <[email protected]> [160427 04:22]:
> > On 26/04/16 20:54, J.D. Schroeder wrote:
> > >From: "J.D. Schroeder" <[email protected]>
> > >
> > >This commit fixes the clock data inside the DRA7xx clocks device tree
> > >structure for the gmac_gmii_ref_clk_div clock. This clock is actually
> > >the GMAC_MAIN_CLK and has nothing to do with the register at address
> > >0x4a0093d0. If CLKSEL_REF bit 24 inside of CM_GMAC_GMAC_CLKCTRL, is
> > >set to 1 in order to use the GMAC_RMII_CLK instead of the
> > >GMAC_RMII_HS_CLK, the kernel generates a clock divider warning:
> > > WARNING: CPU: 0 PID: 0 at drivers/clk/clk-divider.c:129 clk_divider_recalc_rate+0xa8/0xe0()
> > > gmac_gmii_ref_clk_div: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set
> > >
> > >By properly configuring the gmac_gmii_ref_clk_div (GMAC_MAIN_CLK) to
> > >have the parent of dpll_gmac_m2_ck always divided by 2 the warning is
> > >resolved and the clock tree is fixed up.
> > >
> > >Additionally, a new clock called rmii_50mhz_clk_mux is defined that
> > >does utilize CM_GMAC_GMAC_CLKCTRL[24] CLKSEL_REF to configure the
> > >source clock for the RMII_50MHZ_CLK.
> > >
> > >Signed-off-by: J.D. Schroeder <[email protected]>
> > >Reviewed-by: Trenton Andres <[email protected]>
> >
> > Looks like something weird happened with the clock data conversion tool with
> > this specific clock. Seems to be the only buggy instance in our clock data
> > across SoCs. Good catch.
> >
> > Acked-by: Tero Kristo <[email protected]>
>
> Applying into omap-for-v4.6/fixes thanks.
Actually then we end up creating self-inflicted merge conflict
here with next. So let's wait a bit on this one as it's harmless.
J.D. can you please rebase this against current Linux next?
Note the recent unit name and unit address fixes for warnings
with make W=1 dtbs.
Regards,
Tony
On 27/04/16 17:06, J.D. Schroeder wrote:
> On 04/27/2016 06:40 AM, Tero Kristo wrote:
>> On 26/04/16 20:54, J.D. Schroeder wrote:
>>> This commit fixes the 32kHz clock (sys_32k_ck) calculation to be
>>> correctly based on the SYS_CLK1 (sys_clkin1) frequency. Based on the
>>> TRM CTRL_CORE_BOOTSTRAP[9:8] SPEEDSELECT, set by the SYSBOOT[9:8]
>>> board jumpers according to the SYS_CLK1 frequency, the frequency of
>>> the 32kHz FUNC_32K_CLK is set to SYS_CLK1/610. The following
>>> sys_32k_ck frequencies get used for different SYS_CLK1 frequencies:
>>> 0b00: Unknown -> 32768 Hz crystal from CLKIN_32K pin
>>> 0b01: 20 MHz -> 32787 Hz clock (SYS_CLK1/610)
>>> 0b10: 27 MHz -> 44262 Hz clock (SYS_CLK1/610)
>>> 0b11: 19.2 MHz -> 31475 Hz clock (SYS_CLK1/610)
>>
>> A patch doing the same thing is already in mainline, see:
>>
>> commit eea08802f586acd6aef377d1b4a541821013cc0b
>> Author: Keerthy <[email protected]>
>> Date: Mon Apr 4 11:07:15 2016 +0530
>>
>> ARM: dts: dra7: Correct clock tree for sys_32k_ck
>>
>> So, this one can be ignored.
>
> My change had no issue when applying to the tip of master and I'm not seeing
> that SHA1 in mainline. Are you saying it is in another repo ready to be sent
> to mainline for the next release cycle?
>
The patch is merged already in 4.6-rc3.
Which repo / version are you using as baseline?
-Tero
On 04/27/2016 02:47 PM, Tero Kristo wrote:
> The patch is merged already in 4.6-rc3.
>
> Which repo / version are you using as baseline?
I'm using git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git. I
can see eea08802f586acd6aef377d1b4a541821013cc0b as of now. However, I don't
think it was included in -rc3 or even -rc5 which is what I was basing my
changes on. It looks like it got merged in late last night in Linus tree. No
big deal. The change is nearly identical to my solution so no need to pursue mine.
Please disregard this patch.
Thanks,
JD