changes v5:
- use dcfg->offset instead of priv->offset.
changes v4:
- change dependencies in Kconfig
- remove unused includes and order them alphabetically
- set MODULE_LICENSE = GPL v2
- remove unused int err variable
changes v3:
- remove regmap and offset properties.
changes v2:
- correct typos: Registe, parrent...
Oleksij Rempel (3):
nvmem: dt: document SNVS LPGPR binding
nvmem: add snvs_lpgpr driver
ARM: dts: imx6qdl.dtsi: add "fsl,imx6q-snvs-lpgpr" node
.../devicetree/bindings/nvmem/snvs-lpgpr.txt | 19 +++
arch/arm/boot/dts/imx6qdl.dtsi | 4 +
drivers/nvmem/Kconfig | 10 ++
drivers/nvmem/Makefile | 2 +
drivers/nvmem/snvs_lpgpr.c | 138 +++++++++++++++++++++
5 files changed, 173 insertions(+)
create mode 100644 Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
create mode 100644 drivers/nvmem/snvs_lpgpr.c
--
2.11.0
This is a driver for Low Power General Purpose Register (LPGPR)
available on i.MX6 SoCs in Secure Non-Volatile Storage (SNVS)
of this chip.
It is a 32-bit read/write register located in the low power domain.
Since LPGPR is located in the battery-backed power domain, LPGPR can
be used by any application for retaining data during an SoC power-down
mode.
Signed-off-by: Oleksij Rempel <[email protected]>
---
drivers/nvmem/Kconfig | 10 ++++
drivers/nvmem/Makefile | 2 +
drivers/nvmem/snvs_lpgpr.c | 138 +++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 150 insertions(+)
create mode 100644 drivers/nvmem/snvs_lpgpr.c
diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index 101ced4c84be..ea3044c5d6ee 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -144,4 +144,14 @@ config MESON_EFUSE
This driver can also be built as a module. If so, the module
will be called nvmem_meson_efuse.
+config NVMEM_SNVS_LPGPR
+ tristate "Support for Low Power General Purpose Register"
+ depends on SOC_IMX6 || COMPILE_TEST
+ help
+ This is a driver for Low Power General Purpose Register (LPGPR) available on
+ i.MX6 SoCs in Secure Non-Volatile Storage (SNVS) of this chip.
+
+ This driver can also be built as a module. If so, the module
+ will be called nvmem-snvs-lpgpr.
+
endif
diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
index 173140658693..4c589184acee 100644
--- a/drivers/nvmem/Makefile
+++ b/drivers/nvmem/Makefile
@@ -30,3 +30,5 @@ obj-$(CONFIG_NVMEM_VF610_OCOTP) += nvmem-vf610-ocotp.o
nvmem-vf610-ocotp-y := vf610-ocotp.o
obj-$(CONFIG_MESON_EFUSE) += nvmem_meson_efuse.o
nvmem_meson_efuse-y := meson-efuse.o
+obj-$(CONFIG_NVMEM_SNVS_LPGPR) += nvmem_snvs_lpgpr.o
+nvmem_snvs_lpgpr-y := snvs_lpgpr.o
diff --git a/drivers/nvmem/snvs_lpgpr.c b/drivers/nvmem/snvs_lpgpr.c
new file mode 100644
index 000000000000..acb3ddc0d990
--- /dev/null
+++ b/drivers/nvmem/snvs_lpgpr.c
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2015 Pengutronix, Steffen Trumtrar <[email protected]>
+ * Copyright (c) 2017 Pengutronix, Oleksij Rempel <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/nvmem-provider.h>
+#include <linux/of_device.h>
+#include <linux/regmap.h>
+
+struct snvs_lpgpr_cfg {
+ int offset;
+};
+
+struct snvs_lpgpr_priv {
+ struct device_d *dev;
+ struct regmap *regmap;
+ struct nvmem_config cfg;
+ const struct snvs_lpgpr_cfg *dcfg;
+};
+
+static const struct snvs_lpgpr_cfg snvs_lpgpr_cfg_imx6q = {
+ .offset = 0x68,
+};
+
+static int snvs_lpgpr_write(void *context, unsigned int offset, void *_val,
+ size_t bytes)
+{
+ struct snvs_lpgpr_priv *priv = context;
+ const struct snvs_lpgpr_cfg *dcfg = priv->dcfg;
+ const u32 *val = _val;
+ int i = 0, words = bytes / 4;
+
+ while (words--)
+ regmap_write(priv->regmap, dcfg->offset + offset + (i++ * 4),
+ *val++);
+
+ return 0;
+}
+
+static int snvs_lpgpr_read(void *context, unsigned int offset, void *_val,
+ size_t bytes)
+{
+ struct snvs_lpgpr_priv *priv = context;
+ const struct snvs_lpgpr_cfg *dcfg = priv->dcfg;
+ u32 *val = _val;
+ int i = 0, words = bytes / 4;
+
+ while (words--)
+ regmap_read(priv->regmap, dcfg->offset + offset + (i++ * 4),
+ val++);
+
+ return 0;
+}
+
+static int snvs_lpgpr_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *node = dev->of_node;
+ struct device_node *syscon_node;
+ struct snvs_lpgpr_priv *priv;
+ struct nvmem_config *cfg;
+ struct nvmem_device *nvmem;
+ const struct snvs_lpgpr_cfg *dcfg;
+
+ if (!node)
+ return -ENOENT;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ dcfg = of_device_get_match_data(dev);
+ if (!dcfg)
+ return -EINVAL;
+
+ syscon_node = of_get_parent(node);
+ if (!syscon_node)
+ return -ENODEV;
+
+ priv->regmap = syscon_node_to_regmap(syscon_node);
+ of_node_put(syscon_node);
+ if (IS_ERR(priv->regmap))
+ return PTR_ERR(priv->regmap);
+
+ priv->dcfg = dcfg;
+
+ cfg = &priv->cfg;
+ cfg->priv = priv;
+ cfg->name = dev_name(dev);
+ cfg->dev = dev;
+ cfg->stride = 4,
+ cfg->word_size = 4,
+ cfg->size = 4,
+ cfg->owner = THIS_MODULE,
+ cfg->reg_read = snvs_lpgpr_read,
+ cfg->reg_write = snvs_lpgpr_write,
+
+ nvmem = nvmem_register(cfg);
+ if (IS_ERR(nvmem))
+ return PTR_ERR(nvmem);
+
+ platform_set_drvdata(pdev, nvmem);
+
+ return 0;
+}
+
+static int snvs_lpgpr_remove(struct platform_device *pdev)
+{
+ struct nvmem_device *nvmem = platform_get_drvdata(pdev);
+
+ return nvmem_unregister(nvmem);
+}
+
+static const struct of_device_id snvs_lpgpr_dt_ids[] = {
+ { .compatible = "fsl,imx6q-snvs-lpgpr", .data = &snvs_lpgpr_cfg_imx6q },
+ { },
+};
+MODULE_DEVICE_TABLE(of, snvs_lpgpr_dt_ids);
+
+static struct platform_driver snvs_lpgpr_driver = {
+ .probe = snvs_lpgpr_probe,
+ .remove = snvs_lpgpr_remove,
+ .driver = {
+ .name = "snvs_lpgpr",
+ .of_match_table = snvs_lpgpr_dt_ids,
+ },
+};
+module_platform_driver(snvs_lpgpr_driver);
+
+MODULE_AUTHOR("Oleksij Rempel <[email protected]>");
+MODULE_DESCRIPTION("Low Power General Purpose Register in i.MX6 Secure Non-Volatile Storage");
+MODULE_LICENSE("GPL v2");
--
2.11.0
Documentation bindings for the Low Power General Purpose Register
available on i.MX6 SoCs in the Secure Non-Volatile Storage.
Signed-off-by: Oleksij Rempel <[email protected]>
---
.../devicetree/bindings/nvmem/snvs-lpgpr.txt | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
create mode 100644 Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
diff --git a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
new file mode 100644
index 000000000000..21910fb3159f
--- /dev/null
+++ b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
@@ -0,0 +1,19 @@
+Device tree bindings for Low Power General Purpose Register found in i.MX6Q/D
+Secure Non-Volatile Storage.
+
+This DT node should be represented as a sub-node of a "syscon",
+"simple-mfd" node.
+
+Required properties:
+- compatible: should be:
+ "fsl,imx6q-snvs-lpgpr" for Freescale i.MX6Q/D/DL/S
+
+Example:
+snvs: snvs@020cc000 {
+ compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
+ reg = <0x020cc000 0x4000>;
+
+ snvs_lpgpr: snvs-lpgpr {
+ compatible = "fsl,imx6q-snvs-lpgpr";
+ };
+};
--
2.11.0
This node is for Low Power General Purpose Register which can
be used as Non-Volatile Storage.
Signed-off-by: Oleksij Rempel <[email protected]>
---
arch/arm/boot/dts/imx6qdl.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index e426faa9c243..94e992558238 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -769,6 +769,10 @@
mask = <0x60>;
status = "disabled";
};
+
+ snvs_lpgpr: snvs-lpgpr {
+ compatible = "fsl,imx6q-snvs-lpgpr";
+ };
};
epit1: epit@020d0000 { /* EPIT1 */
--
2.11.0
Hi Oleksij,
Am 09.06.2017 um 14:57 schrieb Oleksij Rempel:
> Documentation bindings for the Low Power General Purpose Register
> available on i.MX6 SoCs in the Secure Non-Volatile Storage.
>
> Signed-off-by: Oleksij Rempel <[email protected]>
> ---
> .../devicetree/bindings/nvmem/snvs-lpgpr.txt | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
>
> diff --git a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
> new file mode 100644
> index 000000000000..21910fb3159f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
> @@ -0,0 +1,19 @@
> +Device tree bindings for Low Power General Purpose Register found in i.MX6Q/D
> +Secure Non-Volatile Storage.
> +
> +This DT node should be represented as a sub-node of a "syscon",
> +"simple-mfd" node.
> +
> +Required properties:
> +- compatible: should be:
> + "fsl,imx6q-snvs-lpgpr" for Freescale i.MX6Q/D/DL/S
> +
> +Example:
> +snvs: snvs@020cc000 {
> + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
> + reg = <0x020cc000 0x4000>;
> +
> + snvs_lpgpr: snvs-lpgpr {
> + compatible = "fsl,imx6q-snvs-lpgpr";
according to the reference manual at least the clock "lp_ipg_clk_s" is
required for register R/W access.
So it should be added to the binding and enabled by the driver.
Best regards
Stefan
> + };
> +};
Hi Oleksij,
please add the NXP guys in CC in order to give them a chance to review.
Am 09.06.2017 um 14:57 schrieb Oleksij Rempel:
> This is a driver for Low Power General Purpose Register (LPGPR)
> available on i.MX6 SoCs in Secure Non-Volatile Storage (SNVS)
> of this chip.
>
> It is a 32-bit read/write register located in the low power domain.
> Since LPGPR is located in the battery-backed power domain, LPGPR can
> be used by any application for retaining data during an SoC power-down
> mode.
>
> Signed-off-by: Oleksij Rempel <[email protected]>
> ---
> drivers/nvmem/Kconfig | 10 ++++
> drivers/nvmem/Makefile | 2 +
> drivers/nvmem/snvs_lpgpr.c | 138 +++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 150 insertions(+)
> create mode 100644 drivers/nvmem/snvs_lpgpr.c
>
> diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
> index 101ced4c84be..ea3044c5d6ee 100644
> --- a/drivers/nvmem/Kconfig
> +++ b/drivers/nvmem/Kconfig
> @@ -144,4 +144,14 @@ config MESON_EFUSE
> This driver can also be built as a module. If so, the module
> will be called nvmem_meson_efuse.
>
> +config NVMEM_SNVS_LPGPR
> + tristate "Support for Low Power General Purpose Register"
> + depends on SOC_IMX6 || COMPILE_TEST
> + help
> + This is a driver for Low Power General Purpose Register (LPGPR) available on
> + i.MX6 SoCs in Secure Non-Volatile Storage (SNVS) of this chip.
> +
> + This driver can also be built as a module. If so, the module
> + will be called nvmem-snvs-lpgpr.
> +
> endif
> diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
> index 173140658693..4c589184acee 100644
> --- a/drivers/nvmem/Makefile
> +++ b/drivers/nvmem/Makefile
> @@ -30,3 +30,5 @@ obj-$(CONFIG_NVMEM_VF610_OCOTP) += nvmem-vf610-ocotp.o
> nvmem-vf610-ocotp-y := vf610-ocotp.o
> obj-$(CONFIG_MESON_EFUSE) += nvmem_meson_efuse.o
> nvmem_meson_efuse-y := meson-efuse.o
> +obj-$(CONFIG_NVMEM_SNVS_LPGPR) += nvmem_snvs_lpgpr.o
> +nvmem_snvs_lpgpr-y := snvs_lpgpr.o
> diff --git a/drivers/nvmem/snvs_lpgpr.c b/drivers/nvmem/snvs_lpgpr.c
> new file mode 100644
> index 000000000000..acb3ddc0d990
> --- /dev/null
> +++ b/drivers/nvmem/snvs_lpgpr.c
> @@ -0,0 +1,138 @@
> +/*
> + * Copyright (c) 2015 Pengutronix, Steffen Trumtrar <[email protected]>
> + * Copyright (c) 2017 Pengutronix, Oleksij Rempel <[email protected]>
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2
> + * as published by the Free Software Foundation.
> + */
> +
> +#include <linux/mfd/syscon.h>
> +#include <linux/module.h>
> +#include <linux/nvmem-provider.h>
> +#include <linux/of_device.h>
> +#include <linux/regmap.h>
> +
> +struct snvs_lpgpr_cfg {
> + int offset;
> +};
> +
> +struct snvs_lpgpr_priv {
> + struct device_d *dev;
> + struct regmap *regmap;
> + struct nvmem_config cfg;
> + const struct snvs_lpgpr_cfg *dcfg;
> +};
> +
> +static const struct snvs_lpgpr_cfg snvs_lpgpr_cfg_imx6q = {
> + .offset = 0x68,
> +};
> +
> +static int snvs_lpgpr_write(void *context, unsigned int offset, void *_val,
> + size_t bytes)
> +{
> + struct snvs_lpgpr_priv *priv = context;
> + const struct snvs_lpgpr_cfg *dcfg = priv->dcfg;
> + const u32 *val = _val;
> + int i = 0, words = bytes / 4;
> +
> + while (words--)
> + regmap_write(priv->regmap, dcfg->offset + offset + (i++ * 4),
> + *val++);
according to the reference manual "57.9.14 SNVS_LP General Purpose
Register (SNVS_LPGPR)":
When GPR_SL or GPR_HL bit is set, the register cannot be programmed.
I think the driver should handle this error case properly.
Best regards
Stefan
On 09/06/2017 15:57, Oleksij Rempel wrote:
> Documentation bindings for the Low Power General Purpose Register
> available on i.MX6 SoCs in the Secure Non-Volatile Storage.
>
> Signed-off-by: Oleksij Rempel <[email protected]>
> ---
> .../devicetree/bindings/nvmem/snvs-lpgpr.txt | 19
> +++++++++++++++++++
> 1 file changed, 19 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
>
> diff --git a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
> b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
> new file mode 100644
> index 000000000000..21910fb3159f
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
> @@ -0,0 +1,19 @@
> +Device tree bindings for Low Power General Purpose Register found in
> i.MX6Q/D
> +Secure Non-Volatile Storage.
> +
> +This DT node should be represented as a sub-node of a "syscon",
> +"simple-mfd" node.
> +
> +Required properties:
> +- compatible: should be:
> + "fsl,imx6q-snvs-lpgpr" for Freescale i.MX6Q/D/DL/S
I've tested the basic functionality on i.MX6UL. It seems to work as is.
Please add "/UL" on the next version.
Regards,
Guy
> +
> +Example:
> +snvs: snvs@020cc000 {
> + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
> + reg = <0x020cc000 0x4000>;
> +
> + snvs_lpgpr: snvs-lpgpr {
> + compatible = "fsl,imx6q-snvs-lpgpr";
> + };
> +};
On Fri, Jun 09, 2017 at 04:59:00PM +0200, Stefan Wahren wrote:
Hi Stefan,
> Hi Oleksij,
>
> Am 09.06.2017 um 14:57 schrieb Oleksij Rempel:
> > Documentation bindings for the Low Power General Purpose Register
> > available on i.MX6 SoCs in the Secure Non-Volatile Storage.
> >
> > Signed-off-by: Oleksij Rempel <[email protected]>
> > ---
> > .../devicetree/bindings/nvmem/snvs-lpgpr.txt | 19 +++++++++++++++++++
> > 1 file changed, 19 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
> >
> > diff --git a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
> > new file mode 100644
> > index 000000000000..21910fb3159f
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
> > @@ -0,0 +1,19 @@
> > +Device tree bindings for Low Power General Purpose Register found in i.MX6Q/D
> > +Secure Non-Volatile Storage.
> > +
> > +This DT node should be represented as a sub-node of a "syscon",
> > +"simple-mfd" node.
> > +
> > +Required properties:
> > +- compatible: should be:
> > + "fsl,imx6q-snvs-lpgpr" for Freescale i.MX6Q/D/DL/S
> > +
> > +Example:
> > +snvs: snvs@020cc000 {
> > + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
> > + reg = <0x020cc000 0x4000>;
> > +
> > + snvs_lpgpr: snvs-lpgpr {
> > + compatible = "fsl,imx6q-snvs-lpgpr";
>
> according to the reference manual at least the clock "lp_ipg_clk_s" is
> required for register R/W access.
> So it should be added to the binding and enabled by the driver.
Hm...
Non of current SNVS drives use, set or defines *_ipg_clk_s. I can't find
in the docs how can I control this clocks.
lp_ipg_clk_s and hp_ipg_clk_s depend on ipg_clk_root, which seems to be
not gated. So, it is always on. Or do I miss something.
--
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Industrial Linux Solutions | http://www.pengutronix.de/ |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
Hi Fabio,
Am 19.06.2017 um 08:06 schrieb Oleksij Rempel:
> On Fri, Jun 09, 2017 at 04:59:00PM +0200, Stefan Wahren wrote:
> Hi Stefan,
>
>> Hi Oleksij,
>>
>> Am 09.06.2017 um 14:57 schrieb Oleksij Rempel:
>>> Documentation bindings for the Low Power General Purpose Register
>>> available on i.MX6 SoCs in the Secure Non-Volatile Storage.
>>>
>>> Signed-off-by: Oleksij Rempel <[email protected]>
>>> ---
>>> .../devicetree/bindings/nvmem/snvs-lpgpr.txt | 19 +++++++++++++++++++
>>> 1 file changed, 19 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
>>>
>>> diff --git a/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
>>> new file mode 100644
>>> index 000000000000..21910fb3159f
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/nvmem/snvs-lpgpr.txt
>>> @@ -0,0 +1,19 @@
>>> +Device tree bindings for Low Power General Purpose Register found in i.MX6Q/D
>>> +Secure Non-Volatile Storage.
>>> +
>>> +This DT node should be represented as a sub-node of a "syscon",
>>> +"simple-mfd" node.
>>> +
>>> +Required properties:
>>> +- compatible: should be:
>>> + "fsl,imx6q-snvs-lpgpr" for Freescale i.MX6Q/D/DL/S
>>> +
>>> +Example:
>>> +snvs: snvs@020cc000 {
>>> + compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
>>> + reg = <0x020cc000 0x4000>;
>>> +
>>> + snvs_lpgpr: snvs-lpgpr {
>>> + compatible = "fsl,imx6q-snvs-lpgpr";
>> according to the reference manual at least the clock "lp_ipg_clk_s" is
>> required for register R/W access.
>> So it should be added to the binding and enabled by the driver.
> Hm...
> Non of current SNVS drives use, set or defines *_ipg_clk_s. I can't find
> in the docs how can I control this clocks.
> lp_ipg_clk_s and hp_ipg_clk_s depend on ipg_clk_root, which seems to be
> not gated. So, it is always on. Or do I miss something.
>
do you know how the clock "lp_ipg_clk_s" should be handled?
Thanks
Stefan
Hi Stefan,
On Mon, Jun 19, 2017 at 7:58 AM, Stefan Wahren <[email protected]> wrote:
> do you know how the clock "lp_ipg_clk_s" should be handled?
As per the Reference Manual there is no CCM gating bits for this clock.
Am 19.06.2017 um 14:52 schrieb Fabio Estevam:
> Hi Stefan,
>
> On Mon, Jun 19, 2017 at 7:58 AM, Stefan Wahren <[email protected]> wrote:
>
>> do you know how the clock "lp_ipg_clk_s" should be handled?
> As per the Reference Manual there is no CCM gating bits for this clock.
I was only surprised that there is no clock handling in the driver.
Sorry, about that noise.
Hi Stefan,
On Fri, Jun 09, 2017 at 05:01:09PM +0200, Stefan Wahren wrote:
> Hi Oleksij,
>
> please add the NXP guys in CC in order to give them a chance to review.
>
> Am 09.06.2017 um 14:57 schrieb Oleksij Rempel:
> > This is a driver for Low Power General Purpose Register (LPGPR)
> > available on i.MX6 SoCs in Secure Non-Volatile Storage (SNVS)
> > of this chip.
> >
> > It is a 32-bit read/write register located in the low power domain.
> > Since LPGPR is located in the battery-backed power domain, LPGPR can
> > be used by any application for retaining data during an SoC power-down
> > mode.
> >
> > Signed-off-by: Oleksij Rempel <[email protected]>
> > ---
> > drivers/nvmem/Kconfig | 10 ++++
> > drivers/nvmem/Makefile | 2 +
> > drivers/nvmem/snvs_lpgpr.c | 138 +++++++++++++++++++++++++++++++++++++++++++++
> > 3 files changed, 150 insertions(+)
> > create mode 100644 drivers/nvmem/snvs_lpgpr.c
> >
> > diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
> > index 101ced4c84be..ea3044c5d6ee 100644
> > --- a/drivers/nvmem/Kconfig
> > +++ b/drivers/nvmem/Kconfig
> > @@ -144,4 +144,14 @@ config MESON_EFUSE
> > This driver can also be built as a module. If so, the module
> > will be called nvmem_meson_efuse.
> >
> > +config NVMEM_SNVS_LPGPR
> > + tristate "Support for Low Power General Purpose Register"
> > + depends on SOC_IMX6 || COMPILE_TEST
> > + help
> > + This is a driver for Low Power General Purpose Register (LPGPR) available on
> > + i.MX6 SoCs in Secure Non-Volatile Storage (SNVS) of this chip.
> > +
> > + This driver can also be built as a module. If so, the module
> > + will be called nvmem-snvs-lpgpr.
> > +
> > endif
> > diff --git a/drivers/nvmem/Makefile b/drivers/nvmem/Makefile
> > index 173140658693..4c589184acee 100644
> > --- a/drivers/nvmem/Makefile
> > +++ b/drivers/nvmem/Makefile
> > @@ -30,3 +30,5 @@ obj-$(CONFIG_NVMEM_VF610_OCOTP) += nvmem-vf610-ocotp.o
> > nvmem-vf610-ocotp-y := vf610-ocotp.o
> > obj-$(CONFIG_MESON_EFUSE) += nvmem_meson_efuse.o
> > nvmem_meson_efuse-y := meson-efuse.o
> > +obj-$(CONFIG_NVMEM_SNVS_LPGPR) += nvmem_snvs_lpgpr.o
> > +nvmem_snvs_lpgpr-y := snvs_lpgpr.o
> > diff --git a/drivers/nvmem/snvs_lpgpr.c b/drivers/nvmem/snvs_lpgpr.c
> > new file mode 100644
> > index 000000000000..acb3ddc0d990
> > --- /dev/null
> > +++ b/drivers/nvmem/snvs_lpgpr.c
> > @@ -0,0 +1,138 @@
> > +/*
> > + * Copyright (c) 2015 Pengutronix, Steffen Trumtrar <[email protected]>
> > + * Copyright (c) 2017 Pengutronix, Oleksij Rempel <[email protected]>
> > + *
> > + * This program is free software; you can redistribute it and/or modify
> > + * it under the terms of the GNU General Public License version 2
> > + * as published by the Free Software Foundation.
> > + */
> > +
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/module.h>
> > +#include <linux/nvmem-provider.h>
> > +#include <linux/of_device.h>
> > +#include <linux/regmap.h>
> > +
> > +struct snvs_lpgpr_cfg {
> > + int offset;
> > +};
> > +
> > +struct snvs_lpgpr_priv {
> > + struct device_d *dev;
> > + struct regmap *regmap;
> > + struct nvmem_config cfg;
> > + const struct snvs_lpgpr_cfg *dcfg;
> > +};
> > +
> > +static const struct snvs_lpgpr_cfg snvs_lpgpr_cfg_imx6q = {
> > + .offset = 0x68,
> > +};
> > +
> > +static int snvs_lpgpr_write(void *context, unsigned int offset, void *_val,
> > + size_t bytes)
> > +{
> > + struct snvs_lpgpr_priv *priv = context;
> > + const struct snvs_lpgpr_cfg *dcfg = priv->dcfg;
> > + const u32 *val = _val;
> > + int i = 0, words = bytes / 4;
> > +
> > + while (words--)
> > + regmap_write(priv->regmap, dcfg->offset + offset + (i++ * 4),
> > + *val++);
>
> according to the reference manual "57.9.14 SNVS_LP General Purpose
> Register (SNVS_LPGPR)":
>
> When GPR_SL or GPR_HL bit is set, the register cannot be programmed.
>
> I think the driver should handle this error case properly.
good point,
I'll update it.
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