Hello,
The Marvell Armada 7K/8K SoCs are composed of two parts: the AP (which
contains the CPU cores) and the CP (which contains most
peripherals). The 7K SoCs have one CP, while the 8K SoCs have two CPs,
doubling the number of available peripherals.
In terms of interrupt handling, all devices in the CPs are connected
through wired interrupt to a unit called ICU located in each CP. This
unit converts the wired interrupts from the devices into memory
transactions.
Inside the AP, there is a GIC extension called GICP, which allows a
memory write transaction to trigger a GIC SPI interrupt. The ICUs in
each CP are therefore configured to trigger a memory write into the
appropriate GICP register so that a wired interrupt from a CP device
is converted into a memory write, itself converted into a regular GIC
SPI interrupt.
Until now, the configuration of the ICU was done statically by the
firmware, and therefore the Device Tree files in Linux were specifying
directly GIC interrupts for the interrupts of CP devices. However,
with the growing number of devices in the CP, a static allocation
scheme doesn't work for the long term.
This patch series therefore makes Linux aware of the ICU: GIC SPI
interrupts are dynamically allocated, and the ICU is configured
accordingly to route a CP wired interrupt to the allocated GIC SPI
interrupt.
In detail:
- The first two patches are the Device Tree binding patches
- The third patch adds a driver for the GICP.
- The fourth patch adds the driver for the ICU.
- The fifth patch adjust Kconfig.platforms to select the GICP and ICU
drivers.
- The last patch adjusts the Device Tree files of the Armada 7K/8K to
describe and use the GICP/ICU.
Changes since v3:
- Change the API between the ICU and the GICP driver to a single
function "int mvebu_gicp_get_doorbells(struct device_node *dn,
phys_addr_t *setspi, phys_addr_t *clrspi). This allows the ICU
driver to retrieve the physical addresses of the doorbell registers
of the GICP. This API was suggested by Marc Zyngier.
- Remove a useless "*hwirq < 0" check, since hwirq is an unsigned
long pointer. Pointed by Marc Zyngier.
- Remove a bogus "put_device()" in the ICU error path. This is no
longer needed, since we are no longer doing a get_device() on the
GICP. It was a bug already present in the v3.
Changes since v2:
- Major rework of the GICP/ICU interaction, as suggested by Marc
Zyngier. Now the GICP acts as a proper MSI controller, and the ICU
driver is a consumer of MSIs provided by the GICP.
Therefore, the GICP now has a "msi-controller" property in the
Device Tree, stating it is a provider of MSIs, while the ICUs have
a "msi-parent" property pointing to the GICP, so that they allocate
MSIs from the GICP.
The only remaining non-standard interaction between ICU and GICP is
transmitting the SETSPI/CLRSPI addresses from the GICP to the
ICU. Unfortunately, the "struct msi_msg" is only designed to carry
a single address, while we need two. So we still have two function
calls from ICU to the GICP to retrieve those addresses.
Changes since v1:
- Fix the #interrupt-cells value in the ICU DT binding
example. Pointed by Marc Zyngier.
- Add details about the possible group types in the ICU DT binding
documentation, as requested by Marc Zyngier. This allowed to
discover that the list of types listed was not matching the macros
provided in <dt-bindings/interrupt-controller/mvebu-icu.h>, so this
was fixed as well.
- Changed the "gicp" property of the ICU to "marvell,gicp", as
suggested by Marc Zyngier.
- Add a marvell,spi-ranges property to the gicp node, which defines
which ranges of GIC SPI interrupts are available for us by the
GICP.
- Move more GICP logic into the gicp driver. Indeed, it was confusing
to have in the ICU driver some global logic mixed with per-ICU
logic: there is only one GICP per system, but one ICU per CP (so in
an Armada 8K we have one GICP but two ICUs). So it makes more sense
to handle the GICP aspects in one driver (which has only one
device) and the ICU aspects in another driver (which has one device
per ICU).
- Use writel_relaxed() as suggested by Marc Zyngier.
- Use irq_set_irqchip_state() in the ICU driver to clear any pending
interrupt when allocating an interrupt. This ensures we don't get
bothered by an interrupt left pending by the firmware. This
replaces a more manual pending interrupt clearing done in the GICP
driver, which wasn't suitable for edge triggered
interrupts. Suggested by Marc Zyngier.
- Use devm_kstrdup() instead of kstrdup() to fix a potential memory
leak in the error path of ICU's ->probe() function. Noticed by Marc
Zyngier.
- Change compatible strings from "marvell,gicp" to
"marvell,ap806-gicp" and "marvell,icu" to "marvell,cp110-icu", as
future versions of those IP blocks may be different. Suggested by
Yehuda Yitschak.
- Use a shorter name for the irqchip domain, suggested by Grégory
Clement.
- Rename ICU_{SATA0,SATA1}_IRQ_INT to ICU_{SATA0,SATA1}_ICU_ID to
clarify we're talking about ICU identifiers and not interrupt
numbers. Suggested by Yehuda Yitschak.
- Fix bogus message when checking the ICU group type, make sure the
message says "wrong ICU group type" and not "wrong ICU
type". Suggested by Yehuda Yitschak.
- Add a check that the ICU identifier used in the DT is not higher
than ICU_MAX_IRQS. Suggested by Yehuda Yitschak.
Best regards,
Thomas
Thomas Petazzoni (6):
dt-bindings: interrupt-controller: add DT binding for the Marvell GICP
dt-bindings: interrupt-controller: add DT binding for the Marvell ICU
irqchip: irq-mvebu-gicp: new driver for Marvell GICP
irqchip: irq-mvebu-icu: new driver for Marvell ICU
arm64: marvell: enable ICU and GICP drivers
arm64: dts: marvell: enable GICP and ICU on Armada 7K/8K
.../bindings/interrupt-controller/marvell,gicp.txt | 27 ++
.../bindings/interrupt-controller/marvell,icu.txt | 51 ++++
arch/arm64/Kconfig.platforms | 2 +
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 7 +
.../boot/dts/marvell/armada-cp110-master.dtsi | 59 +++--
.../arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 53 ++--
drivers/irqchip/Kconfig | 6 +
drivers/irqchip/Makefile | 2 +
drivers/irqchip/irq-mvebu-gicp.c | 279 ++++++++++++++++++++
drivers/irqchip/irq-mvebu-gicp.h | 12 +
drivers/irqchip/irq-mvebu-icu.c | 291 +++++++++++++++++++++
.../dt-bindings/interrupt-controller/mvebu-icu.h | 15 ++
12 files changed, 756 insertions(+), 48 deletions(-)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt
create mode 100644 drivers/irqchip/irq-mvebu-gicp.c
create mode 100644 drivers/irqchip/irq-mvebu-gicp.h
create mode 100644 drivers/irqchip/irq-mvebu-icu.c
create mode 100644 include/dt-bindings/interrupt-controller/mvebu-icu.h
--
2.9.4
This commit adds the Device Tree binding documentation for the Marvell
ICU interrupt controller, which collects wired interrupts from the
devices located into the CP110 hardware block of Marvell Armada 7K/8K,
and converts them into SPI interrupts in the GIC located in the AP
hardware block, using the GICP extension.
Signed-off-by: Thomas Petazzoni <[email protected]>
---
.../bindings/interrupt-controller/marvell,icu.txt | 51 ++++++++++++++++++++++
1 file changed, 51 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt
new file mode 100644
index 0000000..aa8bf2e
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,icu.txt
@@ -0,0 +1,51 @@
+Marvell ICU Interrupt Controller
+--------------------------------
+
+The Marvell ICU (Interrupt Consolidation Unit) controller is
+responsible for collecting all wired-interrupt sources in the CP and
+communicating them to the GIC in the AP, the unit translates interrupt
+requests on input wires to MSG memory mapped transactions to the GIC.
+
+Required properties:
+
+- compatible: Should be "marvell,cp110-icu"
+
+- reg: Should contain ICU registers location and length.
+
+- #interrupt-cells: Specifies the number of cells needed to encode an
+ interrupt source. The value shall be 3.
+
+ The 1st cell is the group type of the ICU interrupt. Possible group
+ types are:
+
+ ICU_GRP_NSR (0x0) : Shared peripheral interrupt, non-secure
+ ICU_GRP_SR (0x1) : Shared peripheral interrupt, secure
+ ICU_GRP_SEI (0x4) : System error interrupt
+ ICU_GRP_REI (0x5) : RAM error interrupt
+
+ The 2nd cell is the index of the interrupt in the ICU unit.
+
+ The 3rd cell is the type of the interrupt. See arm,gic.txt for
+ details.
+
+- interrupt-controller: Identifies the node as an interrupt
+ controller.
+
+- msi-parent: Should point to the GICP controller, the GIC extension
+ that allows to trigger interrupts using MSG memory mapped
+ transactions.
+
+Example:
+
+icu: interrupt-controller@1e0000 {
+ compatible = "marvell,cp110-icu";
+ reg = <0x1e0000 0x10>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ msi-parent = <&gicp>;
+};
+
+usb3h0: usb3@500000 {
+ interrupt-parent = <&icu>;
+ interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
+};
--
2.9.4
This commit adds the Device Tree binding documentation for the Marvell
GICP, an extension to the GIC that allows to trigger GIC SPI interrupts
using memory transactions. It is used by the ICU unit in the Marvell
CP110 block to turn wired interrupts inside the CP into SPI interrupts
at the GIC level in the AP.
Signed-off-by: Thomas Petazzoni <[email protected]>
---
.../bindings/interrupt-controller/marvell,gicp.txt | 27 ++++++++++++++++++++++
1 file changed, 27 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt
diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt
new file mode 100644
index 0000000..64a00ce
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt
@@ -0,0 +1,27 @@
+Marvell GICP Controller
+-----------------------
+
+GICP is a Marvell extension of the GIC that allows to trigger GIC SPI
+interrupts by doing a memory transaction. It is used by the ICU
+located in the Marvell CP110 to turn wired interrupts inside the CP
+into GIC SPI interrupts.
+
+Required properties:
+
+- compatible: Must be "marvell,ap806-gicp"
+
+- reg: Must be the address and size of the GICP SPI registers
+
+- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
+ for this GICP
+
+- msi-controller: indicates that this is an MSI controller
+
+Example:
+
+gicp_spi: gicp-spi@3f0040 {
+ compatible = "marvell,ap806-gicp";
+ reg = <0x3f0040 0x10>;
+ marvell,spi-ranges = <64 64>, <288 64>;
+ msi-controller;
+};
--
2.9.4
This commit modifies the Marvell EBU Armada 7K and 8K Device Tree files
to describe the ICU and GICP units, and use ICU interrupts for all
devices in the CP110 blocks.
Signed-off-by: Thomas Petazzoni <[email protected]>
---
arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 7 +++
.../boot/dts/marvell/armada-cp110-master.dtsi | 59 +++++++++++++---------
.../arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 53 ++++++++++---------
3 files changed, 71 insertions(+), 48 deletions(-)
diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
index fe41bf9..e0a9198 100644
--- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
@@ -146,6 +146,13 @@
marvell,spi-base = <128>, <136>, <144>, <152>;
};
+ gicp: gicp@3f0040 {
+ compatible = "marvell,ap806-gicp";
+ reg = <0x3f0040 0x10>;
+ marvell,spi-ranges = <64 64>, <288 64>;
+ msi-controller;
+ };
+
pic: interrupt-controller@3f0100 {
compatible = "marvell,armada-8k-pic";
reg = <0x3f0100 0x10>;
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
index ac8df52..50586de 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
@@ -44,19 +44,20 @@
* Device Tree file for Marvell Armada CP110 Master.
*/
+#include <dt-bindings/interrupt-controller/mvebu-icu.h>
+
/ {
cp110-master {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
- interrupt-parent = <&gic>;
+ interrupt-parent = <&cpm_icu>;
ranges;
config-space@f2000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
- interrupt-parent = <&gic>;
ranges = <0x0 0x0 0xf2000000 0x2000000>;
cpm_ethernet: ethernet@0 {
@@ -68,21 +69,21 @@
dma-coherent;
cpm_eth0: eth0 {
- interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>;
port-id = <0>;
gop-port-id = <0>;
status = "disabled";
};
cpm_eth1: eth1 {
- interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>;
port-id = <1>;
gop-port-id = <2>;
status = "disabled";
};
cpm_eth2: eth2 {
- interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>;
port-id = <2>;
gop-port-id = <3>;
status = "disabled";
@@ -96,6 +97,14 @@
reg = <0x12a200 0x10>;
};
+ cpm_icu: interrupt-controller@1e0000 {
+ compatible = "marvell,cp110-icu";
+ reg = <0x1e0000 0x10>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ msi-parent = <&gicp>;
+ };
+
cpm_syscon0: system-controller@440000 {
compatible = "marvell,cp110-system-controller0",
"syscon";
@@ -120,14 +129,14 @@
compatible = "marvell,armada-8k-rtc";
reg = <0x284000 0x20>, <0x284080 0x24>;
reg-names = "rtc", "rtc-soc";
- interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
};
cpm_sata0: sata@540000 {
compatible = "marvell,armada-8k-ahci",
"generic-ahci";
reg = <0x540000 0x30000>;
- interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_syscon0 1 15>;
status = "disabled";
};
@@ -137,7 +146,7 @@
"generic-xhci";
reg = <0x500000 0x4000>;
dma-coherent;
- interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_syscon0 1 22>;
status = "disabled";
};
@@ -147,7 +156,7 @@
"generic-xhci";
reg = <0x510000 0x4000>;
dma-coherent;
- interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_syscon0 1 23>;
status = "disabled";
};
@@ -195,7 +204,7 @@
reg = <0x701000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_syscon0 1 21>;
status = "disabled";
};
@@ -205,7 +214,7 @@
reg = <0x701100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_syscon0 1 21>;
status = "disabled";
};
@@ -213,7 +222,7 @@
cpm_trng: trng@760000 {
compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
reg = <0x760000 0x7d>;
- interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpm_syscon0 1 25>;
status = "okay";
};
@@ -221,7 +230,7 @@
cpm_sdhci0: sdhci@780000 {
compatible = "marvell,armada-cp110-sdhci";
reg = <0x780000 0x300>;
- interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core";
clocks = <&cpm_syscon0 1 4>;
dma-coherent;
@@ -231,13 +240,13 @@
cpm_crypto: crypto@800000 {
compatible = "inside-secure,safexcel-eip197";
reg = <0x800000 0x200000>;
- interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
+ interrupts = <ICU_GRP_NSR 87 (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+ <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
clocks = <&cpm_syscon0 1 26>;
@@ -264,8 +273,8 @@
/* non-prefetchable memory */
0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cpm_syscon0 1 13>;
status = "disabled";
@@ -290,8 +299,8 @@
/* non-prefetchable memory */
0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cpm_syscon0 1 11>;
@@ -317,8 +326,8 @@
/* non-prefetchable memory */
0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cpm_syscon0 1 12>;
diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
index 7740a75..3def18f 100644
--- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
+++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
@@ -49,14 +49,13 @@
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
- interrupt-parent = <&gic>;
+ interrupt-parent = <&cps_icu>;
ranges;
config-space@f4000000 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
- interrupt-parent = <&gic>;
ranges = <0x0 0x0 0xf4000000 0x2000000>;
cps_rtc: rtc@284000 {
@@ -75,21 +74,21 @@
dma-coherent;
cps_eth0: eth0 {
- interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>;
port-id = <0>;
gop-port-id = <0>;
status = "disabled";
};
cps_eth1: eth1 {
- interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>;
port-id = <1>;
gop-port-id = <2>;
status = "disabled";
};
cps_eth2: eth2 {
- interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>;
port-id = <2>;
gop-port-id = <3>;
status = "disabled";
@@ -103,6 +102,14 @@
reg = <0x12a200 0x10>;
};
+ cps_icu: interrupt-controller@1e0000 {
+ compatible = "marvell,cp110-icu";
+ reg = <0x1e0000 0x10>;
+ #interrupt-cells = <3>;
+ interrupt-controller;
+ msi-parent = <&gicp>;
+ };
+
cps_syscon0: system-controller@440000 {
compatible = "marvell,cp110-system-controller0",
"syscon";
@@ -127,7 +134,7 @@
compatible = "marvell,armada-8k-ahci",
"generic-ahci";
reg = <0x540000 0x30000>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_syscon0 1 15>;
status = "disabled";
};
@@ -137,7 +144,7 @@
"generic-xhci";
reg = <0x500000 0x4000>;
dma-coherent;
- interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_syscon0 1 22>;
status = "disabled";
};
@@ -147,7 +154,7 @@
"generic-xhci";
reg = <0x510000 0x4000>;
dma-coherent;
- interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_syscon0 1 23>;
status = "disabled";
};
@@ -195,7 +202,7 @@
reg = <0x701000 0x20>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_syscon0 1 21>;
status = "disabled";
};
@@ -205,7 +212,7 @@
reg = <0x701100 0x20>;
#address-cells = <1>;
#size-cells = <0>;
- interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_syscon0 1 21>;
status = "disabled";
};
@@ -213,7 +220,7 @@
cps_trng: trng@760000 {
compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
reg = <0x760000 0x7d>;
- interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cps_syscon0 1 25>;
status = "okay";
};
@@ -221,13 +228,13 @@
cps_crypto: crypto@800000 {
compatible = "inside-secure,safexcel-eip197";
reg = <0x800000 0x200000>;
- interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
+ interrupts = <ICU_GRP_NSR 87 (IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>;
+ <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
+ <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "mem", "ring0", "ring1",
"ring2", "ring3", "eip";
clocks = <&cps_syscon0 1 26>;
@@ -254,8 +261,8 @@
/* non-prefetchable memory */
0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cps_syscon0 1 13>;
status = "disabled";
@@ -280,8 +287,8 @@
/* non-prefetchable memory */
0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cps_syscon0 1 11>;
@@ -307,8 +314,8 @@
/* non-prefetchable memory */
0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
interrupt-map-mask = <0 0 0 0>;
- interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
- interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
+ interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
num-lanes = <1>;
clocks = <&cps_syscon0 1 12>;
--
2.9.4
This commit enables the newly introduced Marvell GICP and ICUs driver
for the 64-bit Marvell EBU platforms.
Signed-off-by: Thomas Petazzoni <[email protected]>
---
arch/arm64/Kconfig.platforms | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 4afcffc..bf3b505 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -106,6 +106,8 @@ config ARCH_MVEBU
select ARMADA_AP806_SYSCON
select ARMADA_CP110_SYSCON
select ARMADA_37XX_CLK
+ select MVEBU_GICP
+ select MVEBU_ICU
select MVEBU_ODMI
select MVEBU_PIC
help
--
2.9.4
This commit adds a simple driver for the Marvell GICP, a hardware unit
that converts memory writes into GIC SPI interrupts. The driver provides
a number of functions to the ICU driver to allocate GICP interrupts, and
get the physical addresses that the ICUs should write to to set/clear
interrupts.
Signed-off-by: Thomas Petazzoni <[email protected]>
---
drivers/irqchip/Kconfig | 3 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-mvebu-gicp.c | 279 +++++++++++++++++++++++++++++++++++++++
drivers/irqchip/irq-mvebu-gicp.h | 12 ++
4 files changed, 295 insertions(+)
create mode 100644 drivers/irqchip/irq-mvebu-gicp.c
create mode 100644 drivers/irqchip/irq-mvebu-gicp.h
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 478f8ac..e527ee5 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -268,6 +268,9 @@ config IRQ_MXS
select IRQ_DOMAIN
select STMP_DEVICE
+config MVEBU_GICP
+ bool
+
config MVEBU_ODMI
bool
select GENERIC_MSI_IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index b64c59b..11eb858 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_ARCH_SA1100) += irq-sa11x0.o
obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o
obj-$(CONFIG_PIC32_EVIC) += irq-pic32-evic.o
+obj-$(CONFIG_MVEBU_GICP) += irq-mvebu-gicp.o
obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
obj-$(CONFIG_MVEBU_PIC) += irq-mvebu-pic.o
obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
diff --git a/drivers/irqchip/irq-mvebu-gicp.c b/drivers/irqchip/irq-mvebu-gicp.c
new file mode 100644
index 0000000..45358ac
--- /dev/null
+++ b/drivers/irqchip/irq-mvebu-gicp.c
@@ -0,0 +1,279 @@
+/*
+ * Copyright (C) 2017 Marvell
+ *
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/msi.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+#include "irq-mvebu-gicp.h"
+
+#define GICP_SETSPI_NSR_OFFSET 0x0
+#define GICP_CLRSPI_NSR_OFFSET 0x8
+
+struct mvebu_gicp_spi_range {
+ unsigned int start;
+ unsigned int count;
+};
+
+struct mvebu_gicp {
+ struct mvebu_gicp_spi_range *spi_ranges;
+ unsigned int spi_ranges_cnt;
+ unsigned int spi_cnt;
+ unsigned long *spi_bitmap;
+ spinlock_t spi_lock;
+ struct resource *res;
+ struct device *dev;
+};
+
+static int gicp_idx_to_spi(struct mvebu_gicp *gicp, int idx)
+{
+ int i;
+
+ for (i = 0; i < gicp->spi_ranges_cnt; i++) {
+ struct mvebu_gicp_spi_range *r = &gicp->spi_ranges[i];
+
+ if (idx < r->count)
+ return r->start + idx;
+
+ idx -= r->count;
+ }
+
+ return -EINVAL;
+}
+
+int mvebu_gicp_get_doorbells(struct device_node *dn, phys_addr_t *setspi,
+ phys_addr_t *clrspi)
+{
+ struct platform_device *pdev;
+ struct mvebu_gicp *gicp;
+
+ pdev = of_find_device_by_node(dn);
+ if (!pdev)
+ return -ENODEV;
+
+ gicp = platform_get_drvdata(pdev);
+ if (!gicp)
+ return -ENODEV;
+
+ *setspi = gicp->res->start + GICP_SETSPI_NSR_OFFSET;
+ *clrspi = gicp->res->start + GICP_CLRSPI_NSR_OFFSET;
+
+ return 0;
+}
+
+static void gicp_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
+{
+ struct mvebu_gicp *gicp = data->chip_data;
+ phys_addr_t setspi = gicp->res->start + GICP_SETSPI_NSR_OFFSET;
+
+ msg->data = data->hwirq;
+ msg->address_lo = lower_32_bits(setspi);
+ msg->address_hi = upper_32_bits(setspi);
+}
+
+static struct irq_chip gicp_irq_chip = {
+ .name = "GICP",
+ .irq_mask = irq_chip_mask_parent,
+ .irq_unmask = irq_chip_unmask_parent,
+ .irq_eoi = irq_chip_eoi_parent,
+ .irq_set_affinity = irq_chip_set_affinity_parent,
+ .irq_set_type = irq_chip_set_type_parent,
+ .irq_compose_msi_msg = gicp_compose_msi_msg,
+};
+
+static int gicp_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs, void *args)
+{
+ struct mvebu_gicp *gicp = domain->host_data;
+ struct irq_fwspec fwspec;
+ unsigned int hwirq;
+ int ret;
+
+ spin_lock(&gicp->spi_lock);
+ hwirq = find_first_zero_bit(gicp->spi_bitmap, gicp->spi_cnt);
+ if (hwirq == gicp->spi_cnt) {
+ spin_unlock(&gicp->spi_lock);
+ return -ENOSPC;
+ }
+ __set_bit(hwirq, gicp->spi_bitmap);
+ spin_unlock(&gicp->spi_lock);
+
+ fwspec.fwnode = domain->parent->fwnode;
+ fwspec.param_count = 3;
+ fwspec.param[0] = GIC_SPI;
+ fwspec.param[1] = gicp_idx_to_spi(gicp, hwirq) - 32;
+ /*
+ * Assume edge rising for now, it will be properly set when
+ * ->set_type() is called
+ */
+ fwspec.param[2] = IRQ_TYPE_EDGE_RISING;
+
+ ret = irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
+ if (ret) {
+ dev_err(gicp->dev, "Cannot allocate parent IRQ\n");
+ goto free_hwirq;
+ }
+
+ ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
+ &gicp_irq_chip, gicp);
+ if (ret)
+ goto free_irqs_parent;
+
+ return 0;
+
+free_irqs_parent:
+ irq_domain_free_irqs_parent(domain, virq, nr_irqs);
+free_hwirq:
+ spin_lock(&gicp->spi_lock);
+ __clear_bit(hwirq, gicp->spi_bitmap);
+ spin_unlock(&gicp->spi_lock);
+ return ret;
+}
+
+static void gicp_irq_domain_free(struct irq_domain *domain,
+ unsigned int virq, unsigned int nr_irqs)
+{
+ struct mvebu_gicp *gicp = domain->host_data;
+ struct irq_data *d = irq_domain_get_irq_data(domain, virq);
+
+ if (d->hwirq >= gicp->spi_cnt) {
+ dev_err(gicp->dev, "Invalid hwirq %lu\n", d->hwirq);
+ return;
+ }
+
+ irq_domain_free_irqs_parent(domain, virq, nr_irqs);
+
+ spin_lock(&gicp->spi_lock);
+ __clear_bit(d->hwirq, gicp->spi_bitmap);
+ spin_unlock(&gicp->spi_lock);
+}
+
+static const struct irq_domain_ops gicp_domain_ops = {
+ .alloc = gicp_irq_domain_alloc,
+ .free = gicp_irq_domain_free,
+};
+
+static struct irq_chip gicp_msi_irq_chip = {
+ .name = "GICP",
+ .irq_set_type = irq_chip_set_type_parent,
+};
+
+static struct msi_domain_ops gicp_msi_ops = {
+};
+
+static struct msi_domain_info gicp_msi_domain_info = {
+ .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
+ .ops = &gicp_msi_ops,
+ .chip = &gicp_msi_irq_chip,
+};
+
+static int mvebu_gicp_probe(struct platform_device *pdev)
+{
+ struct mvebu_gicp *gicp;
+ struct irq_domain *inner_domain, *plat_domain, *parent_domain;
+ struct device_node *node = pdev->dev.of_node;
+ struct device_node *irq_parent_dn;
+ int ret, i;
+
+ gicp = devm_kzalloc(&pdev->dev, sizeof(*gicp), GFP_KERNEL);
+ if (!gicp)
+ return -ENOMEM;
+
+ gicp->dev = &pdev->dev;
+
+ gicp->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!gicp->res)
+ return -ENODEV;
+
+ ret = of_property_count_u32_elems(node, "marvell,spi-ranges");
+ if (ret < 0)
+ return ret;
+
+ gicp->spi_ranges_cnt = ret / 2;
+
+ gicp->spi_ranges =
+ devm_kzalloc(&pdev->dev,
+ gicp->spi_ranges_cnt *
+ sizeof(struct mvebu_gicp_spi_range),
+ GFP_KERNEL);
+ if (!gicp->spi_ranges)
+ return -ENOMEM;
+
+ for (i = 0; i < gicp->spi_ranges_cnt; i++) {
+ of_property_read_u32_index(node, "marvell,spi-ranges",
+ i * 2,
+ &gicp->spi_ranges[i].start);
+
+ of_property_read_u32_index(node, "marvell,spi-ranges",
+ i * 2 + 1,
+ &gicp->spi_ranges[i].count);
+
+ gicp->spi_cnt += gicp->spi_ranges[i].count;
+ }
+
+ gicp->spi_bitmap = devm_kzalloc(&pdev->dev,
+ BITS_TO_LONGS(gicp->spi_cnt),
+ GFP_KERNEL);
+ if (!gicp->spi_bitmap)
+ return -ENOMEM;
+
+ irq_parent_dn = of_irq_find_parent(node);
+ if (!irq_parent_dn) {
+ dev_err(&pdev->dev, "failed to find parent IRQ node\n");
+ return -ENODEV;
+ }
+
+ parent_domain = irq_find_host(irq_parent_dn);
+ if (!parent_domain) {
+ dev_err(&pdev->dev, "failed to find parent IRQ domain\n");
+ return -ENODEV;
+ }
+
+ inner_domain = irq_domain_create_hierarchy(parent_domain, 0,
+ gicp->spi_cnt,
+ of_node_to_fwnode(node),
+ &gicp_domain_ops, gicp);
+ if (!inner_domain)
+ return -ENOMEM;
+
+
+ plat_domain = platform_msi_create_irq_domain(of_node_to_fwnode(node),
+ &gicp_msi_domain_info,
+ inner_domain);
+ if (!plat_domain) {
+ irq_domain_remove(inner_domain);
+ return -ENOMEM;
+ }
+
+ platform_set_drvdata(pdev, gicp);
+
+ return 0;
+}
+
+static const struct of_device_id mvebu_gicp_of_match[] = {
+ { .compatible = "marvell,ap806-gicp", },
+ {},
+};
+
+static struct platform_driver mvebu_gicp_driver = {
+ .probe = mvebu_gicp_probe,
+ .driver = {
+ .name = "mvebu-gicp",
+ .of_match_table = mvebu_gicp_of_match,
+ },
+};
+builtin_platform_driver(mvebu_gicp_driver);
diff --git a/drivers/irqchip/irq-mvebu-gicp.h b/drivers/irqchip/irq-mvebu-gicp.h
new file mode 100644
index 0000000..89a8dc2
--- /dev/null
+++ b/drivers/irqchip/irq-mvebu-gicp.h
@@ -0,0 +1,12 @@
+#ifndef __MVEBU_GICP_H__
+#define __MVEBU_GICP_H__
+
+#include <linux/types.h>
+
+struct device_node;
+
+int mvebu_gicp_get_doorbells(struct device_node *dn, phys_addr_t *setspi,
+ phys_addr_t *clrspi);
+
+#endif /* __MVEBU_GICP_H__ */
+
--
2.9.4
The Marvell ICU unit is found in the CP110 block of the Marvell Armada
7K and 8K SoCs. It collects the wired interrupts of the devices located
in the CP110 and turns them into SPI interrupts in the GIC located in
the AP806 side of the SoC, by using a memory transaction.
Until now, the ICU was configured in a static fashion by the firmware,
and Linux was relying on this static configuration. By having Linux
configure the ICU, we are more flexible, and we can allocate dynamically
the GIC SPI interrupts only for devices that are actually in use.
The driver was initially written by Hanna Hawa <[email protected]>.
Signed-off-by: Thomas Petazzoni <[email protected]>
---
drivers/irqchip/Kconfig | 3 +
drivers/irqchip/Makefile | 1 +
drivers/irqchip/irq-mvebu-icu.c | 291 +++++++++++++++++++++
.../dt-bindings/interrupt-controller/mvebu-icu.h | 15 ++
4 files changed, 310 insertions(+)
create mode 100644 drivers/irqchip/irq-mvebu-icu.c
create mode 100644 include/dt-bindings/interrupt-controller/mvebu-icu.h
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index e527ee5..676232a 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -271,6 +271,9 @@ config IRQ_MXS
config MVEBU_GICP
bool
+config MVEBU_ICU
+ bool
+
config MVEBU_ODMI
bool
select GENERIC_MSI_IRQ_DOMAIN
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 11eb858..18fa5fa 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -70,6 +70,7 @@ obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o
obj-$(CONFIG_PIC32_EVIC) += irq-pic32-evic.o
obj-$(CONFIG_MVEBU_GICP) += irq-mvebu-gicp.o
+obj-$(CONFIG_MVEBU_ICU) += irq-mvebu-icu.o
obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
obj-$(CONFIG_MVEBU_PIC) += irq-mvebu-pic.o
obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
diff --git a/drivers/irqchip/irq-mvebu-icu.c b/drivers/irqchip/irq-mvebu-icu.c
new file mode 100644
index 0000000..efc80ee
--- /dev/null
+++ b/drivers/irqchip/irq-mvebu-icu.c
@@ -0,0 +1,291 @@
+/*
+ * Copyright (C) 2017 Marvell
+ *
+ * Hanna Hawa <[email protected]>
+ * Thomas Petazzoni <[email protected]>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/irqdomain.h>
+#include <linux/kernel.h>
+#include <linux/msi.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/interrupt-controller/mvebu-icu.h>
+
+#include "irq-mvebu-gicp.h"
+
+/* ICU registers */
+#define ICU_SETSPI_NSR_AL 0x10
+#define ICU_SETSPI_NSR_AH 0x14
+#define ICU_CLRSPI_NSR_AL 0x18
+#define ICU_CLRSPI_NSR_AH 0x1c
+#define ICU_INT_CFG(x) (0x100 + 4 * (x))
+#define ICU_INT_ENABLE BIT(24)
+#define ICU_IS_EDGE BIT(28)
+#define ICU_GROUP_SHIFT 29
+
+/* ICU definitions */
+#define ICU_MAX_IRQS 207
+#define ICU_SATA0_ICU_ID 109
+#define ICU_SATA1_ICU_ID 107
+
+struct mvebu_icu {
+ struct irq_chip irq_chip;
+ void __iomem *base;
+ struct irq_domain *domain;
+ struct device *dev;
+};
+
+struct mvebu_icu_irq_data {
+ struct mvebu_icu *icu;
+ unsigned int icu_group;
+ unsigned int type;
+};
+
+static void mvebu_icu_write_msg(struct msi_desc *desc, struct msi_msg *msg)
+{
+ struct irq_data *d = irq_get_irq_data(desc->irq);
+ struct mvebu_icu_irq_data *icu_irqd = d->chip_data;
+ struct mvebu_icu *icu = icu_irqd->icu;
+ unsigned int icu_int;
+
+ if (msg->address_lo) {
+ /* Configure the ICU with irq number & type */
+ icu_int = msg->data | ICU_INT_ENABLE;
+ if (icu_irqd->type & IRQ_TYPE_EDGE_RISING)
+ icu_int |= ICU_IS_EDGE;
+ icu_int |= icu_irqd->icu_group << ICU_GROUP_SHIFT;
+ } else {
+ /* De-configure the ICU */
+ icu_int = 0;
+ }
+
+ writel_relaxed(icu_int, icu->base + ICU_INT_CFG(d->hwirq));
+
+ /*
+ * The SATA unit has 2 ports, and a dedicated ICU entry per
+ * port. The ahci sata driver supports only one irq interrupt
+ * per SATA unit. To solve this conflict, we configure the 2
+ * SATA wired interrupts in the south bridge into 1 GIC
+ * interrupt in the north bridge. Even if only a single port
+ * is enabled, if sata node is enabled, both interrupts are
+ * configured (regardless of which port is actually in use).
+ */
+ if (d->hwirq == ICU_SATA0_ICU_ID || d->hwirq == ICU_SATA1_ICU_ID) {
+ writel_relaxed(icu_int,
+ icu->base + ICU_INT_CFG(ICU_SATA0_ICU_ID));
+ writel_relaxed(icu_int,
+ icu->base + ICU_INT_CFG(ICU_SATA1_ICU_ID));
+ }
+}
+
+static int
+mvebu_icu_irq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
+ unsigned long *hwirq, unsigned int *type)
+{
+ struct mvebu_icu *icu = d->host_data;
+ unsigned int icu_group;
+
+ /* Check the count of the parameters in dt */
+ if (WARN_ON(fwspec->param_count < 3)) {
+ dev_err(icu->dev, "wrong ICU parameter count %d\n",
+ fwspec->param_count);
+ return -EINVAL;
+ }
+
+ /* Only ICU group type is handled */
+ icu_group = fwspec->param[0];
+ if (icu_group != ICU_GRP_NSR && icu_group != ICU_GRP_SR &&
+ icu_group != ICU_GRP_SEI && icu_group != ICU_GRP_REI) {
+ dev_err(icu->dev, "wrong ICU group type %x\n", icu_group);
+ return -EINVAL;
+ }
+
+ *hwirq = fwspec->param[1];
+ if (*hwirq >= ICU_MAX_IRQS) {
+ dev_err(icu->dev, "invalid interrupt number %ld\n", *hwirq);
+ return -EINVAL;
+ }
+
+ /* Mask the type to prevent wrong DT configuration */
+ *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
+
+ return 0;
+}
+
+static int
+mvebu_icu_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs, void *args)
+{
+ int err;
+ unsigned long hwirq;
+ struct irq_fwspec *fwspec = args;
+ struct mvebu_icu *icu = platform_msi_get_host_data(domain);
+ struct mvebu_icu_irq_data *icu_irqd;
+
+ icu_irqd = kmalloc(sizeof(*icu_irqd), GFP_KERNEL);
+ if (!icu_irqd)
+ return -ENOMEM;
+
+ err = mvebu_icu_irq_domain_translate(domain, fwspec, &hwirq,
+ &icu_irqd->type);
+ if (err) {
+ dev_err(icu->dev, "failed to translate ICU parameters\n");
+ goto free_irqd;
+ }
+
+ icu_irqd->icu_group = fwspec->param[0];
+ icu_irqd->icu = icu;
+
+ err = platform_msi_domain_alloc(domain, virq, nr_irqs);
+ if (err) {
+ dev_err(icu->dev, "failed to allocate ICU interrupt in parent domain\n");
+ goto free_irqd;
+ }
+
+ /* Make sure there is no interrupt left pending by the firmware */
+ err = irq_set_irqchip_state(virq, IRQCHIP_STATE_PENDING, false);
+ if (err)
+ goto free_msi;
+
+ err = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
+ &icu->irq_chip, icu_irqd);
+ if (err) {
+ dev_err(icu->dev, "failed to set the data to IRQ domain\n");
+ goto free_msi;
+ }
+
+ return 0;
+
+free_msi:
+ platform_msi_domain_free(domain, virq, nr_irqs);
+free_irqd:
+ kfree(icu_irqd);
+ return err;
+}
+
+static void
+mvebu_icu_irq_domain_free(struct irq_domain *domain, unsigned int virq,
+ unsigned int nr_irqs)
+{
+ struct irq_data *d = irq_get_irq_data(virq);
+ struct mvebu_icu_irq_data *icu_irqd = d->chip_data;
+
+ kfree(icu_irqd);
+
+ platform_msi_domain_free(domain, virq, nr_irqs);
+}
+
+static const struct irq_domain_ops mvebu_icu_domain_ops = {
+ .translate = mvebu_icu_irq_domain_translate,
+ .alloc = mvebu_icu_irq_domain_alloc,
+ .free = mvebu_icu_irq_domain_free,
+};
+
+static int mvebu_icu_probe(struct platform_device *pdev)
+{
+ struct mvebu_icu *icu;
+ struct device_node *node = pdev->dev.of_node;
+ struct device_node *gicp_dn;
+ struct resource *res;
+ phys_addr_t setspi, clrspi;
+ u32 i, icu_int;
+ int ret;
+
+ icu = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_icu),
+ GFP_KERNEL);
+ if (!icu)
+ return -ENOMEM;
+
+ icu->dev = &pdev->dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ icu->base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(icu->base)) {
+ dev_err(&pdev->dev, "Failed to map icu base address.\n");
+ return PTR_ERR(icu->base);
+ }
+
+ icu->irq_chip.name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
+ "ICU.%x",
+ (unsigned int)res->start);
+ if (!icu->irq_chip.name)
+ return -ENOMEM;
+
+ icu->irq_chip.irq_mask = irq_chip_mask_parent;
+ icu->irq_chip.irq_unmask = irq_chip_unmask_parent;
+ icu->irq_chip.irq_eoi = irq_chip_eoi_parent;
+ icu->irq_chip.irq_set_type = irq_chip_set_type_parent;
+#ifdef CONFIG_SMP
+ icu->irq_chip.irq_set_affinity = irq_chip_set_affinity_parent;
+#endif
+
+ /*
+ * We're probed after MSI domains have been resolved, so force
+ * resolution here.
+ */
+ pdev->dev.msi_domain = of_msi_get_domain(&pdev->dev, node,
+ DOMAIN_BUS_PLATFORM_MSI);
+ if (!pdev->dev.msi_domain)
+ return -EPROBE_DEFER;
+
+ gicp_dn = of_parse_phandle(node, "msi-parent", 0);
+ if (!gicp_dn) {
+ dev_err(&pdev->dev, "Missing marvell,gicp property.\n");
+ return -ENODEV;
+ }
+
+ ret = mvebu_gicp_get_doorbells(gicp_dn, &setspi, &clrspi);
+ if (ret)
+ return ret;
+
+ /* Set Clear/Set ICU SPI message address in AP */
+ writel_relaxed(upper_32_bits(setspi), icu->base + ICU_SETSPI_NSR_AH);
+ writel_relaxed(lower_32_bits(setspi), icu->base + ICU_SETSPI_NSR_AL);
+ writel_relaxed(upper_32_bits(clrspi), icu->base + ICU_CLRSPI_NSR_AH);
+ writel_relaxed(lower_32_bits(clrspi), icu->base + ICU_CLRSPI_NSR_AL);
+
+ /*
+ * Clean all ICU interrupts with type SPI_NSR, required to
+ * avoid unpredictable SPI assignments done by firmware.
+ */
+ for (i = 0 ; i < ICU_MAX_IRQS ; i++) {
+ icu_int = readl(icu->base + ICU_INT_CFG(i));
+ if ((icu_int >> ICU_GROUP_SHIFT) == ICU_GRP_NSR)
+ writel_relaxed(0x0, icu->base + ICU_INT_CFG(i));
+ }
+
+ icu->domain =
+ platform_msi_create_device_domain(&pdev->dev, ICU_MAX_IRQS,
+ mvebu_icu_write_msg,
+ &mvebu_icu_domain_ops, icu);
+ if (!icu->domain) {
+ dev_err(&pdev->dev, "Failed to create ICU domain\n");
+ return -ENOMEM;
+ }
+
+ return 0;
+}
+
+static const struct of_device_id mvebu_icu_of_match[] = {
+ { .compatible = "marvell,cp110-icu", },
+ {},
+};
+
+static struct platform_driver mvebu_icu_driver = {
+ .probe = mvebu_icu_probe,
+ .driver = {
+ .name = "mvebu-icu",
+ .of_match_table = mvebu_icu_of_match,
+ },
+};
+builtin_platform_driver(mvebu_icu_driver);
diff --git a/include/dt-bindings/interrupt-controller/mvebu-icu.h b/include/dt-bindings/interrupt-controller/mvebu-icu.h
new file mode 100644
index 0000000..8249558
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/mvebu-icu.h
@@ -0,0 +1,15 @@
+/*
+ * This header provides constants for the MVEBU ICU driver.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MVEBU_ICU_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MVEBU_ICU_H
+
+/* interrupt specifier cell 0 */
+
+#define ICU_GRP_NSR 0x0
+#define ICU_GRP_SR 0x1
+#define ICU_GRP_SEI 0x4
+#define ICU_GRP_REI 0x5
+
+#endif
--
2.9.4
Hi Thomas,
On mar., juin 20 2017, Thomas Petazzoni <[email protected]> wrote:
> This commit modifies the Marvell EBU Armada 7K and 8K Device Tree files
> to describe the ICU and GICP units, and use ICU interrupts for all
> devices in the CP110 blocks.
>
> Signed-off-by: Thomas Petazzoni <[email protected]>
I've just tried to apply your patch as the series seems about to be
merged. After the resolution of a few merge conflict it was applied.
But I still have a problem see below:
> ---
> arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 7 +++
> .../boot/dts/marvell/armada-cp110-master.dtsi | 59 +++++++++++++---------
> .../arm64/boot/dts/marvell/armada-cp110-slave.dtsi | 53 ++++++++++---------
> 3 files changed, 71 insertions(+), 48 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
> index fe41bf9..e0a9198 100644
> --- a/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-ap806.dtsi
> @@ -146,6 +146,13 @@
> marvell,spi-base = <128>, <136>, <144>, <152>;
> };
>
> + gicp: gicp@3f0040 {
> + compatible = "marvell,ap806-gicp";
> + reg = <0x3f0040 0x10>;
> + marvell,spi-ranges = <64 64>, <288 64>;
> + msi-controller;
> + };
> +
> pic: interrupt-controller@3f0100 {
> compatible = "marvell,armada-8k-pic";
> reg = <0x3f0100 0x10>;
> diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
> index ac8df52..50586de 100644
> --- a/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
> @@ -44,19 +44,20 @@
> * Device Tree file for Marvell Armada CP110 Master.
> */
>
> +#include <dt-bindings/interrupt-controller/mvebu-icu.h>
With this line you created a dependency with the patch "irqchip:
irq-mvebu-icu: new driver for Marvell ICU". And without it the dtb is
not buidable.
So either I wait for the next kernel release to apply it or I will need
a stable branch with the commit adding the mvebu-icu.h file.
Gregory
> +
> / {
> cp110-master {
> #address-cells = <2>;
> #size-cells = <2>;
> compatible = "simple-bus";
> - interrupt-parent = <&gic>;
> + interrupt-parent = <&cpm_icu>;
> ranges;
>
> config-space@f2000000 {
> #address-cells = <1>;
> #size-cells = <1>;
> compatible = "simple-bus";
> - interrupt-parent = <&gic>;
> ranges = <0x0 0x0 0xf2000000 0x2000000>;
>
> cpm_ethernet: ethernet@0 {
> @@ -68,21 +69,21 @@
> dma-coherent;
>
> cpm_eth0: eth0 {
> - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>;
> port-id = <0>;
> gop-port-id = <0>;
> status = "disabled";
> };
>
> cpm_eth1: eth1 {
> - interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>;
> port-id = <1>;
> gop-port-id = <2>;
> status = "disabled";
> };
>
> cpm_eth2: eth2 {
> - interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>;
> port-id = <2>;
> gop-port-id = <3>;
> status = "disabled";
> @@ -96,6 +97,14 @@
> reg = <0x12a200 0x10>;
> };
>
> + cpm_icu: interrupt-controller@1e0000 {
> + compatible = "marvell,cp110-icu";
> + reg = <0x1e0000 0x10>;
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + msi-parent = <&gicp>;
> + };
> +
> cpm_syscon0: system-controller@440000 {
> compatible = "marvell,cp110-system-controller0",
> "syscon";
> @@ -120,14 +129,14 @@
> compatible = "marvell,armada-8k-rtc";
> reg = <0x284000 0x20>, <0x284080 0x24>;
> reg-names = "rtc", "rtc-soc";
> - interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 77 IRQ_TYPE_LEVEL_HIGH>;
> };
>
> cpm_sata0: sata@540000 {
> compatible = "marvell,armada-8k-ahci",
> "generic-ahci";
> reg = <0x540000 0x30000>;
> - interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cpm_syscon0 1 15>;
> status = "disabled";
> };
> @@ -137,7 +146,7 @@
> "generic-xhci";
> reg = <0x500000 0x4000>;
> dma-coherent;
> - interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cpm_syscon0 1 22>;
> status = "disabled";
> };
> @@ -147,7 +156,7 @@
> "generic-xhci";
> reg = <0x510000 0x4000>;
> dma-coherent;
> - interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cpm_syscon0 1 23>;
> status = "disabled";
> };
> @@ -195,7 +204,7 @@
> reg = <0x701000 0x20>;
> #address-cells = <1>;
> #size-cells = <0>;
> - interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cpm_syscon0 1 21>;
> status = "disabled";
> };
> @@ -205,7 +214,7 @@
> reg = <0x701100 0x20>;
> #address-cells = <1>;
> #size-cells = <0>;
> - interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cpm_syscon0 1 21>;
> status = "disabled";
> };
> @@ -213,7 +222,7 @@
> cpm_trng: trng@760000 {
> compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
> reg = <0x760000 0x7d>;
> - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cpm_syscon0 1 25>;
> status = "okay";
> };
> @@ -221,7 +230,7 @@
> cpm_sdhci0: sdhci@780000 {
> compatible = "marvell,armada-cp110-sdhci";
> reg = <0x780000 0x300>;
> - interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
> clock-names = "core";
> clocks = <&cpm_syscon0 1 4>;
> dma-coherent;
> @@ -231,13 +240,13 @@
> cpm_crypto: crypto@800000 {
> compatible = "inside-secure,safexcel-eip197";
> reg = <0x800000 0x200000>;
> - interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
> + interrupts = <ICU_GRP_NSR 87 (IRQ_TYPE_EDGE_RISING
> | IRQ_TYPE_LEVEL_HIGH)>,
> - <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
> + <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
> + <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
> + <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
> + <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
> + <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "mem", "ring0", "ring1",
> "ring2", "ring3", "eip";
> clocks = <&cpm_syscon0 1 26>;
> @@ -264,8 +273,8 @@
> /* non-prefetchable memory */
> 0x82000000 0 0xf6000000 0 0xf6000000 0 0xf00000>;
> interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
> num-lanes = <1>;
> clocks = <&cpm_syscon0 1 13>;
> status = "disabled";
> @@ -290,8 +299,8 @@
> /* non-prefetchable memory */
> 0x82000000 0 0xf7000000 0 0xf7000000 0 0xf00000>;
> interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
>
> num-lanes = <1>;
> clocks = <&cpm_syscon0 1 11>;
> @@ -317,8 +326,8 @@
> /* non-prefetchable memory */
> 0x82000000 0 0xf8000000 0 0xf8000000 0 0xf00000>;
> interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> - interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-map = <0 0 0 0 &cpm_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
>
> num-lanes = <1>;
> clocks = <&cpm_syscon0 1 12>;
> diff --git a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
> index 7740a75..3def18f 100644
> --- a/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
> +++ b/arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
> @@ -49,14 +49,13 @@
> #address-cells = <2>;
> #size-cells = <2>;
> compatible = "simple-bus";
> - interrupt-parent = <&gic>;
> + interrupt-parent = <&cps_icu>;
> ranges;
>
> config-space@f4000000 {
> #address-cells = <1>;
> #size-cells = <1>;
> compatible = "simple-bus";
> - interrupt-parent = <&gic>;
> ranges = <0x0 0x0 0xf4000000 0x2000000>;
>
> cps_rtc: rtc@284000 {
> @@ -75,21 +74,21 @@
> dma-coherent;
>
> cps_eth0: eth0 {
> - interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 39 IRQ_TYPE_LEVEL_HIGH>;
> port-id = <0>;
> gop-port-id = <0>;
> status = "disabled";
> };
>
> cps_eth1: eth1 {
> - interrupts = <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 40 IRQ_TYPE_LEVEL_HIGH>;
> port-id = <1>;
> gop-port-id = <2>;
> status = "disabled";
> };
>
> cps_eth2: eth2 {
> - interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 41 IRQ_TYPE_LEVEL_HIGH>;
> port-id = <2>;
> gop-port-id = <3>;
> status = "disabled";
> @@ -103,6 +102,14 @@
> reg = <0x12a200 0x10>;
> };
>
> + cps_icu: interrupt-controller@1e0000 {
> + compatible = "marvell,cp110-icu";
> + reg = <0x1e0000 0x10>;
> + #interrupt-cells = <3>;
> + interrupt-controller;
> + msi-parent = <&gicp>;
> + };
> +
> cps_syscon0: system-controller@440000 {
> compatible = "marvell,cp110-system-controller0",
> "syscon";
> @@ -127,7 +134,7 @@
> compatible = "marvell,armada-8k-ahci",
> "generic-ahci";
> reg = <0x540000 0x30000>;
> - interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 107 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cps_syscon0 1 15>;
> status = "disabled";
> };
> @@ -137,7 +144,7 @@
> "generic-xhci";
> reg = <0x500000 0x4000>;
> dma-coherent;
> - interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 106 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cps_syscon0 1 22>;
> status = "disabled";
> };
> @@ -147,7 +154,7 @@
> "generic-xhci";
> reg = <0x510000 0x4000>;
> dma-coherent;
> - interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 105 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cps_syscon0 1 23>;
> status = "disabled";
> };
> @@ -195,7 +202,7 @@
> reg = <0x701000 0x20>;
> #address-cells = <1>;
> #size-cells = <0>;
> - interrupts = <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 120 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cps_syscon0 1 21>;
> status = "disabled";
> };
> @@ -205,7 +212,7 @@
> reg = <0x701100 0x20>;
> #address-cells = <1>;
> #size-cells = <0>;
> - interrupts = <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 121 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cps_syscon0 1 21>;
> status = "disabled";
> };
> @@ -213,7 +220,7 @@
> cps_trng: trng@760000 {
> compatible = "marvell,armada-8k-rng", "inside-secure,safexcel-eip76";
> reg = <0x760000 0x7d>;
> - interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 95 IRQ_TYPE_LEVEL_HIGH>;
> clocks = <&cps_syscon0 1 25>;
> status = "okay";
> };
> @@ -221,13 +228,13 @@
> cps_crypto: crypto@800000 {
> compatible = "inside-secure,safexcel-eip197";
> reg = <0x800000 0x200000>;
> - interrupts = <GIC_SPI 34 (IRQ_TYPE_EDGE_RISING
> + interrupts = <ICU_GRP_NSR 87 (IRQ_TYPE_EDGE_RISING
> | IRQ_TYPE_LEVEL_HIGH)>,
> - <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>,
> - <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>;
> + <ICU_GRP_NSR 88 IRQ_TYPE_LEVEL_HIGH>,
> + <ICU_GRP_NSR 89 IRQ_TYPE_LEVEL_HIGH>,
> + <ICU_GRP_NSR 90 IRQ_TYPE_LEVEL_HIGH>,
> + <ICU_GRP_NSR 91 IRQ_TYPE_LEVEL_HIGH>,
> + <ICU_GRP_NSR 92 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "mem", "ring0", "ring1",
> "ring2", "ring3", "eip";
> clocks = <&cps_syscon0 1 26>;
> @@ -254,8 +261,8 @@
> /* non-prefetchable memory */
> 0x82000000 0 0xfa000000 0 0xfa000000 0 0xf00000>;
> interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
> - interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 22 IRQ_TYPE_LEVEL_HIGH>;
> num-lanes = <1>;
> clocks = <&cps_syscon0 1 13>;
> status = "disabled";
> @@ -280,8 +287,8 @@
> /* non-prefetchable memory */
> 0x82000000 0 0xfb000000 0 0xfb000000 0 0xf00000>;
> interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
> - interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 24 IRQ_TYPE_LEVEL_HIGH>;
>
> num-lanes = <1>;
> clocks = <&cps_syscon0 1 11>;
> @@ -307,8 +314,8 @@
> /* non-prefetchable memory */
> 0x82000000 0 0xfc000000 0 0xfc000000 0 0xf00000>;
> interrupt-map-mask = <0 0 0 0>;
> - interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
> - interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-map = <0 0 0 0 &cps_icu 0 ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
> + interrupts = <ICU_GRP_NSR 23 IRQ_TYPE_LEVEL_HIGH>;
>
> num-lanes = <1>;
> clocks = <&cps_syscon0 1 12>;
> --
> 2.9.4
>
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Hello,
On Tue, 20 Jun 2017 16:56:35 +0200, Gregory CLEMENT wrote:
> > +#include <dt-bindings/interrupt-controller/mvebu-icu.h>
>
> With this line you created a dependency with the patch "irqchip:
> irq-mvebu-icu: new driver for Marvell ICU". And without it the dtb is
> not buidable.
>
> So either I wait for the next kernel release to apply it or I will need
> a stable branch with the commit adding the mvebu-icu.h file.
Alternatively, I could change the patch to use hardcoded values for now
(i.e replace ICU_GRP_NSR everywhere by 0x0), and then change it during
the next kernel cycle to use the #define value. I would really prefer
such a solution to a solution where merging the entire ICU DT change
would be delayed by one cycle.
Let me know what you prefer. Maybe Marc can say if the irqchip
maintainers can provide a stable branch containing the mvebu-icu.h file.
Best regards,
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
Hi Thomas,
On mar., juin 20 2017, Thomas Petazzoni <[email protected]> wrote:
> Hello,
>
> On Tue, 20 Jun 2017 16:56:35 +0200, Gregory CLEMENT wrote:
>
>> > +#include <dt-bindings/interrupt-controller/mvebu-icu.h>
>>
>> With this line you created a dependency with the patch "irqchip:
>> irq-mvebu-icu: new driver for Marvell ICU". And without it the dtb is
>> not buidable.
>>
>> So either I wait for the next kernel release to apply it or I will need
>> a stable branch with the commit adding the mvebu-icu.h file.
>
> Alternatively, I could change the patch to use hardcoded values for now
> (i.e replace ICU_GRP_NSR everywhere by 0x0), and then change it during
> the next kernel cycle to use the #define value. I would really prefer
> such a solution to a solution where merging the entire ICU DT change
> would be delayed by one cycle.
As we start to be short in time then not having an external dependency
is easier so use the hardcoded value in your v5 series, and we will
switch to #define value in the next cycle.
Thanks,
Gregory
>
> Let me know what you prefer. Maybe Marc can say if the irqchip
> maintainers can provide a stable branch containing the mvebu-icu.h file.
>
> Best regards,
>
> Thomas
> --
> Thomas Petazzoni, CTO, Free Electrons
> Embedded Linux and Kernel engineering
> http://free-electrons.com
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
Hi Thomas,
On 20/06/17 15:07, Thomas Petazzoni wrote:
> The Marvell ICU unit is found in the CP110 block of the Marvell Armada
> 7K and 8K SoCs. It collects the wired interrupts of the devices located
> in the CP110 and turns them into SPI interrupts in the GIC located in
> the AP806 side of the SoC, by using a memory transaction.
>
> Until now, the ICU was configured in a static fashion by the firmware,
> and Linux was relying on this static configuration. By having Linux
> configure the ICU, we are more flexible, and we can allocate dynamically
> the GIC SPI interrupts only for devices that are actually in use.
>
> The driver was initially written by Hanna Hawa <[email protected]>.
>
> Signed-off-by: Thomas Petazzoni <[email protected]>
> ---
> drivers/irqchip/Kconfig | 3 +
> drivers/irqchip/Makefile | 1 +
> drivers/irqchip/irq-mvebu-icu.c | 291 +++++++++++++++++++++
> .../dt-bindings/interrupt-controller/mvebu-icu.h | 15 ++
> 4 files changed, 310 insertions(+)
> create mode 100644 drivers/irqchip/irq-mvebu-icu.c
> create mode 100644 include/dt-bindings/interrupt-controller/mvebu-icu.h
>
> diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
> index e527ee5..676232a 100644
> --- a/drivers/irqchip/Kconfig
> +++ b/drivers/irqchip/Kconfig
> @@ -271,6 +271,9 @@ config IRQ_MXS
> config MVEBU_GICP
> bool
>
> +config MVEBU_ICU
> + bool
> +
> config MVEBU_ODMI
> bool
> select GENERIC_MSI_IRQ_DOMAIN
> diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
> index 11eb858..18fa5fa 100644
> --- a/drivers/irqchip/Makefile
> +++ b/drivers/irqchip/Makefile
> @@ -70,6 +70,7 @@ obj-$(CONFIG_INGENIC_IRQ) += irq-ingenic.o
> obj-$(CONFIG_IMX_GPCV2) += irq-imx-gpcv2.o
> obj-$(CONFIG_PIC32_EVIC) += irq-pic32-evic.o
> obj-$(CONFIG_MVEBU_GICP) += irq-mvebu-gicp.o
> +obj-$(CONFIG_MVEBU_ICU) += irq-mvebu-icu.o
> obj-$(CONFIG_MVEBU_ODMI) += irq-mvebu-odmi.o
> obj-$(CONFIG_MVEBU_PIC) += irq-mvebu-pic.o
> obj-$(CONFIG_LS_SCFG_MSI) += irq-ls-scfg-msi.o
> diff --git a/drivers/irqchip/irq-mvebu-icu.c b/drivers/irqchip/irq-mvebu-icu.c
> new file mode 100644
> index 0000000..efc80ee
> --- /dev/null
> +++ b/drivers/irqchip/irq-mvebu-icu.c
> @@ -0,0 +1,291 @@
> +/*
> + * Copyright (C) 2017 Marvell
> + *
> + * Hanna Hawa <[email protected]>
> + * Thomas Petazzoni <[email protected]>
> + *
> + * This file is licensed under the terms of the GNU General Public
> + * License version 2. This program is licensed "as is" without any
> + * warranty of any kind, whether express or implied.
> + */
> +
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/irqchip.h>
> +#include <linux/irqdomain.h>
> +#include <linux/kernel.h>
> +#include <linux/msi.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_platform.h>
> +#include <linux/platform_device.h>
> +
> +#include <dt-bindings/interrupt-controller/mvebu-icu.h>
> +
> +#include "irq-mvebu-gicp.h"
> +
> +/* ICU registers */
> +#define ICU_SETSPI_NSR_AL 0x10
> +#define ICU_SETSPI_NSR_AH 0x14
> +#define ICU_CLRSPI_NSR_AL 0x18
> +#define ICU_CLRSPI_NSR_AH 0x1c
> +#define ICU_INT_CFG(x) (0x100 + 4 * (x))
> +#define ICU_INT_ENABLE BIT(24)
> +#define ICU_IS_EDGE BIT(28)
> +#define ICU_GROUP_SHIFT 29
> +
> +/* ICU definitions */
> +#define ICU_MAX_IRQS 207
> +#define ICU_SATA0_ICU_ID 109
> +#define ICU_SATA1_ICU_ID 107
> +
> +struct mvebu_icu {
> + struct irq_chip irq_chip;
> + void __iomem *base;
> + struct irq_domain *domain;
> + struct device *dev;
> +};
> +
> +struct mvebu_icu_irq_data {
> + struct mvebu_icu *icu;
> + unsigned int icu_group;
> + unsigned int type;
> +};
> +
> +static void mvebu_icu_write_msg(struct msi_desc *desc, struct msi_msg *msg)
> +{
> + struct irq_data *d = irq_get_irq_data(desc->irq);
> + struct mvebu_icu_irq_data *icu_irqd = d->chip_data;
> + struct mvebu_icu *icu = icu_irqd->icu;
> + unsigned int icu_int;
> +
> + if (msg->address_lo) {
As mention in the previous thread, this needs to check address_hi as well.
> + /* Configure the ICU with irq number & type */
> + icu_int = msg->data | ICU_INT_ENABLE;
> + if (icu_irqd->type & IRQ_TYPE_EDGE_RISING)
> + icu_int |= ICU_IS_EDGE;
> + icu_int |= icu_irqd->icu_group << ICU_GROUP_SHIFT;
> + } else {
> + /* De-configure the ICU */
> + icu_int = 0;
> + }
> +
> + writel_relaxed(icu_int, icu->base + ICU_INT_CFG(d->hwirq));
> +
> + /*
> + * The SATA unit has 2 ports, and a dedicated ICU entry per
> + * port. The ahci sata driver supports only one irq interrupt
> + * per SATA unit. To solve this conflict, we configure the 2
> + * SATA wired interrupts in the south bridge into 1 GIC
> + * interrupt in the north bridge. Even if only a single port
> + * is enabled, if sata node is enabled, both interrupts are
> + * configured (regardless of which port is actually in use).
> + */
> + if (d->hwirq == ICU_SATA0_ICU_ID || d->hwirq == ICU_SATA1_ICU_ID) {
> + writel_relaxed(icu_int,
> + icu->base + ICU_INT_CFG(ICU_SATA0_ICU_ID));
> + writel_relaxed(icu_int,
> + icu->base + ICU_INT_CFG(ICU_SATA1_ICU_ID));
> + }
> +}
> +
> +static int
> +mvebu_icu_irq_domain_translate(struct irq_domain *d, struct irq_fwspec *fwspec,
> + unsigned long *hwirq, unsigned int *type)
> +{
> + struct mvebu_icu *icu = d->host_data;
> + unsigned int icu_group;
> +
> + /* Check the count of the parameters in dt */
> + if (WARN_ON(fwspec->param_count < 3)) {
> + dev_err(icu->dev, "wrong ICU parameter count %d\n",
> + fwspec->param_count);
> + return -EINVAL;
> + }
> +
> + /* Only ICU group type is handled */
> + icu_group = fwspec->param[0];
> + if (icu_group != ICU_GRP_NSR && icu_group != ICU_GRP_SR &&
> + icu_group != ICU_GRP_SEI && icu_group != ICU_GRP_REI) {
> + dev_err(icu->dev, "wrong ICU group type %x\n", icu_group);
> + return -EINVAL;
> + }
> +
> + *hwirq = fwspec->param[1];
> + if (*hwirq >= ICU_MAX_IRQS) {
> + dev_err(icu->dev, "invalid interrupt number %ld\n", *hwirq);
> + return -EINVAL;
> + }
> +
> + /* Mask the type to prevent wrong DT configuration */
> + *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;
> +
> + return 0;
> +}
> +
> +static int
> +mvebu_icu_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
> + unsigned int nr_irqs, void *args)
> +{
> + int err;
> + unsigned long hwirq;
> + struct irq_fwspec *fwspec = args;
> + struct mvebu_icu *icu = platform_msi_get_host_data(domain);
> + struct mvebu_icu_irq_data *icu_irqd;
> +
> + icu_irqd = kmalloc(sizeof(*icu_irqd), GFP_KERNEL);
> + if (!icu_irqd)
> + return -ENOMEM;
> +
> + err = mvebu_icu_irq_domain_translate(domain, fwspec, &hwirq,
> + &icu_irqd->type);
> + if (err) {
> + dev_err(icu->dev, "failed to translate ICU parameters\n");
> + goto free_irqd;
> + }
> +
> + icu_irqd->icu_group = fwspec->param[0];
> + icu_irqd->icu = icu;
> +
> + err = platform_msi_domain_alloc(domain, virq, nr_irqs);
> + if (err) {
> + dev_err(icu->dev, "failed to allocate ICU interrupt in parent domain\n");
> + goto free_irqd;
> + }
> +
> + /* Make sure there is no interrupt left pending by the firmware */
> + err = irq_set_irqchip_state(virq, IRQCHIP_STATE_PENDING, false);
> + if (err)
> + goto free_msi;
> +
> + err = irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
> + &icu->irq_chip, icu_irqd);
> + if (err) {
> + dev_err(icu->dev, "failed to set the data to IRQ domain\n");
> + goto free_msi;
> + }
> +
> + return 0;
> +
> +free_msi:
> + platform_msi_domain_free(domain, virq, nr_irqs);
> +free_irqd:
> + kfree(icu_irqd);
> + return err;
> +}
> +
> +static void
> +mvebu_icu_irq_domain_free(struct irq_domain *domain, unsigned int virq,
> + unsigned int nr_irqs)
> +{
> + struct irq_data *d = irq_get_irq_data(virq);
> + struct mvebu_icu_irq_data *icu_irqd = d->chip_data;
> +
> + kfree(icu_irqd);
> +
> + platform_msi_domain_free(domain, virq, nr_irqs);
> +}
> +
> +static const struct irq_domain_ops mvebu_icu_domain_ops = {
> + .translate = mvebu_icu_irq_domain_translate,
> + .alloc = mvebu_icu_irq_domain_alloc,
> + .free = mvebu_icu_irq_domain_free,
> +};
> +
> +static int mvebu_icu_probe(struct platform_device *pdev)
> +{
> + struct mvebu_icu *icu;
> + struct device_node *node = pdev->dev.of_node;
> + struct device_node *gicp_dn;
> + struct resource *res;
> + phys_addr_t setspi, clrspi;
> + u32 i, icu_int;
> + int ret;
> +
> + icu = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_icu),
> + GFP_KERNEL);
> + if (!icu)
> + return -ENOMEM;
> +
> + icu->dev = &pdev->dev;
> +
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> + icu->base = devm_ioremap_resource(&pdev->dev, res);
> + if (IS_ERR(icu->base)) {
> + dev_err(&pdev->dev, "Failed to map icu base address.\n");
> + return PTR_ERR(icu->base);
> + }
> +
> + icu->irq_chip.name = devm_kasprintf(&pdev->dev, GFP_KERNEL,
> + "ICU.%x",
> + (unsigned int)res->start);
> + if (!icu->irq_chip.name)
> + return -ENOMEM;
> +
> + icu->irq_chip.irq_mask = irq_chip_mask_parent;
> + icu->irq_chip.irq_unmask = irq_chip_unmask_parent;
> + icu->irq_chip.irq_eoi = irq_chip_eoi_parent;
> + icu->irq_chip.irq_set_type = irq_chip_set_type_parent;
> +#ifdef CONFIG_SMP
> + icu->irq_chip.irq_set_affinity = irq_chip_set_affinity_parent;
> +#endif
> +
> + /*
> + * We're probed after MSI domains have been resolved, so force
> + * resolution here.
> + */
> + pdev->dev.msi_domain = of_msi_get_domain(&pdev->dev, node,
> + DOMAIN_BUS_PLATFORM_MSI);
> + if (!pdev->dev.msi_domain)
> + return -EPROBE_DEFER;
> +
> + gicp_dn = of_parse_phandle(node, "msi-parent", 0);
> + if (!gicp_dn) {
> + dev_err(&pdev->dev, "Missing marvell,gicp property.\n");
The property name doesn't match here. But overall, there is little point
in reparsing the msi-parent, since that's what of_msi_get_domain does.
Instead, consider using:
gicp_dn = irq_domain_get_of_node(pdev->dev.msi_domain);
which will do the right thing.
> + return -ENODEV;
> + }
> +
> + ret = mvebu_gicp_get_doorbells(gicp_dn, &setspi, &clrspi);
> + if (ret)
> + return ret;
> +
> + /* Set Clear/Set ICU SPI message address in AP */
> + writel_relaxed(upper_32_bits(setspi), icu->base + ICU_SETSPI_NSR_AH);
> + writel_relaxed(lower_32_bits(setspi), icu->base + ICU_SETSPI_NSR_AL);
> + writel_relaxed(upper_32_bits(clrspi), icu->base + ICU_CLRSPI_NSR_AH);
> + writel_relaxed(lower_32_bits(clrspi), icu->base + ICU_CLRSPI_NSR_AL);
> +
> + /*
> + * Clean all ICU interrupts with type SPI_NSR, required to
> + * avoid unpredictable SPI assignments done by firmware.
> + */
> + for (i = 0 ; i < ICU_MAX_IRQS ; i++) {
> + icu_int = readl(icu->base + ICU_INT_CFG(i));
> + if ((icu_int >> ICU_GROUP_SHIFT) == ICU_GRP_NSR)
> + writel_relaxed(0x0, icu->base + ICU_INT_CFG(i));
> + }
> +
> + icu->domain =
> + platform_msi_create_device_domain(&pdev->dev, ICU_MAX_IRQS,
> + mvebu_icu_write_msg,
> + &mvebu_icu_domain_ops, icu);
> + if (!icu->domain) {
> + dev_err(&pdev->dev, "Failed to create ICU domain\n");
> + return -ENOMEM;
> + }
> +
> + return 0;
> +}
> +
> +static const struct of_device_id mvebu_icu_of_match[] = {
> + { .compatible = "marvell,cp110-icu", },
> + {},
> +};
> +
> +static struct platform_driver mvebu_icu_driver = {
> + .probe = mvebu_icu_probe,
> + .driver = {
> + .name = "mvebu-icu",
> + .of_match_table = mvebu_icu_of_match,
> + },
> +};
> +builtin_platform_driver(mvebu_icu_driver);
> diff --git a/include/dt-bindings/interrupt-controller/mvebu-icu.h b/include/dt-bindings/interrupt-controller/mvebu-icu.h
> new file mode 100644
> index 0000000..8249558
> --- /dev/null
> +++ b/include/dt-bindings/interrupt-controller/mvebu-icu.h
> @@ -0,0 +1,15 @@
> +/*
> + * This header provides constants for the MVEBU ICU driver.
> + */
> +
> +#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_MVEBU_ICU_H
> +#define _DT_BINDINGS_INTERRUPT_CONTROLLER_MVEBU_ICU_H
> +
> +/* interrupt specifier cell 0 */
> +
> +#define ICU_GRP_NSR 0x0
> +#define ICU_GRP_SR 0x1
> +#define ICU_GRP_SEI 0x4
> +#define ICU_GRP_REI 0x5
> +
> +#endif
>
With the two minor changes above, and for patch #3 as well:
Reviewed-by: Marc Zyngier <[email protected]>
I can either perform the changes when applying the patches, or let you
do it so that you can test it first (and solve the issue with the DT
include fine with Gregory).
Thanks,
M.
--
Jazz is not dead. It just smells funny...
On 20/06/17 15:07, Thomas Petazzoni wrote:
> This commit enables the newly introduced Marvell GICP and ICUs driver
> for the 64-bit Marvell EBU platforms.
>
> Signed-off-by: Thomas Petazzoni <[email protected]>
> ---
> arch/arm64/Kconfig.platforms | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
> index 4afcffc..bf3b505 100644
> --- a/arch/arm64/Kconfig.platforms
> +++ b/arch/arm64/Kconfig.platforms
> @@ -106,6 +106,8 @@ config ARCH_MVEBU
> select ARMADA_AP806_SYSCON
> select ARMADA_CP110_SYSCON
> select ARMADA_37XX_CLK
> + select MVEBU_GICP
> + select MVEBU_ICU
> select MVEBU_ODMI
> select MVEBU_PIC
> help
>
Acked-by: Marc Zyngier <[email protected]>
M.
--
Jazz is not dead. It just smells funny...
Hello,
On Wed, 21 Jun 2017 08:56:24 +0100, Marc Zyngier wrote:
> > +static void mvebu_icu_write_msg(struct msi_desc *desc, struct msi_msg *msg)
> > +{
> > + struct irq_data *d = irq_get_irq_data(desc->irq);
> > + struct mvebu_icu_irq_data *icu_irqd = d->chip_data;
> > + struct mvebu_icu *icu = icu_irqd->icu;
> > + unsigned int icu_int;
> > +
> > + if (msg->address_lo) {
>
> As mention in the previous thread, this needs to check address_hi as well.
Fixed in v5.
> > + gicp_dn = of_parse_phandle(node, "msi-parent", 0);
> > + if (!gicp_dn) {
> > + dev_err(&pdev->dev, "Missing marvell,gicp property.\n");
>
> The property name doesn't match here. But overall, there is little point
> in reparsing the msi-parent, since that's what of_msi_get_domain does.
> Instead, consider using:
>
> gicp_dn = irq_domain_get_of_node(pdev->dev.msi_domain);
>
> which will do the right thing.
Fixed in v5.
> With the two minor changes above, and for patch #3 as well:
>
> Reviewed-by: Marc Zyngier <[email protected]>
Thanks! Tags added in v5.
> I can either perform the changes when applying the patches, or let you
> do it so that you can test it first (and solve the issue with the DT
> include fine with Gregory).
I've sent a v5 that fixes the different issues you pointed out, and
also fixes the DT include problem. Tested on HW, it still works as
expected.
Thanks again for the review!
Best regards,
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com