Hi,
This patch series add support for AHCI compatible SATA controller, and it is
compliant with the ahci 1.3 and sata 3.0 specification. This driver is slightly
different than ahci_platform.c (eg. reset control, subsystem setting).
Ryder Lee (2):
ata: mediatek: add support for MediaTek SATA controller
dt-bindings: ata: add DT bindings for MediaTek SATA controller
Documentation/devicetree/bindings/ata/ahci-mtk.txt | 48 +++++
drivers/ata/Kconfig | 10 ++
drivers/ata/Makefile | 1 +
drivers/ata/ahci_mtk.c | 196 +++++++++++++++++++++
4 files changed, 255 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ata/ahci-mtk.txt
create mode 100644 drivers/ata/ahci_mtk.c
--
1.9.1
Add DT bindings for the onboard SATA controller present on the MediaTek
SoCs.
Signed-off-by: Ryder Lee <[email protected]>
---
Documentation/devicetree/bindings/ata/ahci-mtk.txt | 48 ++++++++++++++++++++++
1 file changed, 48 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ata/ahci-mtk.txt
diff --git a/Documentation/devicetree/bindings/ata/ahci-mtk.txt b/Documentation/devicetree/bindings/ata/ahci-mtk.txt
new file mode 100644
index 0000000..a8d11db
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/ahci-mtk.txt
@@ -0,0 +1,48 @@
+MediaTek Seria ATA controller
+
+Required properties:
+ - compatible : Must be "mediatek,ahci".
+ - reg : Physical base addresses and length of register sets.
+ - interrupts : Interrupt associated with the SATA device.
+ - interrupt-names : Associated name must be: "hostc".
+ - clocks : The phandle for the clock.
+ - clock-names : Associated name must be: "ahb", "axi", "asic", "rbc", "pm"
+ - phys : The phandle for the PHY port.
+ - phy-names : Associated name must be: "sata-phy".
+ - ports-implemented : Mask that indicates which ports that the HBA supports
+ are available for software to use. Useful if PORTS_IMPL
+ is not programmed by the BIOS, which is true with some
+ embedded SOC's.
+Optional properties:
+ - power-domains : A phandle and power domain specifier pair to the power
+ domain which is responsible for collapsing and restoring
+ power to the peripheral.
+ - resets : Must contain an entry for each entry in reset-names.
+ See ../reset/reset.txt for details.
+ - reset-names : Associated names must be: "axi-rst", "sw-rst", "reg-rst".
+ - mediatek,phy-mode : A phandle to the system controller, used to enable
+ SATA function.
+
+Example:
+
+ sata: sata@1a200000 {
+ compatible = "mediatek,ahci";
+ reg = <0 0x1a200000 0 0x1100>;
+ interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "hostc";
+ clocks = <&pciesys CLK_SATA_AHB_EN>,
+ <&pciesys CLK_SATA_AXI_EN>,
+ <&pciesys CLK_SATA_ASIC_EN>,
+ <&pciesys CLK_SATA_RBC_EN>,
+ <&pciesys CLK_SATA_PM_EN>;
+ clock-names = "ahb", "axi", "asic", "rbc", "pm";
+ phys = <&u3port1 PHY_TYPE_SATA>;
+ phy-names = "sata-phy";
+ ports-implemented = <0x1>;
+ power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
+ resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
+ <&pciesys MT7622_SATA_PHY_SW_RST>,
+ <&pciesys MT7622_SATA_PHY_REG_RST>;
+ reset-names = "axi-rst", "sw-rst", "reg-rst";
+ mediatek,phy-mode = <&pciesys>;
+ };
--
1.9.1
This adds support the AHCI-compliant Serial ATA controller present
on MediaTek SoCs.
Signed-off-by: Ryder Lee <[email protected]>
---
drivers/ata/Kconfig | 10 +++
drivers/ata/Makefile | 1 +
drivers/ata/ahci_mtk.c | 196 +++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 207 insertions(+)
create mode 100644 drivers/ata/ahci_mtk.c
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 948fc86..7d3eb47 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -153,6 +153,16 @@ config AHCI_CEVA
If unsure, say N.
+config AHCI_MTK
+ tristate "MediaTek AHCI SATA support"
+ depends on ARCH_MEDIATEK
+ select MFD_SYSCON
+ help
+ This option enables support for the MediaTek SoC's
+ onboard AHCI SATA controller.
+
+ If unsure, say N.
+
config AHCI_MVEBU
tristate "Marvell EBU AHCI SATA support"
depends on ARCH_MVEBU
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index a26ef5a..ff9cd2e 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_AHCI_CEVA) += ahci_ceva.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_DA850) += ahci_da850.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_DM816) += ahci_dm816.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_IMX) += ahci_imx.o libahci.o libahci_platform.o
+obj-$(CONFIG_AHCI_MTK) += ahci_mtk.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_OCTEON) += ahci_octeon.o
obj-$(CONFIG_AHCI_SUNXI) += ahci_sunxi.o libahci.o libahci_platform.o
diff --git a/drivers/ata/ahci_mtk.c b/drivers/ata/ahci_mtk.c
new file mode 100644
index 0000000..220dce6
--- /dev/null
+++ b/drivers/ata/ahci_mtk.c
@@ -0,0 +1,196 @@
+/*
+ * MeidaTek AHCI SATA driver
+ *
+ * Copyright (c) 2017 MediaTek Inc.
+ * Author: Ryder Lee <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/ahci_platform.h>
+#include <linux/kernel.h>
+#include <linux/libata.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include "ahci.h"
+
+#define DRV_NAME "ahci"
+
+#define SYS_CFG 0x14
+#define SYS_CFG_SATA_MSK GENMASK(31, 30)
+#define SYS_CFG_SATA_EN BIT(31)
+
+struct mtk_ahci_drv_data {
+ struct regmap *mode;
+ struct reset_control *axi_rst;
+ struct reset_control *sw_rst;
+ struct reset_control *reg_rst;
+};
+
+static const struct ata_port_info ahci_port_info = {
+ .flags = AHCI_FLAG_COMMON,
+ .pio_mask = ATA_PIO4,
+ .udma_mask = ATA_UDMA6,
+ .port_ops = &ahci_platform_ops,
+};
+
+static struct scsi_host_template ahci_platform_sht = {
+ AHCI_SHT(DRV_NAME),
+};
+
+static int mtk_ahci_platform_resets(struct ahci_host_priv *hpriv,
+ struct device *dev)
+{
+ struct mtk_ahci_drv_data *drv_data = hpriv->plat_data;
+ int err;
+
+ /* reset AXI bus and phy part */
+ drv_data->axi_rst = devm_reset_control_get_optional(dev, "axi-rst");
+ if (IS_ERR(drv_data->axi_rst) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+
+ drv_data->sw_rst = devm_reset_control_get_optional(dev, "sw-rst");
+ if (IS_ERR(drv_data->sw_rst) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+
+ drv_data->reg_rst = devm_reset_control_get_optional(dev, "reg-rst");
+ if (IS_ERR(drv_data->reg_rst) == -EPROBE_DEFER)
+ return -EPROBE_DEFER;
+
+ err = reset_control_assert(drv_data->axi_rst);
+ if (err) {
+ dev_err(dev, "assert axi bus failed\n");
+ return err;
+ }
+
+ err = reset_control_assert(drv_data->sw_rst);
+ if (err) {
+ dev_err(dev, "assert phy digital part failed\n");
+ return err;
+ }
+
+ err = reset_control_assert(drv_data->reg_rst);
+ if (err) {
+ dev_err(dev, "assert phy register part failed\n");
+ return err;
+ }
+
+ err = reset_control_deassert(drv_data->reg_rst);
+ if (err) {
+ dev_err(dev, "deassert phy register part failed\n");
+ return err;
+ }
+
+ err = reset_control_deassert(drv_data->sw_rst);
+ if (err) {
+ dev_err(dev, "deassert phy digital part failed\n");
+ return err;
+ }
+
+ err = reset_control_deassert(drv_data->axi_rst);
+ if (err) {
+ dev_err(dev, "deassert axi bus failed\n");
+ return err;
+ }
+
+ return 0;
+}
+
+static int mtk_ahci_parse_property(struct ahci_host_priv *hpriv,
+ struct device *dev)
+{
+ struct mtk_ahci_drv_data *drv_data = hpriv->plat_data;
+ struct device_node *np = dev->of_node;
+
+ /* enable SATA function if needed */
+ if (of_find_property(np, "mediatek,phy-mode", NULL)) {
+ drv_data->mode = syscon_regmap_lookup_by_phandle(
+ np, "mediatek,phy-mode");
+ if (IS_ERR(drv_data->mode)) {
+ dev_err(dev, "missing phy-mode phandle\n");
+ return PTR_ERR(drv_data->mode);
+ }
+
+ regmap_update_bits(drv_data->mode, SYS_CFG, SYS_CFG_SATA_MSK,
+ SYS_CFG_SATA_EN);
+ }
+
+ of_property_read_u32(np, "ports-implemented", &hpriv->force_port_map);
+
+ return 0;
+}
+
+static int mtk_ahci_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_ahci_drv_data *drv_data;
+ struct ahci_host_priv *hpriv;
+ int err;
+
+ drv_data = devm_kzalloc(dev, sizeof(*drv_data), GFP_KERNEL);
+ if (!drv_data)
+ return -ENOMEM;
+
+ hpriv = ahci_platform_get_resources(pdev);
+ if (IS_ERR(hpriv))
+ return PTR_ERR(hpriv);
+
+ hpriv->plat_data = drv_data;
+
+ err = mtk_ahci_parse_property(hpriv, dev);
+ if (err)
+ return err;
+
+ err = mtk_ahci_platform_resets(hpriv, dev);
+ if (err)
+ return err;
+
+ err = ahci_platform_enable_resources(hpriv);
+ if (err)
+ return err;
+
+ err = ahci_platform_init_host(pdev, hpriv, &ahci_port_info,
+ &ahci_platform_sht);
+ if (err)
+ goto disable_resources;
+
+ return 0;
+
+disable_resources:
+ ahci_platform_disable_resources(hpriv);
+ return err;
+}
+
+static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend,
+ ahci_platform_resume);
+
+static const struct of_device_id ahci_of_match[] = {
+ { .compatible = "mediatek,ahci", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ahci_of_match);
+
+static struct platform_driver mtk_ahci_driver = {
+ .probe = mtk_ahci_probe,
+ .remove = ata_platform_remove_one,
+ .driver = {
+ .name = DRV_NAME,
+ .of_match_table = ahci_of_match,
+ .pm = &ahci_pm_ops,
+ },
+};
+module_platform_driver(mtk_ahci_driver);
+
+MODULE_DESCRIPTION("MeidaTek SATA AHCI Driver");
+MODULE_LICENSE("GPL v2");
--
1.9.1
Hello!
On 7/27/2017 9:38 AM, Ryder Lee wrote:
> Add DT bindings for the onboard SATA controller present on the MediaTek
> SoCs.
>
> Signed-off-by: Ryder Lee <[email protected]>
> ---
> Documentation/devicetree/bindings/ata/ahci-mtk.txt | 48 ++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/ata/ahci-mtk.txt
>
> diff --git a/Documentation/devicetree/bindings/ata/ahci-mtk.txt b/Documentation/devicetree/bindings/ata/ahci-mtk.txt
> new file mode 100644
> index 0000000..a8d11db
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ata/ahci-mtk.txt
> @@ -0,0 +1,48 @@
> +MediaTek Seria ATA controller
> +
> +Required properties:
> + - compatible : Must be "mediatek,ahci".
> + - reg : Physical base addresses and length of register sets.
> + - interrupts : Interrupt associated with the SATA device.
> + - interrupt-names : Associated name must be: "hostc".
> + - clocks : The phandle for the clock.
Your example shows that you need both phandle and specifier (afetr phandle).
> + - clock-names : Associated name must be: "ahb", "axi", "asic", "rbc", "pm"
> + - phys : The phandle for the PHY port.
Likewise.
> + - phy-names : Associated name must be: "sata-phy".
> + - ports-implemented : Mask that indicates which ports that the HBA supports
> + are available for software to use. Useful if PORTS_IMPL
> + is not programmed by the BIOS, which is true with some
> + embedded SOC's.
An empty line wouldn't hurt here...
> +Optional properties:
> + - power-domains : A phandle and power domain specifier pair to the power
> + domain which is responsible for collapsing and restoring
> + power to the peripheral.
> + - resets : Must contain an entry for each entry in reset-names.
> + See ../reset/reset.txt for details.
> + - reset-names : Associated names must be: "axi-rst", "sw-rst", "reg-rst".
> + - mediatek,phy-mode : A phandle to the system controller, used to enable
> + SATA function.
> +
> +Example:
> +
> + sata: sata@1a200000 {
> + compatible = "mediatek,ahci";
> + reg = <0 0x1a200000 0 0x1100>;
> + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "hostc";
> + clocks = <&pciesys CLK_SATA_AHB_EN>,
> + <&pciesys CLK_SATA_AXI_EN>,
> + <&pciesys CLK_SATA_ASIC_EN>,
> + <&pciesys CLK_SATA_RBC_EN>,
> + <&pciesys CLK_SATA_PM_EN>;
> + clock-names = "ahb", "axi", "asic", "rbc", "pm";
> + phys = <&u3port1 PHY_TYPE_SATA>;
> + phy-names = "sata-phy";
> + ports-implemented = <0x1>;
> + power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
> + resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
> + <&pciesys MT7622_SATA_PHY_SW_RST>,
> + <&pciesys MT7622_SATA_PHY_REG_RST>;
> + reset-names = "axi-rst", "sw-rst", "reg-rst";
> + mediatek,phy-mode = <&pciesys>;
> + };
MBR, Sergei
On Fri, 2017-07-28 at 12:20 +0300, Sergei Shtylyov wrote:
> > +Required properties:
> > + - compatible : Must be "mediatek,ahci".
> > + - reg : Physical base addresses and length of register sets.
> > + - interrupts : Interrupt associated with the SATA device.
> > + - interrupt-names : Associated name must be: "hostc".
> > + - clocks : The phandle for the clock.
>
> Your example shows that you need both phandle and specifier (afetr phandle).
>
> > + - clock-names : Associated name must be: "ahb", "axi", "asic", "rbc", "pm"
> > + - phys : The phandle for the PHY port.
>
> Likewise.
Oh yeah, I forgot about that.
> > + - phy-names : Associated name must be: "sata-phy".
> > + - ports-implemented : Mask that indicates which ports that the HBA supports
> > + are available for software to use. Useful if PORTS_IMPL
> > + is not programmed by the BIOS, which is true with some
> > + embedded SOC's.
>
> An empty line wouldn't hurt here...
Okay.
> > +Optional properties:
> > + - power-domains : A phandle and power domain specifier pair to the power
> > + domain which is responsible for collapsing and restoring
> > + power to the peripheral.
> > + - resets : Must contain an entry for each entry in reset-names.
> > + See ../reset/reset.txt for details.
> > + - reset-names : Associated names must be: "axi-rst", "sw-rst", "reg-rst".
> > + - mediatek,phy-mode : A phandle to the system controller, used to enable
> > + SATA function.
Thanks!
Ryder.
Hi Ryder,
[auto build test WARNING on tj-libata/for-next]
[also build test WARNING on v4.13-rc2 next-20170728]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Ryder-Lee/Add-support-for-MediaTek-AHCI-SATA/20170728-164513
base: https://git.kernel.org/pub/scm/linux/kernel/git/tj/libata.git for-next
config: arm64-allyesconfig (attached as .config)
compiler: aarch64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
make.cross ARCH=arm64
All warnings (new ones prefixed by >>):
drivers/ata/ahci_mtk.c: In function 'mtk_ahci_platform_resets':
>> drivers/ata/ahci_mtk.c:60:32: warning: comparison of constant '-517' with boolean expression is always false [-Wbool-compare]
if (IS_ERR(drv_data->axi_rst) == -EPROBE_DEFER)
^~
drivers/ata/ahci_mtk.c:64:31: warning: comparison of constant '-517' with boolean expression is always false [-Wbool-compare]
if (IS_ERR(drv_data->sw_rst) == -EPROBE_DEFER)
^~
drivers/ata/ahci_mtk.c:68:32: warning: comparison of constant '-517' with boolean expression is always false [-Wbool-compare]
if (IS_ERR(drv_data->reg_rst) == -EPROBE_DEFER)
^~
>> drivers/ata/ahci_mtk.c:60:6: warning: ignoring return value of 'IS_ERR', declared with attribute warn_unused_result [-Wunused-result]
if (IS_ERR(drv_data->axi_rst) == -EPROBE_DEFER)
^~~~~~~~~~~~~~~~~~~~~~~~~
drivers/ata/ahci_mtk.c:64:6: warning: ignoring return value of 'IS_ERR', declared with attribute warn_unused_result [-Wunused-result]
if (IS_ERR(drv_data->sw_rst) == -EPROBE_DEFER)
^~~~~~~~~~~~~~~~~~~~~~~~
drivers/ata/ahci_mtk.c:68:6: warning: ignoring return value of 'IS_ERR', declared with attribute warn_unused_result [-Wunused-result]
if (IS_ERR(drv_data->reg_rst) == -EPROBE_DEFER)
^~~~~~~~~~~~~~~~~~~~~~~~~
vim +60 drivers/ata/ahci_mtk.c
51
52 static int mtk_ahci_platform_resets(struct ahci_host_priv *hpriv,
53 struct device *dev)
54 {
55 struct mtk_ahci_drv_data *drv_data = hpriv->plat_data;
56 int err;
57
58 /* reset AXI bus and phy part */
59 drv_data->axi_rst = devm_reset_control_get_optional(dev, "axi-rst");
> 60 if (IS_ERR(drv_data->axi_rst) == -EPROBE_DEFER)
61 return -EPROBE_DEFER;
62
63 drv_data->sw_rst = devm_reset_control_get_optional(dev, "sw-rst");
64 if (IS_ERR(drv_data->sw_rst) == -EPROBE_DEFER)
65 return -EPROBE_DEFER;
66
67 drv_data->reg_rst = devm_reset_control_get_optional(dev, "reg-rst");
68 if (IS_ERR(drv_data->reg_rst) == -EPROBE_DEFER)
69 return -EPROBE_DEFER;
70
71 err = reset_control_assert(drv_data->axi_rst);
72 if (err) {
73 dev_err(dev, "assert axi bus failed\n");
74 return err;
75 }
76
77 err = reset_control_assert(drv_data->sw_rst);
78 if (err) {
79 dev_err(dev, "assert phy digital part failed\n");
80 return err;
81 }
82
83 err = reset_control_assert(drv_data->reg_rst);
84 if (err) {
85 dev_err(dev, "assert phy register part failed\n");
86 return err;
87 }
88
89 err = reset_control_deassert(drv_data->reg_rst);
90 if (err) {
91 dev_err(dev, "deassert phy register part failed\n");
92 return err;
93 }
94
95 err = reset_control_deassert(drv_data->sw_rst);
96 if (err) {
97 dev_err(dev, "deassert phy digital part failed\n");
98 return err;
99 }
100
101 err = reset_control_deassert(drv_data->axi_rst);
102 if (err) {
103 dev_err(dev, "deassert axi bus failed\n");
104 return err;
105 }
106
107 return 0;
108 }
109
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