Add clock for audio subsystem (AIO) and SoC internal audio codec
(EVEA) on UniPhier LD11/LD20 SoCs.
Signed-off-by: Katsuhiro Suzuki <[email protected]>
---
drivers/clk/uniphier/clk-uniphier-sys.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index ad0218182a9f..7c4528d0fb6e 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -57,6 +57,14 @@
#define UNIPHIER_PRO4_SYS_CLK_USB3(idx, ch) \
UNIPHIER_CLK_GATE("usb3" #ch, (idx), NULL, 0x2104, 16 + (ch))
+#define UNIPHIER_LD11_SYS_CLK_AIO(idx) \
+ UNIPHIER_CLK_FACTOR("aio-io200m", -1, "spll", 1, 10), \
+ UNIPHIER_CLK_GATE("aio", (idx), "aio-io200m", 0x2108, 0)
+
+#define UNIPHIER_LD11_SYS_CLK_EVEA(idx) \
+ UNIPHIER_CLK_FACTOR("evea-io100m", -1, "spll", 1, 20), \
+ UNIPHIER_CLK_GATE("evea", (idx), "evea-io100m", 0x2108, 1)
+
const struct uniphier_clk_data uniphier_sld3_sys_clk_data[] = {
UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
@@ -158,6 +166,8 @@ const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {
/* Index 5 reserved for eMMC PHY */
UNIPHIER_LD11_SYS_CLK_STDMAC(8), /* HSC, MIO */
UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),
+ UNIPHIER_LD11_SYS_CLK_AIO(40),
+ UNIPHIER_LD11_SYS_CLK_EVEA(41),
/* CPU gears */
UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8),
@@ -194,6 +204,8 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
UNIPHIER_CLK_GATE("usb30", 14, NULL, 0x210c, 14),
UNIPHIER_CLK_GATE("usb30-phy0", 16, NULL, 0x210c, 12),
UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13),
+ UNIPHIER_LD11_SYS_CLK_AIO(40),
+ UNIPHIER_LD11_SYS_CLK_EVEA(41),
/* CPU gears */
UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
--
2.13.2
Add a clock for video input subsystem (EXIV) on
UniPhier LD11/LD20 SoCs.
Signed-off-by: Katsuhiro Suzuki <[email protected]>
---
drivers/clk/uniphier/clk-uniphier-sys.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/clk/uniphier/clk-uniphier-sys.c b/drivers/clk/uniphier/clk-uniphier-sys.c
index 7c4528d0fb6e..c60aa586fea7 100644
--- a/drivers/clk/uniphier/clk-uniphier-sys.c
+++ b/drivers/clk/uniphier/clk-uniphier-sys.c
@@ -65,6 +65,10 @@
UNIPHIER_CLK_FACTOR("evea-io100m", -1, "spll", 1, 20), \
UNIPHIER_CLK_GATE("evea", (idx), "evea-io100m", 0x2108, 1)
+#define UNIPHIER_LD11_SYS_CLK_EXIV(idx) \
+ UNIPHIER_CLK_FACTOR("exiv-io200m", -1, "spll", 1, 10), \
+ UNIPHIER_CLK_GATE("exiv", (idx), "exiv-io200m", 0x2110, 2)
+
const struct uniphier_clk_data uniphier_sld3_sys_clk_data[] = {
UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
@@ -168,6 +172,7 @@ const struct uniphier_clk_data uniphier_ld11_sys_clk_data[] = {
UNIPHIER_CLK_FACTOR("usb2", -1, "ref", 24, 25),
UNIPHIER_LD11_SYS_CLK_AIO(40),
UNIPHIER_LD11_SYS_CLK_EVEA(41),
+ UNIPHIER_LD11_SYS_CLK_EXIV(42),
/* CPU gears */
UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
UNIPHIER_CLK_DIV4("mpll", 2, 3, 4, 8),
@@ -206,6 +211,7 @@ const struct uniphier_clk_data uniphier_ld20_sys_clk_data[] = {
UNIPHIER_CLK_GATE("usb30-phy1", 17, NULL, 0x210c, 13),
UNIPHIER_LD11_SYS_CLK_AIO(40),
UNIPHIER_LD11_SYS_CLK_EVEA(41),
+ UNIPHIER_LD11_SYS_CLK_EXIV(42),
/* CPU gears */
UNIPHIER_CLK_DIV4("cpll", 2, 3, 4, 8),
UNIPHIER_CLK_DIV4("spll", 2, 3, 4, 8),
--
2.13.2
2017-08-10 16:23 GMT+09:00 Katsuhiro Suzuki <[email protected]>:
> Add clock for audio subsystem (AIO) and SoC internal audio codec
> (EVEA) on UniPhier LD11/LD20 SoCs.
>
> Signed-off-by: Katsuhiro Suzuki <[email protected]>
> ---
Acked-by: Masahiro Yamada <[email protected]>
--
Best Regards
Masahiro Yamada
2017-08-10 16:23 GMT+09:00 Katsuhiro Suzuki <[email protected]>:
> Add a clock for video input subsystem (EXIV) on
> UniPhier LD11/LD20 SoCs.
>
> Signed-off-by: Katsuhiro Suzuki <[email protected]>
Acked-by: Masahiro Yamada <[email protected]>
--
Best Regards
Masahiro Yamada
On 08/10, Katsuhiro Suzuki wrote:
> Add clock for audio subsystem (AIO) and SoC internal audio codec
> (EVEA) on UniPhier LD11/LD20 SoCs.
>
> Signed-off-by: Katsuhiro Suzuki <[email protected]>
> ---
Applied to clk-next with some conflict resolving.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
On 08/10, Katsuhiro Suzuki wrote:
> Add a clock for video input subsystem (EXIV) on
> UniPhier LD11/LD20 SoCs.
>
> Signed-off-by: Katsuhiro Suzuki <[email protected]>
> ---
Applied to clk-next with some conflict resolving, please check.
--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project
Hello Stephen,
> Applied to clk-next with some conflict resolving, please check.
No problem. Thank you for applying!
Regards,
--
Katsuhiro Suzuki
> -----Original Message-----
> From: Stephen Boyd [mailto:[email protected]]
> Sent: Friday, September 1, 2017 10:42 AM
> To: Suzuki, Katsuhiro/$BNkLZ(B $B>!Gn(B <[email protected]>
> Cc: Michael Turquette <[email protected]>; Yamada, Masahiro/$B;3ED(B $B??90(B
> <[email protected]>; [email protected]; Masami Hiramatsu <[email protected]>;
> Jassi Brar <[email protected]>; [email protected]
> Subject: Re: [PATCH 2/2] clk: uniphier: add video input subsystem clock
>
> On 08/10, Katsuhiro Suzuki wrote:
> > Add a clock for video input subsystem (EXIV) on UniPhier LD11/LD20
> > SoCs.
> >
> > Signed-off-by: Katsuhiro Suzuki <[email protected]>
> > ---
>
> Applied to clk-next with some conflict resolving, please check.
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project