Initialize the IST based traps via a table
Signed-off-by: Thomas Gleixner <[email protected]>
---
arch/x86/include/asm/desc.h | 2 ++
arch/x86/kernel/idt.c | 22 ++++++++++++++++++++++
arch/x86/kernel/traps.c | 9 +--------
3 files changed, 25 insertions(+), 8 deletions(-)
--- a/arch/x86/include/asm/desc.h
+++ b/arch/x86/include/asm/desc.h
@@ -509,9 +509,11 @@ extern void idt_setup_early_traps(void);
#ifdef CONFIG_X86_64
extern void idt_setup_early_pf(void);
+extern void idt_setup_ist_traps(void);
extern void idt_setup_debugidt_traps(void);
#else
static inline void idt_setup_early_pf(void) { }
+static inline void idt_setup_ist_traps(void) { }
static inline void idt_setup_debugidt_traps(void) { }
#endif
--- a/arch/x86/kernel/idt.c
+++ b/arch/x86/kernel/idt.c
@@ -92,6 +92,20 @@ struct desc_ptr idt_descr __ro_after_ini
gate_desc debug_idt_table[IDT_ENTRIES] __page_aligned_bss;
/*
+ * The exceptions which use Interrupt stacks. They are setup after
+ * cpu_init() when the TSS has been initialized.
+ */
+static const __initdata struct idt_data ist_idts[] = {
+ ISTG(X86_TRAP_DB, debug, DEBUG_STACK),
+ ISTG(X86_TRAP_NMI, nmi, NMI_STACK),
+ ISTG(X86_TRAP_BP, int3, DEBUG_STACK),
+ ISTG(X86_TRAP_DF, double_fault, DOUBLEFAULT_STACK),
+#ifdef CONFIG_X86_MCE
+ ISTG(X86_TRAP_MC, &machine_check, MCE_STACK),
+#endif
+};
+
+/*
* Override for the debug_idt. Same as the default, but with interrupt
* stack set to DEFAULT_STACK (0). Required for NMI trap handling.
*/
@@ -158,6 +172,14 @@ void __init idt_setup_early_pf(void)
}
/**
+ * idt_setup_ist_traps - Initialize the idt table with traps using IST
+ */
+void __init idt_setup_ist_traps(void)
+{
+ idt_setup_from_table(idt_table, ist_idts, ARRAY_SIZE(ist_idts));
+}
+
+/**
* idt_setup_debugidt_traps - Initialize the debug idt table with debug traps
*/
void __init idt_setup_debugidt_traps(void)
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -979,14 +979,7 @@ void __init trap_init(void)
*/
cpu_init();
- /*
- * X86_TRAP_DB and X86_TRAP_BP have been set
- * in early_trap_init(). However, ITS works only after
- * cpu_init() loads TSS. See comments in early_trap_init().
- */
- set_intr_gate_ist(X86_TRAP_DB, &debug, DEBUG_STACK);
- /* int3 can be called from all */
- set_system_intr_gate_ist(X86_TRAP_BP, &int3, DEBUG_STACK);
+ idt_setup_ist_traps();
x86_init.irqs.trap_init();
Commit-ID: 90f6225fba0c732f3f5f9f5e265bdefa021ff12d
Gitweb: http://git.kernel.org/tip/90f6225fba0c732f3f5f9f5e265bdefa021ff12d
Author: Thomas Gleixner <[email protected]>
AuthorDate: Mon, 28 Aug 2017 08:47:52 +0200
Committer: Ingo Molnar <[email protected]>
CommitDate: Tue, 29 Aug 2017 12:07:27 +0200
x86/idt: Move IST stack based traps to table init
Initialize the IST based traps via a table.
Signed-off-by: Thomas Gleixner <[email protected]>
Cc: Andy Lutomirski <[email protected]>
Cc: Borislav Petkov <[email protected]>
Cc: Brian Gerst <[email protected]>
Cc: Denys Vlasenko <[email protected]>
Cc: H. Peter Anvin <[email protected]>
Cc: Josh Poimboeuf <[email protected]>
Cc: Linus Torvalds <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Steven Rostedt <[email protected]>
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>
---
arch/x86/include/asm/desc.h | 2 ++
arch/x86/kernel/idt.c | 22 ++++++++++++++++++++++
arch/x86/kernel/traps.c | 9 +--------
3 files changed, 25 insertions(+), 8 deletions(-)
diff --git a/arch/x86/include/asm/desc.h b/arch/x86/include/asm/desc.h
index 930acd5..e624527 100644
--- a/arch/x86/include/asm/desc.h
+++ b/arch/x86/include/asm/desc.h
@@ -509,9 +509,11 @@ extern void idt_setup_early_traps(void);
#ifdef CONFIG_X86_64
extern void idt_setup_early_pf(void);
+extern void idt_setup_ist_traps(void);
extern void idt_setup_debugidt_traps(void);
#else
static inline void idt_setup_early_pf(void) { }
+static inline void idt_setup_ist_traps(void) { }
static inline void idt_setup_debugidt_traps(void) { }
#endif
diff --git a/arch/x86/kernel/idt.c b/arch/x86/kernel/idt.c
index f5281b8..a6326fd 100644
--- a/arch/x86/kernel/idt.c
+++ b/arch/x86/kernel/idt.c
@@ -92,6 +92,20 @@ struct desc_ptr idt_descr __ro_after_init = {
gate_desc debug_idt_table[IDT_ENTRIES] __page_aligned_bss;
/*
+ * The exceptions which use Interrupt stacks. They are setup after
+ * cpu_init() when the TSS has been initialized.
+ */
+static const __initdata struct idt_data ist_idts[] = {
+ ISTG(X86_TRAP_DB, debug, DEBUG_STACK),
+ ISTG(X86_TRAP_NMI, nmi, NMI_STACK),
+ ISTG(X86_TRAP_BP, int3, DEBUG_STACK),
+ ISTG(X86_TRAP_DF, double_fault, DOUBLEFAULT_STACK),
+#ifdef CONFIG_X86_MCE
+ ISTG(X86_TRAP_MC, &machine_check, MCE_STACK),
+#endif
+};
+
+/*
* Override for the debug_idt. Same as the default, but with interrupt
* stack set to DEFAULT_STACK (0). Required for NMI trap handling.
*/
@@ -158,6 +172,14 @@ void __init idt_setup_early_pf(void)
}
/**
+ * idt_setup_ist_traps - Initialize the idt table with traps using IST
+ */
+void __init idt_setup_ist_traps(void)
+{
+ idt_setup_from_table(idt_table, ist_idts, ARRAY_SIZE(ist_idts));
+}
+
+/**
* idt_setup_debugidt_traps - Initialize the debug idt table with debug traps
*/
void __init idt_setup_debugidt_traps(void)
diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
index 1492bf5..293f5bd 100644
--- a/arch/x86/kernel/traps.c
+++ b/arch/x86/kernel/traps.c
@@ -979,14 +979,7 @@ void __init trap_init(void)
*/
cpu_init();
- /*
- * X86_TRAP_DB and X86_TRAP_BP have been set
- * in early_trap_init(). However, ITS works only after
- * cpu_init() loads TSS. See comments in early_trap_init().
- */
- set_intr_gate_ist(X86_TRAP_DB, &debug, DEBUG_STACK);
- /* int3 can be called from all */
- set_system_intr_gate_ist(X86_TRAP_BP, &int3, DEBUG_STACK);
+ idt_setup_ist_traps();
x86_init.irqs.trap_init();
Hi Thomas,
We run CRIU tests for linux-next and today they detected an issue. I've
bisected this problem and it looks like a problem is in this patch.
[root@fc24 criu]# python ./test/zdtm.py run -t zdtm/static/env00
=== Run 1/1 ================ zdtm/static/env00
========================== Run zdtm/static/env00 in h ==========================
Start test
./env00 --pidfile=env00.pid --outfile=env00.out --envname=ENV_00_TEST
Run criu dump
=[log]=> dump/zdtm/static/env00/36/1/dump.log
------------------------ grep Error ------------------------
(00.004013) Dump private signals of 36
(00.004022) Dump shared signals of 36
(00.004036) Parasite syscall_ip at 0x400000
(00.004097) ** delivering signal 11 si_code=128
(00.004103) Error (compel/src/lib/infect.c:528): Unexpected 36 task interruption, aborting
(00.004118) Error (criu/cr-dump.c:1371): Can't infect (pid: 36) with parasite
(00.004208) Unlock network
(00.004218) Unfreezing tasks into 1
(00.004223) Unseizing 36 into 1
(00.004244) Error (criu/cr-dump.c:1807): Dumping FAILED.
------------------------ ERROR OVER ------------------------
################### Test zdtm/static/env00 FAIL at CRIU dump ###################
Send the 9 signal to 36
Wait for zdtm/static/env00(36) to die for 0.100000
##################################### FAIL #####################################
Here is a line in a code where we get this unexpected error:
https://github.com/xemul/criu/blob/criu-dev/compel/src/lib/infect.c#L735
At this moment criu tries to execute the memfd_create syscall in a
context of another task with help of ptrace.
Here is a link to a test job:
https://travis-ci.org/avagin/linux/builds/270623449
Thanks,
Andrei
On Tue, Aug 29, 2017 at 04:18:51AM -0700, tip-bot for Jacob Shin wrote:
> Commit-ID: 90f6225fba0c732f3f5f9f5e265bdefa021ff12d
> Gitweb: http://git.kernel.org/tip/90f6225fba0c732f3f5f9f5e265bdefa021ff12d
> Author: Thomas Gleixner <[email protected]>
> AuthorDate: Mon, 28 Aug 2017 08:47:52 +0200
> Committer: Ingo Molnar <[email protected]>
> CommitDate: Tue, 29 Aug 2017 12:07:27 +0200
>
> x86/idt: Move IST stack based traps to table init
>
> Initialize the IST based traps via a table.
>
> Signed-off-by: Thomas Gleixner <[email protected]>
> Cc: Andy Lutomirski <[email protected]>
> Cc: Borislav Petkov <[email protected]>
> Cc: Brian Gerst <[email protected]>
> Cc: Denys Vlasenko <[email protected]>
> Cc: H. Peter Anvin <[email protected]>
> Cc: Josh Poimboeuf <[email protected]>
> Cc: Linus Torvalds <[email protected]>
> Cc: Peter Zijlstra <[email protected]>
> Cc: Steven Rostedt <[email protected]>
> Link: http://lkml.kernel.org/r/[email protected]
> Signed-off-by: Ingo Molnar <[email protected]>
> ---
> arch/x86/include/asm/desc.h | 2 ++
> arch/x86/kernel/idt.c | 22 ++++++++++++++++++++++
> arch/x86/kernel/traps.c | 9 +--------
> 3 files changed, 25 insertions(+), 8 deletions(-)
>
> diff --git a/arch/x86/include/asm/desc.h b/arch/x86/include/asm/desc.h
> index 930acd5..e624527 100644
> --- a/arch/x86/include/asm/desc.h
> +++ b/arch/x86/include/asm/desc.h
> @@ -509,9 +509,11 @@ extern void idt_setup_early_traps(void);
>
> #ifdef CONFIG_X86_64
> extern void idt_setup_early_pf(void);
> +extern void idt_setup_ist_traps(void);
> extern void idt_setup_debugidt_traps(void);
> #else
> static inline void idt_setup_early_pf(void) { }
> +static inline void idt_setup_ist_traps(void) { }
> static inline void idt_setup_debugidt_traps(void) { }
> #endif
>
> diff --git a/arch/x86/kernel/idt.c b/arch/x86/kernel/idt.c
> index f5281b8..a6326fd 100644
> --- a/arch/x86/kernel/idt.c
> +++ b/arch/x86/kernel/idt.c
> @@ -92,6 +92,20 @@ struct desc_ptr idt_descr __ro_after_init = {
> gate_desc debug_idt_table[IDT_ENTRIES] __page_aligned_bss;
>
> /*
> + * The exceptions which use Interrupt stacks. They are setup after
> + * cpu_init() when the TSS has been initialized.
> + */
> +static const __initdata struct idt_data ist_idts[] = {
> + ISTG(X86_TRAP_DB, debug, DEBUG_STACK),
> + ISTG(X86_TRAP_NMI, nmi, NMI_STACK),
> + ISTG(X86_TRAP_BP, int3, DEBUG_STACK),
> + ISTG(X86_TRAP_DF, double_fault, DOUBLEFAULT_STACK),
> +#ifdef CONFIG_X86_MCE
> + ISTG(X86_TRAP_MC, &machine_check, MCE_STACK),
> +#endif
> +};
> +
> +/*
> * Override for the debug_idt. Same as the default, but with interrupt
> * stack set to DEFAULT_STACK (0). Required for NMI trap handling.
> */
> @@ -158,6 +172,14 @@ void __init idt_setup_early_pf(void)
> }
>
> /**
> + * idt_setup_ist_traps - Initialize the idt table with traps using IST
> + */
> +void __init idt_setup_ist_traps(void)
> +{
> + idt_setup_from_table(idt_table, ist_idts, ARRAY_SIZE(ist_idts));
> +}
> +
> +/**
> * idt_setup_debugidt_traps - Initialize the debug idt table with debug traps
> */
> void __init idt_setup_debugidt_traps(void)
> diff --git a/arch/x86/kernel/traps.c b/arch/x86/kernel/traps.c
> index 1492bf5..293f5bd 100644
> --- a/arch/x86/kernel/traps.c
> +++ b/arch/x86/kernel/traps.c
> @@ -979,14 +979,7 @@ void __init trap_init(void)
> */
> cpu_init();
>
> - /*
> - * X86_TRAP_DB and X86_TRAP_BP have been set
> - * in early_trap_init(). However, ITS works only after
> - * cpu_init() loads TSS. See comments in early_trap_init().
> - */
> - set_intr_gate_ist(X86_TRAP_DB, &debug, DEBUG_STACK);
> - /* int3 can be called from all */
> - set_system_intr_gate_ist(X86_TRAP_BP, &int3, DEBUG_STACK);
> + idt_setup_ist_traps();
>
> x86_init.irqs.trap_init();
>
Hi Andrei,
* Andrei Vagin <[email protected]> wrote:
> Hi Thomas,
>
> We run CRIU tests for linux-next and today they detected an issue. I've
> bisected this problem and it looks like a problem is in this patch.
Ok, there appears to be a bug in that conversion - does the patch below fix the
regression for you?
Thanks,
Ingo
================================>
Subject: x86/idt: Fix the X86_TRAP_BP gate
From: Ingo Molnar <[email protected]>
Andrei Vagin reported a CRIU regression and bisected it back to:
90f6225fba0c ("x86/idt: Move IST stack based traps to table init")
This table init conversion loses the system-gate property of X86_TRAP_BP
and erroneously moves it from DPL3 to DPL0.
Fix it.
Reported-by: Andrei Vagin <[email protected]>
Cc: Linus Torvalds <[email protected]>
Cc: Peter Zijlstra <[email protected]>
Cc: Thomas Gleixner <[email protected]>
Signed-off-by: Ingo Molnar <[email protected]>
---
arch/x86/kernel/idt.c | 6 +++++-
arch/x86/kernel/idt.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
Index: tip/arch/x86/kernel/idt.c
===================================================================
--- tip.orig/arch/x86/kernel/idt.c
+++ tip/arch/x86/kernel/idt.c
@@ -44,6 +44,10 @@ struct idt_data {
#define ISTG(_vector, _addr, _ist) \
G(_vector, _addr, _ist, GATE_INTERRUPT, DPL0, __KERNEL_CS)
+/* System interrupt gate with interrupt stack */
+#define SISTG(_vector, _addr, _ist) \
+ G(_vector, _addr, _ist, GATE_INTERRUPT, DPL3, __KERNEL_CS)
+
/* Task gate */
#define TSKG(_vector, _gdt) \
G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3)
@@ -181,7 +185,7 @@ gate_desc debug_idt_table[IDT_ENTRIES] _
static const __initdata struct idt_data ist_idts[] = {
ISTG(X86_TRAP_DB, debug, DEBUG_STACK),
ISTG(X86_TRAP_NMI, nmi, NMI_STACK),
- ISTG(X86_TRAP_BP, int3, DEBUG_STACK),
+ SISTG(X86_TRAP_BP, int3, DEBUG_STACK),
ISTG(X86_TRAP_DF, double_fault, DOUBLEFAULT_STACK),
#ifdef CONFIG_X86_MCE
ISTG(X86_TRAP_MC, &machine_check, MCE_STACK),
On Fri, 1 Sep 2017, Ingo Molnar wrote:
> Subject: x86/idt: Fix the X86_TRAP_BP gate
> From: Ingo Molnar <[email protected]>
>
> Andrei Vagin reported a CRIU regression and bisected it back to:
>
> 90f6225fba0c ("x86/idt: Move IST stack based traps to table init")
>
> This table init conversion loses the system-gate property of X86_TRAP_BP
> and erroneously moves it from DPL3 to DPL0.
Duh, yes. Thanks for spotting it.
> Fix it.
>
> Reported-by: Andrei Vagin <[email protected]>
> Cc: Linus Torvalds <[email protected]>
> Cc: Peter Zijlstra <[email protected]>
> Cc: Thomas Gleixner <[email protected]>
> Signed-off-by: Ingo Molnar <[email protected]>
> ---
> arch/x86/kernel/idt.c | 6 +++++-
> arch/x86/kernel/idt.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> Index: tip/arch/x86/kernel/idt.c
> ===================================================================
> --- tip.orig/arch/x86/kernel/idt.c
> +++ tip/arch/x86/kernel/idt.c
> @@ -44,6 +44,10 @@ struct idt_data {
> #define ISTG(_vector, _addr, _ist) \
> G(_vector, _addr, _ist, GATE_INTERRUPT, DPL0, __KERNEL_CS)
>
> +/* System interrupt gate with interrupt stack */
> +#define SISTG(_vector, _addr, _ist) \
> + G(_vector, _addr, _ist, GATE_INTERRUPT, DPL3, __KERNEL_CS)
> +
> /* Task gate */
> #define TSKG(_vector, _gdt) \
> G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3)
> @@ -181,7 +185,7 @@ gate_desc debug_idt_table[IDT_ENTRIES] _
> static const __initdata struct idt_data ist_idts[] = {
> ISTG(X86_TRAP_DB, debug, DEBUG_STACK),
> ISTG(X86_TRAP_NMI, nmi, NMI_STACK),
> - ISTG(X86_TRAP_BP, int3, DEBUG_STACK),
> + SISTG(X86_TRAP_BP, int3, DEBUG_STACK),
> ISTG(X86_TRAP_DF, double_fault, DOUBLEFAULT_STACK),
> #ifdef CONFIG_X86_MCE
> ISTG(X86_TRAP_MC, &machine_check, MCE_STACK),
>
Commit-ID: c6ef89421e236d75693ae968d80d44a52409889d
Gitweb: http://git.kernel.org/tip/c6ef89421e236d75693ae968d80d44a52409889d
Author: Ingo Molnar <[email protected]>
AuthorDate: Fri, 1 Sep 2017 11:04:56 +0200
Committer: Thomas Gleixner <[email protected]>
CommitDate: Fri, 1 Sep 2017 11:04:56 +0200
x86/idt: Fix the X86_TRAP_BP gate
Andrei Vagin reported a CRIU regression and bisected it back to:
90f6225fba0c ("x86/idt: Move IST stack based traps to table init")
This table init conversion loses the system-gate property of X86_TRAP_BP
and erroneously moves it from DPL3 to DPL0.
Fix it.
Reported-by: Andrei Vagin <[email protected]>
Signed-off-by: Ingo Molnar <[email protected]>
Signed-off-by: Thomas Gleixner <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Cc: Cyrill Gorcunov <[email protected]>
Cc: [email protected]
Cc: tip-bot for Jacob Shin <[email protected]>
Link: http://lkml.kernel.org/r/[email protected]
---
arch/x86/kernel/idt.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/idt.c b/arch/x86/kernel/idt.c
index 61b490c..6107ee1 100644
--- a/arch/x86/kernel/idt.c
+++ b/arch/x86/kernel/idt.c
@@ -44,6 +44,10 @@ struct idt_data {
#define ISTG(_vector, _addr, _ist) \
G(_vector, _addr, _ist, GATE_INTERRUPT, DPL0, __KERNEL_CS)
+/* System interrupt gate with interrupt stack */
+#define SISTG(_vector, _addr, _ist) \
+ G(_vector, _addr, _ist, GATE_INTERRUPT, DPL3, __KERNEL_CS)
+
/* Task gate */
#define TSKG(_vector, _gdt) \
G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3)
@@ -181,7 +185,7 @@ gate_desc debug_idt_table[IDT_ENTRIES] __page_aligned_bss;
static const __initdata struct idt_data ist_idts[] = {
ISTG(X86_TRAP_DB, debug, DEBUG_STACK),
ISTG(X86_TRAP_NMI, nmi, NMI_STACK),
- ISTG(X86_TRAP_BP, int3, DEBUG_STACK),
+ SISTG(X86_TRAP_BP, int3, DEBUG_STACK),
ISTG(X86_TRAP_DF, double_fault, DOUBLEFAULT_STACK),
#ifdef CONFIG_X86_MCE
ISTG(X86_TRAP_MC, &machine_check, MCE_STACK),
On Fri, Sep 01, 2017 at 10:26:30AM +0200, Ingo Molnar wrote:
>
> Hi Andrei,
>
> * Andrei Vagin <[email protected]> wrote:
>
> > Hi Thomas,
> >
> > We run CRIU tests for linux-next and today they detected an issue. I've
> > bisected this problem and it looks like a problem is in this patch.
>
> Ok, there appears to be a bug in that conversion - does the patch below fix the
> regression for you?
Yes, it is.
Thank you!
>
> Thanks,
>
> Ingo
>
> ================================>
> Subject: x86/idt: Fix the X86_TRAP_BP gate
> From: Ingo Molnar <[email protected]>
>
> Andrei Vagin reported a CRIU regression and bisected it back to:
>
> 90f6225fba0c ("x86/idt: Move IST stack based traps to table init")
>
> This table init conversion loses the system-gate property of X86_TRAP_BP
> and erroneously moves it from DPL3 to DPL0.
>
> Fix it.
>
> Reported-by: Andrei Vagin <[email protected]>
> Cc: Linus Torvalds <[email protected]>
> Cc: Peter Zijlstra <[email protected]>
> Cc: Thomas Gleixner <[email protected]>
> Signed-off-by: Ingo Molnar <[email protected]>
> ---
> arch/x86/kernel/idt.c | 6 +++++-
> arch/x86/kernel/idt.c | 6 +++++-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> Index: tip/arch/x86/kernel/idt.c
> ===================================================================
> --- tip.orig/arch/x86/kernel/idt.c
> +++ tip/arch/x86/kernel/idt.c
> @@ -44,6 +44,10 @@ struct idt_data {
> #define ISTG(_vector, _addr, _ist) \
> G(_vector, _addr, _ist, GATE_INTERRUPT, DPL0, __KERNEL_CS)
>
> +/* System interrupt gate with interrupt stack */
> +#define SISTG(_vector, _addr, _ist) \
> + G(_vector, _addr, _ist, GATE_INTERRUPT, DPL3, __KERNEL_CS)
> +
> /* Task gate */
> #define TSKG(_vector, _gdt) \
> G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3)
> @@ -181,7 +185,7 @@ gate_desc debug_idt_table[IDT_ENTRIES] _
> static const __initdata struct idt_data ist_idts[] = {
> ISTG(X86_TRAP_DB, debug, DEBUG_STACK),
> ISTG(X86_TRAP_NMI, nmi, NMI_STACK),
> - ISTG(X86_TRAP_BP, int3, DEBUG_STACK),
> + SISTG(X86_TRAP_BP, int3, DEBUG_STACK),
> ISTG(X86_TRAP_DF, double_fault, DOUBLEFAULT_STACK),
> #ifdef CONFIG_X86_MCE
> ISTG(X86_TRAP_MC, &machine_check, MCE_STACK),