2017-11-27 18:58:51

by Eugeniy Paltsev

Subject: [PATCH 0/4] ARC: Set initial core pll output frequency via DTS

Set initial core pll output frequency on HSDK and AXS103 via
"assigned-clock-rates" property in device tree.
It will be applied at the core pll driver probing.

Eugeniy Paltsev (4):
ARC: [plat-hsdk]: Set initial core pll output frequency
ARC: [plat-hsdk]: Get rid of core pll frequency set in platform code
ARC: [plat-axs103]: Set initial core pll output frequency
ARC: [plat-axs103] refactor the quad core DT quirk code

arch/arc/boot/dts/axc003.dtsi | 3 +++
arch/arc/boot/dts/axc003_idu.dtsi | 3 +++
arch/arc/boot/dts/hsdk.dts | 3 +++
arch/arc/plat-axs10x/axs10x.c | 18 ++++++++---------
arch/arc/plat-hsdk/platform.c | 42 ---------------------------------------
5 files changed, 17 insertions(+), 52 deletions(-)

--
2.9.3


From 1583998623039602266@xxx Tue Nov 14 00:20:04 +0000 2017
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2017-11-27 19:00:25

by Eugeniy Paltsev

Subject: [PATCH 1/4] ARC: [plat-hsdk]: Set initial core pll output frequency

Set initial core pll output frequency specified in device tree to
1GHz. It will be applied at the core pll driver probing.

Signed-off-by: Eugeniy Paltsev <[email protected]>
---
arch/arc/boot/dts/hsdk.dts | 8 ++++++++
1 file changed, 8 insertions(+)

diff --git a/arch/arc/boot/dts/hsdk.dts b/arch/arc/boot/dts/hsdk.dts
index 8f627c2..006aa3d 100644
--- a/arch/arc/boot/dts/hsdk.dts
+++ b/arch/arc/boot/dts/hsdk.dts
@@ -114,6 +114,14 @@
reg = <0x00 0x10>, <0x14B8 0x4>;
#clock-cells = <0>;
clocks = <&input_clk>;
+
+ /*
+ * Set initial core pll output frequency to 1GHz.
+ * It will be applied at the core pll driver probing
+ * on early boot.
+ */
+ assigned-clocks = <&core_clk>;
+ assigned-clock-rates = <1000000000>;
};

serial: serial@5000 {
--
2.9.3


From 1586234315046897834@xxx Fri Dec 08 16:35:26 +0000 2017
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