by Maxime Ripard

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Subject: Re: [PATCH v7 08/11] ARM: sun9i: smp: Add is_a83t field

On Fri, Apr 20, 2018 at 11:10:19PM +0200, Myl?ne Josserand wrote:
> To prepare the support of sun8i-a83t, add a field in the smp_data
> structure to know if we are on sun9i-a80 or sun8i-a83t.
>
> Add also a global variable to retrieve which architecture we are
> having.
>
> Signed-off-by: Myl?ne Josserand <[email protected]>
> ---
> arch/arm/mach-sunxi/mc_smp.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm/mach-sunxi/mc_smp.c b/arch/arm/mach-sunxi/mc_smp.c
> index 03f021d0c73e..48e5f4db64b6 100644
> --- a/arch/arm/mach-sunxi/mc_smp.c
> +++ b/arch/arm/mach-sunxi/mc_smp.c
> @@ -74,6 +74,7 @@ static void __iomem *sram_b_smp_base;
>
> extern void sunxi_mc_smp_secondary_startup(void);
> extern void sunxi_mc_smp_resume(void);
> +static int is_a83t;
>
> static bool sunxi_core_is_cortex_a15(unsigned int core, unsigned int cluster)
> {
> @@ -624,6 +625,7 @@ struct sunxi_mc_smp_nodes {
> struct sunxi_mc_smp_data {
> const char *enable_method;
> int (*get_smp_nodes)(struct sunxi_mc_smp_nodes *nodes);
> + int is_a83t;

This can be made a boolean.

Maxime

--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

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2018-04-23 08:18:49

by Maxime Ripard

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Subject: Re: [PATCH v7 06/11] ARM: sunxi: Add initialization of CNTVOFF

On Fri, Apr 20, 2018 at 11:10:17PM +0200, Myl?ne Josserand wrote:
> Add the initialization of CNTVOFF for sun8i-a83t.
>
> For boot CPU, create a new machine that handles this
> function's call in an "init_early" callback. We need to initialize
> CNTVOFF before the arch timer's initialization otherwise, it will
> not be taken into account and fails to boot correctly.
> Because of that, this function can't be called in SMP's early_initcall
> function which is called after timer's init.
>
> For secondary CPUs, add this function into secondary_startup
> assembly entry.
>
> Signed-off-by: Myl?ne Josserand <[email protected]>
> ---
> arch/arm/mach-sunxi/headsmp.S | 1 +
> arch/arm/mach-sunxi/sunxi.c | 20 +++++++++++++++++++-
> 2 files changed, 20 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-sunxi/headsmp.S b/arch/arm/mach-sunxi/headsmp.S
> index 37dc772701f3..32d76be98541 100644
> --- a/arch/arm/mach-sunxi/headsmp.S
> +++ b/arch/arm/mach-sunxi/headsmp.S
> @@ -71,6 +71,7 @@ ENDPROC(sunxi_mc_smp_cluster_cache_enable)
>
> ENTRY(sunxi_mc_smp_secondary_startup)
> bl sunxi_mc_smp_cluster_cache_enable
> + bl secure_cntvoff_init
> b secondary_startup
> ENDPROC(sunxi_mc_smp_secondary_startup)
>
> diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
> index 5e9602ce1573..ddc439f6269b 100644
> --- a/arch/arm/mach-sunxi/sunxi.c
> +++ b/arch/arm/mach-sunxi/sunxi.c
> @@ -16,6 +16,7 @@
> #include <linux/platform_device.h>
>
> #include <asm/mach/arch.h>
> +#include <asm/secure_cntvoff.h>
>
> static const char * const sunxi_board_dt_compat[] = {
> "allwinner,sun4i-a10",
> @@ -62,7 +63,6 @@ MACHINE_END
> static const char * const sun8i_board_dt_compat[] = {
> "allwinner,sun8i-a23",
> "allwinner,sun8i-a33",
> - "allwinner,sun8i-a83t",
> "allwinner,sun8i-h2-plus",
> "allwinner,sun8i-h3",
> "allwinner,sun8i-r40",
> @@ -75,6 +75,24 @@ DT_MACHINE_START(SUN8I_DT, "Allwinner sun8i Family")
> .dt_compat = sun8i_board_dt_compat,
> MACHINE_END
>
> +void __init sun8i_cntvoff_init(void)
> +{
> +#ifdef CONFIG_SMP
> + secure_cntvoff_init();
> +#endif
> +}
> +
> +static const char * const sun8i_cntvoff_board_dt_compat[] = {
> + "allwinner,sun8i-a83t",
> + NULL,
> +};
> +
> +DT_MACHINE_START(SUN8I_CNTVOFF_DT, "Allwinner sun8i-a83t board")

This name still doesn't really make much sense. It's an A83t, that's
it.

Apart from the other minor comment I had, and once that name has been
fixed:
Acked-by: Maxime Ripard <[email protected]>

Maxime

--
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com

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2018-04-26 18:30:01

On Fri, Apr 20, 2018 at 11:10:16PM +0200, Myl?ne Josserand wrote:
> The CNTVOFF register from arch timer is uninitialized.
> It should be done by the bootloader but it is currently not the case,
> even for boot CPU because this SoC is booting in secure mode.
> It leads to an random offset value meaning that each CPU will have a
> different time, which isn't working very well.
>
> Add assembly code used for boot CPU and secondary CPU cores to make
> sure that the CNTVOFF register is initialized. Because this code can
> be used by different platforms, add this assembly file in ARM's common
> folder.
>
> Signed-off-by: Myl?ne Josserand <[email protected]>
> Reviewed-by: Geert Uytterhoeven <[email protected]>
> Tested-by: Geert Uytterhoeven <[email protected]>
> ---
> arch/arm/common/Makefile | 1 +
> arch/arm/common/secure_cntvoff.S | 31 +++++++++++++++++++++++++++++++
> arch/arm/include/asm/secure_cntvoff.h | 8 ++++++++
> 3 files changed, 40 insertions(+)
> create mode 100644 arch/arm/common/secure_cntvoff.S
> create mode 100644 arch/arm/include/asm/secure_cntvoff.h
>
> diff --git a/arch/arm/common/Makefile b/arch/arm/common/Makefile
> index 70b4a14ed993..1e9f7af8f70f 100644
> --- a/arch/arm/common/Makefile
> +++ b/arch/arm/common/Makefile
> @@ -10,6 +10,7 @@ obj-$(CONFIG_DMABOUNCE) += dmabounce.o
> obj-$(CONFIG_SHARP_LOCOMO) += locomo.o
> obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o
> obj-$(CONFIG_SHARP_SCOOP) += scoop.o
> +obj-$(CONFIG_SMP) += secure_cntvoff.o
> obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o
> obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
> CFLAGS_REMOVE_mcpm_entry.o = -pg
> diff --git a/arch/arm/common/secure_cntvoff.S b/arch/arm/common/secure_cntvoff.S
> new file mode 100644
> index 000000000000..68a4a8344319
> --- /dev/null
> +++ b/arch/arm/common/secure_cntvoff.S
> @@ -0,0 +1,31 @@
> +/* SPDX-License-Identifier: GPL-2.0

For assembly files, the SPDX specifier is of this format:

/* SPDX-License-Identifier: <SPDX License Expression> */

Please see Documentation/process/license-rules.rst for more
information, and fix your specifier to conform to the requirements.
Thanks.

> + *
> + * Copyright (C) 2014 Renesas Electronics Corporation
> + *
> + * Initialization of CNTVOFF register from secure mode
> + *
> + */
> +
> +#include <linux/linkage.h>
> +#include <asm/assembler.h>
> +
> +ENTRY(secure_cntvoff_init)
> + .arch armv7-a
> + /*
> + * CNTVOFF has to be initialized either from non-secure Hypervisor
> + * mode or secure Monitor mode with SCR.NS==1. If TrustZone is enabled
> + * then it should be handled by the secure code

This should also state that this code must not be executed if
virtualisation extensions are not present (which should be obvious)
as the mcrr instruction becomes unpredictable in that case.

> + */
> + cps #MON_MODE
> + mrc p15, 0, r1, c1, c1, 0 /* Get Secure Config */
> + orr r0, r1, #1
> + mcr p15, 0, r0, c1, c1, 0 /* Set Non Secure bit */
> + isb
> + mov r0, #0
> + mcrr p15, 4, r0, r0, c14 /* CNTVOFF = 0 */
> + isb
> + mcr p15, 0, r1, c1, c1, 0 /* Set Secure bit */
> + isb
> + cps #SVC_MODE
> + ret lr
> +ENDPROC(secure_cntvoff_init)
> diff --git a/arch/arm/include/asm/secure_cntvoff.h b/arch/arm/include/asm/secure_cntvoff.h
> new file mode 100644
> index 000000000000..1f93aee1f630
> --- /dev/null
> +++ b/arch/arm/include/asm/secure_cntvoff.h
> @@ -0,0 +1,8 @@
> +/* SPDX-License-Identifier: GPL-2.0 */

This one conforms.

> +
> +#ifndef __ASMARM_ARCH_CNTVOFF_H
> +#define __ASMARM_ARCH_CNTVOFF_H
> +
> +extern void secure_cntvoff_init(void);
> +
> +#endif
> --
> 2.11.0
>

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