Add the documentation for the Device Tree binding for the layerscape PCIe
controller with EP mode.
Signed-off-by: Xiaowei Bao <[email protected]>
Reviewed-by: Minghuan Lian <[email protected]>
Reviewed-by: Zhiqiang Hou <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
v2:
- Add the SoC specific compatibles.
v3:
- modify the commit message.
v4:
- no change.
v5:
- no change.
v6:
- no change.
.../devicetree/bindings/pci/layerscape-pci.txt | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
index 9b2b8d6..e20ceaa 100644
--- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
+++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
@@ -13,6 +13,7 @@ information.
Required properties:
- compatible: should contain the platform identifier such as:
+ RC mode:
"fsl,ls1021a-pcie"
"fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
"fsl,ls2088a-pcie"
@@ -20,6 +21,8 @@ Required properties:
"fsl,ls1046a-pcie"
"fsl,ls1043a-pcie"
"fsl,ls1012a-pcie"
+ EP mode:
+ "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"
- reg: base addresses and lengths of the PCIe controller register blocks.
- interrupts: A list of interrupt outputs of the controller. Must contain an
entry for each entry in the interrupt-names property.
--
1.7.1
Add the layerscape EP device support in pci_endpoint_test driver.
Signed-off-by: Xiaowei Bao <[email protected]>
Reviewed-by: Minghuan Lian <[email protected]>
Reviewed-by: Zhiqiang Hou <[email protected]>
Reviewed-by: Greg KH <[email protected]>
---
v2:
- no change
v3:
- no change
v4:
- delate the comments.
v5:
- no change.
v6:
- no change.
drivers/misc/pci_endpoint_test.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c
index 896e2df..29582fe 100644
--- a/drivers/misc/pci_endpoint_test.c
+++ b/drivers/misc/pci_endpoint_test.c
@@ -788,6 +788,7 @@ static void pci_endpoint_test_remove(struct pci_dev *pdev)
static const struct pci_device_id pci_endpoint_test_tbl[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA74x) },
{ PCI_DEVICE(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_DRA72x) },
+ { PCI_DEVICE(PCI_VENDOR_ID_FREESCALE, 0x81c0) },
{ PCI_DEVICE(PCI_VENDOR_ID_SYNOPSYS, 0xedda) },
{ }
};
--
1.7.1
Add the PCIe EP mode support for layerscape platform.
Signed-off-by: Xiaowei Bao <[email protected]>
Reviewed-by: Minghuan Lian <[email protected]>
Reviewed-by: Zhiqiang Hou <[email protected]>
Reviewed-by: Kishon Vijay Abraham I <[email protected]>
---
depends on: https://patchwork.kernel.org/project/linux-pci/list/?series=66177
v2:
- remove the EP mode check function.
v3:
- modif the return value when enter default case.
v4:
- no change.
v5:
- no change.
v6:
- modify the code base on the submit patch of the EP framework.
drivers/pci/controller/dwc/Makefile | 2 +-
drivers/pci/controller/dwc/pci-layerscape-ep.c | 157 ++++++++++++++++++++++++
2 files changed, 158 insertions(+), 1 deletions(-)
create mode 100644 drivers/pci/controller/dwc/pci-layerscape-ep.c
diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
index 7bcdcdf..b5f3b83 100644
--- a/drivers/pci/controller/dwc/Makefile
+++ b/drivers/pci/controller/dwc/Makefile
@@ -8,7 +8,7 @@ obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o
-obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
+obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o pci-layerscape-ep.o
obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
new file mode 100644
index 0000000..ddc2dbb
--- /dev/null
+++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * PCIe controller EP driver for Freescale Layerscape SoCs
+ *
+ * Copyright (C) 2018 NXP Semiconductor.
+ *
+ * Author: Xiaowei Bao <[email protected]>
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/of_pci.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/pci.h>
+#include <linux/platform_device.h>
+#include <linux/resource.h>
+
+#include "pcie-designware.h"
+
+#define PCIE_DBI2_OFFSET 0x1000 /* DBI2 base address*/
+
+struct ls_pcie_ep {
+ struct dw_pcie *pci;
+};
+
+#define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
+
+static int ls_pcie_establish_link(struct dw_pcie *pci)
+{
+ return 0;
+}
+
+static const struct dw_pcie_ops ls_pcie_ep_ops = {
+ .start_link = ls_pcie_establish_link,
+};
+
+static const struct of_device_id ls_pcie_ep_of_match[] = {
+ { .compatible = "fsl,ls-pcie-ep",},
+ { },
+};
+
+static const struct pci_epc_features ls_pcie_epc_features = {
+ .linkup_notifier = false,
+ .msi_capable = true,
+ .msix_capable = false,
+};
+
+static const struct pci_epc_features*
+ls_pcie_ep_get_features(struct dw_pcie_ep *ep)
+{
+ return &ls_pcie_epc_features;
+}
+
+static void ls_pcie_ep_init(struct dw_pcie_ep *ep)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+ struct pci_epc *epc = ep->epc;
+ enum pci_barno bar;
+
+ for (bar = BAR_0; bar <= BAR_5; bar++)
+ dw_pcie_ep_reset_bar(pci, bar);
+}
+
+static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
+ enum pci_epc_irq_type type, u16 interrupt_num)
+{
+ struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+
+ switch (type) {
+ case PCI_EPC_IRQ_LEGACY:
+ return dw_pcie_ep_raise_legacy_irq(ep, func_no);
+ case PCI_EPC_IRQ_MSI:
+ return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
+ case PCI_EPC_IRQ_MSIX:
+ return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
+ default:
+ dev_err(pci->dev, "UNKNOWN IRQ type\n");
+ return -EINVAL;
+ }
+}
+
+static struct dw_pcie_ep_ops pcie_ep_ops = {
+ .ep_init = ls_pcie_ep_init,
+ .raise_irq = ls_pcie_ep_raise_irq,
+ .get_features = ls_pcie_ep_get_features,
+};
+
+static int __init ls_add_pcie_ep(struct ls_pcie_ep *pcie,
+ struct platform_device *pdev)
+{
+ struct dw_pcie *pci = pcie->pci;
+ struct device *dev = pci->dev;
+ struct dw_pcie_ep *ep;
+ struct resource *res;
+ int ret;
+
+ ep = &pci->ep;
+ ep->ops = &pcie_ep_ops;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
+ if (!res)
+ return -EINVAL;
+
+ ep->phys_base = res->start;
+ ep->addr_size = resource_size(res);
+
+ ret = dw_pcie_ep_init(ep);
+ if (ret) {
+ dev_err(dev, "failed to initialize endpoint\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static int __init ls_pcie_ep_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct dw_pcie *pci;
+ struct ls_pcie_ep *pcie;
+ struct resource *dbi_base;
+ int ret;
+
+ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
+ if (!pcie)
+ return -ENOMEM;
+
+ pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
+ if (!pci)
+ return -ENOMEM;
+
+ dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
+ pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
+ if (IS_ERR(pci->dbi_base))
+ return PTR_ERR(pci->dbi_base);
+
+ pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_OFFSET;
+ pci->dev = dev;
+ pci->ops = &ls_pcie_ep_ops;
+ pcie->pci = pci;
+
+ platform_set_drvdata(pdev, pcie);
+
+ ret = ls_add_pcie_ep(pcie, pdev);
+
+ return ret;
+}
+
+static struct platform_driver ls_pcie_ep_driver = {
+ .driver = {
+ .name = "layerscape-pcie-ep",
+ .of_match_table = ls_pcie_ep_of_match,
+ .suppress_bind_attrs = true,
+ },
+};
+builtin_platform_driver_probe(ls_pcie_ep_driver, ls_pcie_ep_probe);
--
1.7.1
Add the PCIE EP node in dts for ls1046a.
Signed-off-by: Xiaowei Bao <[email protected]>
Reviewed-by: Minghuan Lian <[email protected]>
Reviewed-by: Zhiqiang Hou <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
v2:
- Add the SoC specific compatibles.
v3:
- no change
v4:
- no change
v5:
- change the OB win number due to the RM update.
v6:
- no change
arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 34 +++++++++++++++++++++++-
1 files changed, 33 insertions(+), 1 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 0e762ca..cb71850 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -666,6 +666,17 @@
status = "disabled";
};
+ pcie_ep@3400000 {
+ compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
+ reg = <0x00 0x03400000 0x0 0x00100000
+ 0x40 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <8>;
+ num-lanes = <2>;
+ status = "disabled";
+ };
+
pcie@3500000 {
compatible = "fsl,ls1046a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */
@@ -693,6 +704,17 @@
status = "disabled";
};
+ pcie_ep@3500000 {
+ compatible = "fsl,ls1046a-pcie-ep","fsl,ls-pcie-ep";
+ reg = <0x00 0x03500000 0x0 0x00100000
+ 0x48 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <8>;
+ num-lanes = <2>;
+ status = "disabled";
+ };
+
pcie@3600000 {
compatible = "fsl,ls1046a-pcie";
reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */
@@ -720,6 +742,17 @@
status = "disabled";
};
+ pcie_ep@3600000 {
+ compatible = "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep";
+ reg = <0x00 0x03600000 0x0 0x00100000
+ 0x50 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ num-ib-windows = <6>;
+ num-ob-windows = <8>;
+ num-lanes = <2>;
+ status = "disabled";
+ };
+
qdma: dma-controller@8380000 {
compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma";
reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */
@@ -740,7 +773,6 @@
queue-sizes = <64 64>;
big-endian;
};
-
};
reserved-memory {
--
1.7.1
On Tue, Jan 22, 2019 at 02:33:25PM +0800, Xiaowei Bao wrote:
> Add the documentation for the Device Tree binding for the layerscape PCIe
> controller with EP mode.
>
> Signed-off-by: Xiaowei Bao <[email protected]>
> Reviewed-by: Minghuan Lian <[email protected]>
> Reviewed-by: Zhiqiang Hou <[email protected]>
> Reviewed-by: Rob Herring <[email protected]>
> ---
> v2:
> - Add the SoC specific compatibles.
> v3:
> - modify the commit message.
> v4:
> - no change.
> v5:
> - no change.
> v6:
> - no change.
>
> .../devicetree/bindings/pci/layerscape-pci.txt | 3 +++
> 1 files changed, 3 insertions(+), 0 deletions(-)
Applied the series to pci/layerscape for v5.1, thanks.
Lorenzo
> diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> index 9b2b8d6..e20ceaa 100644
> --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> @@ -13,6 +13,7 @@ information.
>
> Required properties:
> - compatible: should contain the platform identifier such as:
> + RC mode:
> "fsl,ls1021a-pcie"
> "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
> "fsl,ls2088a-pcie"
> @@ -20,6 +21,8 @@ Required properties:
> "fsl,ls1046a-pcie"
> "fsl,ls1043a-pcie"
> "fsl,ls1012a-pcie"
> + EP mode:
> + "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"
> - reg: base addresses and lengths of the PCIe controller register blocks.
> - interrupts: A list of interrupt outputs of the controller. Must contain an
> entry for each entry in the interrupt-names property.
> --
> 1.7.1
>
-----Original Message-----
From: Lorenzo Pieralisi <[email protected]>
Sent: 2019??2??6?? 2:03
To: Xiaowei Bao <[email protected]>
Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leo Li <[email protected]>; [email protected]; [email protected]; [email protected]; M.h. Lian <[email protected]>; Mingkai Hu <[email protected]>; Roy Zang <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]
Subject: Re: [PATCHv6 1/4] dt-bindings: add DT binding for the layerscape PCIe controller with EP mode
On Tue, Jan 22, 2019 at 02:33:25PM +0800, Xiaowei Bao wrote:
> Add the documentation for the Device Tree binding for the layerscape
> PCIe controller with EP mode.
>
> Signed-off-by: Xiaowei Bao <[email protected]>
> Reviewed-by: Minghuan Lian <[email protected]>
> Reviewed-by: Zhiqiang Hou <[email protected]>
> Reviewed-by: Rob Herring <[email protected]>
> ---
> v2:
> - Add the SoC specific compatibles.
> v3:
> - modify the commit message.
> v4:
> - no change.
> v5:
> - no change.
> v6:
> - no change.
>
> .../devicetree/bindings/pci/layerscape-pci.txt | 3 +++
> 1 files changed, 3 insertions(+), 0 deletions(-)
Applied the series to pci/layerscape for v5.1, thanks.
[Xiaowei Bao] Hi Lorenzo, thank a lot.
Lorenzo
> diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> index 9b2b8d6..e20ceaa 100644
> --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> @@ -13,6 +13,7 @@ information.
>
> Required properties:
> - compatible: should contain the platform identifier such as:
> + RC mode:
> "fsl,ls1021a-pcie"
> "fsl,ls2080a-pcie", "fsl,ls2085a-pcie"
> "fsl,ls2088a-pcie"
> @@ -20,6 +21,8 @@ Required properties:
> "fsl,ls1046a-pcie"
> "fsl,ls1043a-pcie"
> "fsl,ls1012a-pcie"
> + EP mode:
> + "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"
> - reg: base addresses and lengths of the PCIe controller register blocks.
> - interrupts: A list of interrupt outputs of the controller. Must contain an
> entry for each entry in the interrupt-names property.
> --
> 1.7.1
>
On Tue, Jan 22, 2019 at 02:33:27PM +0800, Xiaowei Bao wrote:
> Add the PCIe EP mode support for layerscape platform.
>
> Signed-off-by: Xiaowei Bao <[email protected]>
> Reviewed-by: Minghuan Lian <[email protected]>
> Reviewed-by: Zhiqiang Hou <[email protected]>
> Reviewed-by: Kishon Vijay Abraham I <[email protected]>
> ---
> depends on: https://patchwork.kernel.org/project/linux-pci/list/?series=66177
>
> v2:
> - remove the EP mode check function.
> v3:
> - modif the return value when enter default case.
> v4:
> - no change.
> v5:
> - no change.
> v6:
> - modify the code base on the submit patch of the EP framework.
Can I apply this series to my pci/endpoint branch (where I queued
Kishon's EP features rework patches) ? Can you check please ?
Thanks,
Lorenzo
> drivers/pci/controller/dwc/Makefile | 2 +-
> drivers/pci/controller/dwc/pci-layerscape-ep.c | 157 ++++++++++++++++++++++++
> 2 files changed, 158 insertions(+), 1 deletions(-)
> create mode 100644 drivers/pci/controller/dwc/pci-layerscape-ep.c
>
> diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile
> index 7bcdcdf..b5f3b83 100644
> --- a/drivers/pci/controller/dwc/Makefile
> +++ b/drivers/pci/controller/dwc/Makefile
> @@ -8,7 +8,7 @@ obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
> obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
> obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
> obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o
> -obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
> +obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o pci-layerscape-ep.o
> obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
> obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
> obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
> diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> new file mode 100644
> index 0000000..ddc2dbb
> --- /dev/null
> +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> @@ -0,0 +1,157 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * PCIe controller EP driver for Freescale Layerscape SoCs
> + *
> + * Copyright (C) 2018 NXP Semiconductor.
> + *
> + * Author: Xiaowei Bao <[email protected]>
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/of_pci.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_address.h>
> +#include <linux/pci.h>
> +#include <linux/platform_device.h>
> +#include <linux/resource.h>
> +
> +#include "pcie-designware.h"
> +
> +#define PCIE_DBI2_OFFSET 0x1000 /* DBI2 base address*/
> +
> +struct ls_pcie_ep {
> + struct dw_pcie *pci;
> +};
> +
> +#define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
> +
> +static int ls_pcie_establish_link(struct dw_pcie *pci)
> +{
> + return 0;
> +}
> +
> +static const struct dw_pcie_ops ls_pcie_ep_ops = {
> + .start_link = ls_pcie_establish_link,
> +};
> +
> +static const struct of_device_id ls_pcie_ep_of_match[] = {
> + { .compatible = "fsl,ls-pcie-ep",},
> + { },
> +};
> +
> +static const struct pci_epc_features ls_pcie_epc_features = {
> + .linkup_notifier = false,
> + .msi_capable = true,
> + .msix_capable = false,
> +};
> +
> +static const struct pci_epc_features*
> +ls_pcie_ep_get_features(struct dw_pcie_ep *ep)
> +{
> + return &ls_pcie_epc_features;
> +}
> +
> +static void ls_pcie_ep_init(struct dw_pcie_ep *ep)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> + struct pci_epc *epc = ep->epc;
> + enum pci_barno bar;
> +
> + for (bar = BAR_0; bar <= BAR_5; bar++)
> + dw_pcie_ep_reset_bar(pci, bar);
> +}
> +
> +static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> + enum pci_epc_irq_type type, u16 interrupt_num)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> +
> + switch (type) {
> + case PCI_EPC_IRQ_LEGACY:
> + return dw_pcie_ep_raise_legacy_irq(ep, func_no);
> + case PCI_EPC_IRQ_MSI:
> + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> + case PCI_EPC_IRQ_MSIX:
> + return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
> + default:
> + dev_err(pci->dev, "UNKNOWN IRQ type\n");
> + return -EINVAL;
> + }
> +}
> +
> +static struct dw_pcie_ep_ops pcie_ep_ops = {
> + .ep_init = ls_pcie_ep_init,
> + .raise_irq = ls_pcie_ep_raise_irq,
> + .get_features = ls_pcie_ep_get_features,
> +};
> +
> +static int __init ls_add_pcie_ep(struct ls_pcie_ep *pcie,
> + struct platform_device *pdev)
> +{
> + struct dw_pcie *pci = pcie->pci;
> + struct device *dev = pci->dev;
> + struct dw_pcie_ep *ep;
> + struct resource *res;
> + int ret;
> +
> + ep = &pci->ep;
> + ep->ops = &pcie_ep_ops;
> +
> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
> + if (!res)
> + return -EINVAL;
> +
> + ep->phys_base = res->start;
> + ep->addr_size = resource_size(res);
> +
> + ret = dw_pcie_ep_init(ep);
> + if (ret) {
> + dev_err(dev, "failed to initialize endpoint\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int __init ls_pcie_ep_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct dw_pcie *pci;
> + struct ls_pcie_ep *pcie;
> + struct resource *dbi_base;
> + int ret;
> +
> + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
> + if (!pcie)
> + return -ENOMEM;
> +
> + pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
> + if (!pci)
> + return -ENOMEM;
> +
> + dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
> + pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
> + if (IS_ERR(pci->dbi_base))
> + return PTR_ERR(pci->dbi_base);
> +
> + pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_OFFSET;
> + pci->dev = dev;
> + pci->ops = &ls_pcie_ep_ops;
> + pcie->pci = pci;
> +
> + platform_set_drvdata(pdev, pcie);
> +
> + ret = ls_add_pcie_ep(pcie, pdev);
> +
> + return ret;
> +}
> +
> +static struct platform_driver ls_pcie_ep_driver = {
> + .driver = {
> + .name = "layerscape-pcie-ep",
> + .of_match_table = ls_pcie_ep_of_match,
> + .suppress_bind_attrs = true,
> + },
> +};
> +builtin_platform_driver_probe(ls_pcie_ep_driver, ls_pcie_ep_probe);
> --
> 1.7.1
>
-----Original Message-----
From: Lorenzo Pieralisi <[email protected]>
Sent: 2019??2??19?? 19:27
To: Xiaowei Bao <[email protected]>
Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leo Li <[email protected]>; [email protected]; [email protected]; [email protected]; M.h. Lian <[email protected]>; Mingkai Hu <[email protected]>; Roy Zang <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]
Subject: Re: [PATCHv6 3/4] pci: layerscape: Add the EP mode support.
On Tue, Jan 22, 2019 at 02:33:27PM +0800, Xiaowei Bao wrote:
> Add the PCIe EP mode support for layerscape platform.
>
> Signed-off-by: Xiaowei Bao <[email protected]>
> Reviewed-by: Minghuan Lian <[email protected]>
> Reviewed-by: Zhiqiang Hou <[email protected]>
> Reviewed-by: Kishon Vijay Abraham I <[email protected]>
> ---
> depends on:
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat
> chwork.kernel.org%2Fproject%2Flinux-pci%2Flist%2F%3Fseries%3D66177&
> ;data=02%7C01%7Cxiaowei.bao%40nxp.com%7C6f8772ba47c74d8ee0aa08d6965d3e
> b4%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636861724572611193&
> ;sdata=b3Acj0fu7c9vSoHe9VzeAkEMbMkpyfYPsXtf6fA8Flk%3D&reserved=0
>
> v2:
> - remove the EP mode check function.
> v3:
> - modif the return value when enter default case.
> v4:
> - no change.
> v5:
> - no change.
> v6:
> - modify the code base on the submit patch of the EP framework.
Can I apply this series to my pci/endpoint branch (where I queued Kishon's EP features rework patches) ? Can you check please ?
[Xiaowei Bao] of course, in my patch, I found a compile warning, but this series patch have approved by you, I don't know how to do, the compile warning: " struct pci_epc *epc = ep->epc;" in "ls_pcie_ep_init" function, I am so sorry, could you help me remove this code, thanks a lot.
Thanks,
Lorenzo
> drivers/pci/controller/dwc/Makefile | 2 +-
> drivers/pci/controller/dwc/pci-layerscape-ep.c | 157
> ++++++++++++++++++++++++
> 2 files changed, 158 insertions(+), 1 deletions(-) create mode
> 100644 drivers/pci/controller/dwc/pci-layerscape-ep.c
>
> diff --git a/drivers/pci/controller/dwc/Makefile
> b/drivers/pci/controller/dwc/Makefile
> index 7bcdcdf..b5f3b83 100644
> --- a/drivers/pci/controller/dwc/Makefile
> +++ b/drivers/pci/controller/dwc/Makefile
> @@ -8,7 +8,7 @@ obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
> obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
> obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
> obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o
> -obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
> +obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o pci-layerscape-ep.o
> obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
> obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
> obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o diff --git
> a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> new file mode 100644
> index 0000000..ddc2dbb
> --- /dev/null
> +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> @@ -0,0 +1,157 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * PCIe controller EP driver for Freescale Layerscape SoCs
> + *
> + * Copyright (C) 2018 NXP Semiconductor.
> + *
> + * Author: Xiaowei Bao <[email protected]> */
> +
> +#include <linux/kernel.h>
> +#include <linux/init.h>
> +#include <linux/of_pci.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_address.h>
> +#include <linux/pci.h>
> +#include <linux/platform_device.h>
> +#include <linux/resource.h>
> +
> +#include "pcie-designware.h"
> +
> +#define PCIE_DBI2_OFFSET 0x1000 /* DBI2 base address*/
> +
> +struct ls_pcie_ep {
> + struct dw_pcie *pci;
> +};
> +
> +#define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
> +
> +static int ls_pcie_establish_link(struct dw_pcie *pci) {
> + return 0;
> +}
> +
> +static const struct dw_pcie_ops ls_pcie_ep_ops = {
> + .start_link = ls_pcie_establish_link, };
> +
> +static const struct of_device_id ls_pcie_ep_of_match[] = {
> + { .compatible = "fsl,ls-pcie-ep",},
> + { },
> +};
> +
> +static const struct pci_epc_features ls_pcie_epc_features = {
> + .linkup_notifier = false,
> + .msi_capable = true,
> + .msix_capable = false,
> +};
> +
> +static const struct pci_epc_features* ls_pcie_ep_get_features(struct
> +dw_pcie_ep *ep) {
> + return &ls_pcie_epc_features;
> +}
> +
> +static void ls_pcie_ep_init(struct dw_pcie_ep *ep) {
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> + struct pci_epc *epc = ep->epc;
> + enum pci_barno bar;
> +
> + for (bar = BAR_0; bar <= BAR_5; bar++)
> + dw_pcie_ep_reset_bar(pci, bar);
> +}
> +
> +static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> + enum pci_epc_irq_type type, u16 interrupt_num) {
> + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> +
> + switch (type) {
> + case PCI_EPC_IRQ_LEGACY:
> + return dw_pcie_ep_raise_legacy_irq(ep, func_no);
> + case PCI_EPC_IRQ_MSI:
> + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> + case PCI_EPC_IRQ_MSIX:
> + return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
> + default:
> + dev_err(pci->dev, "UNKNOWN IRQ type\n");
> + return -EINVAL;
> + }
> +}
> +
> +static struct dw_pcie_ep_ops pcie_ep_ops = {
> + .ep_init = ls_pcie_ep_init,
> + .raise_irq = ls_pcie_ep_raise_irq,
> + .get_features = ls_pcie_ep_get_features, };
> +
> +static int __init ls_add_pcie_ep(struct ls_pcie_ep *pcie,
> + struct platform_device *pdev)
> +{
> + struct dw_pcie *pci = pcie->pci;
> + struct device *dev = pci->dev;
> + struct dw_pcie_ep *ep;
> + struct resource *res;
> + int ret;
> +
> + ep = &pci->ep;
> + ep->ops = &pcie_ep_ops;
> +
> + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
> + if (!res)
> + return -EINVAL;
> +
> + ep->phys_base = res->start;
> + ep->addr_size = resource_size(res);
> +
> + ret = dw_pcie_ep_init(ep);
> + if (ret) {
> + dev_err(dev, "failed to initialize endpoint\n");
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int __init ls_pcie_ep_probe(struct platform_device *pdev) {
> + struct device *dev = &pdev->dev;
> + struct dw_pcie *pci;
> + struct ls_pcie_ep *pcie;
> + struct resource *dbi_base;
> + int ret;
> +
> + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
> + if (!pcie)
> + return -ENOMEM;
> +
> + pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
> + if (!pci)
> + return -ENOMEM;
> +
> + dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
> + pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
> + if (IS_ERR(pci->dbi_base))
> + return PTR_ERR(pci->dbi_base);
> +
> + pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_OFFSET;
> + pci->dev = dev;
> + pci->ops = &ls_pcie_ep_ops;
> + pcie->pci = pci;
> +
> + platform_set_drvdata(pdev, pcie);
> +
> + ret = ls_add_pcie_ep(pcie, pdev);
> +
> + return ret;
> +}
> +
> +static struct platform_driver ls_pcie_ep_driver = {
> + .driver = {
> + .name = "layerscape-pcie-ep",
> + .of_match_table = ls_pcie_ep_of_match,
> + .suppress_bind_attrs = true,
> + },
> +};
> +builtin_platform_driver_probe(ls_pcie_ep_driver, ls_pcie_ep_probe);
> --
> 1.7.1
>
On Wed, Feb 20, 2019 at 03:09:01AM +0000, Xiaowei Bao wrote:
>
>
> -----Original Message-----
> From: Lorenzo Pieralisi <[email protected]>
> Sent: 2019年2月19日 19:27
> To: Xiaowei Bao <[email protected]>
> Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leo Li <[email protected]>; [email protected]; [email protected]; [email protected]; M.h. Lian <[email protected]>; Mingkai Hu <[email protected]>; Roy Zang <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]
> Subject: Re: [PATCHv6 3/4] pci: layerscape: Add the EP mode support.
>
> On Tue, Jan 22, 2019 at 02:33:27PM +0800, Xiaowei Bao wrote:
> > Add the PCIe EP mode support for layerscape platform.
> >
> > Signed-off-by: Xiaowei Bao <[email protected]>
> > Reviewed-by: Minghuan Lian <[email protected]>
> > Reviewed-by: Zhiqiang Hou <[email protected]>
> > Reviewed-by: Kishon Vijay Abraham I <[email protected]>
> > ---
> > depends on:
> > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpat
> > chwork.kernel.org%2Fproject%2Flinux-pci%2Flist%2F%3Fseries%3D66177&
> > ;data=02%7C01%7Cxiaowei.bao%40nxp.com%7C6f8772ba47c74d8ee0aa08d6965d3e
> > b4%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636861724572611193&
> > ;sdata=b3Acj0fu7c9vSoHe9VzeAkEMbMkpyfYPsXtf6fA8Flk%3D&reserved=0
> >
> > v2:
> > - remove the EP mode check function.
> > v3:
> > - modif the return value when enter default case.
> > v4:
> > - no change.
> > v5:
> > - no change.
> > v6:
> > - modify the code base on the submit patch of the EP framework.
>
> Can I apply this series to my pci/endpoint branch (where I queued Kishon's EP features rework patches) ? Can you check please ?
> [Xiaowei Bao] of course, in my patch, I found a compile warning, but
> this series patch have approved by you, I don't know how to do, the
> compile warning: " struct pci_epc *epc = ep->epc;" in
> "ls_pcie_ep_init" function, I am so sorry, could you help me remove
> this code, thanks a lot.
If you want me to apply your patches you need to rebase them against
my pci/endpoint branch and make sure the code is correct, I have
applied your previous series but as you know it failed because it
depends on Kishon's clean-up series.
So rebase your code against my pci/endpoint branch, make sure it
compiles with no warnings, test it and send a v7.
Thanks,
Lorenzo
> Thanks,
> Lorenzo
>
> > drivers/pci/controller/dwc/Makefile | 2 +-
> > drivers/pci/controller/dwc/pci-layerscape-ep.c | 157
> > ++++++++++++++++++++++++
> > 2 files changed, 158 insertions(+), 1 deletions(-) create mode
> > 100644 drivers/pci/controller/dwc/pci-layerscape-ep.c
> >
> > diff --git a/drivers/pci/controller/dwc/Makefile
> > b/drivers/pci/controller/dwc/Makefile
> > index 7bcdcdf..b5f3b83 100644
> > --- a/drivers/pci/controller/dwc/Makefile
> > +++ b/drivers/pci/controller/dwc/Makefile
> > @@ -8,7 +8,7 @@ obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
> > obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
> > obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
> > obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o
> > -obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
> > +obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o pci-layerscape-ep.o
> > obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
> > obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
> > obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o diff --git
> > a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > new file mode 100644
> > index 0000000..ddc2dbb
> > --- /dev/null
> > +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > @@ -0,0 +1,157 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * PCIe controller EP driver for Freescale Layerscape SoCs
> > + *
> > + * Copyright (C) 2018 NXP Semiconductor.
> > + *
> > + * Author: Xiaowei Bao <[email protected]> */
> > +
> > +#include <linux/kernel.h>
> > +#include <linux/init.h>
> > +#include <linux/of_pci.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/of_address.h>
> > +#include <linux/pci.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/resource.h>
> > +
> > +#include "pcie-designware.h"
> > +
> > +#define PCIE_DBI2_OFFSET 0x1000 /* DBI2 base address*/
> > +
> > +struct ls_pcie_ep {
> > + struct dw_pcie *pci;
> > +};
> > +
> > +#define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
> > +
> > +static int ls_pcie_establish_link(struct dw_pcie *pci) {
> > + return 0;
> > +}
> > +
> > +static const struct dw_pcie_ops ls_pcie_ep_ops = {
> > + .start_link = ls_pcie_establish_link, };
> > +
> > +static const struct of_device_id ls_pcie_ep_of_match[] = {
> > + { .compatible = "fsl,ls-pcie-ep",},
> > + { },
> > +};
> > +
> > +static const struct pci_epc_features ls_pcie_epc_features = {
> > + .linkup_notifier = false,
> > + .msi_capable = true,
> > + .msix_capable = false,
> > +};
> > +
> > +static const struct pci_epc_features* ls_pcie_ep_get_features(struct
> > +dw_pcie_ep *ep) {
> > + return &ls_pcie_epc_features;
> > +}
> > +
> > +static void ls_pcie_ep_init(struct dw_pcie_ep *ep) {
> > + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > + struct pci_epc *epc = ep->epc;
> > + enum pci_barno bar;
> > +
> > + for (bar = BAR_0; bar <= BAR_5; bar++)
> > + dw_pcie_ep_reset_bar(pci, bar);
> > +}
> > +
> > +static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > + enum pci_epc_irq_type type, u16 interrupt_num) {
> > + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > +
> > + switch (type) {
> > + case PCI_EPC_IRQ_LEGACY:
> > + return dw_pcie_ep_raise_legacy_irq(ep, func_no);
> > + case PCI_EPC_IRQ_MSI:
> > + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> > + case PCI_EPC_IRQ_MSIX:
> > + return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
> > + default:
> > + dev_err(pci->dev, "UNKNOWN IRQ type\n");
> > + return -EINVAL;
> > + }
> > +}
> > +
> > +static struct dw_pcie_ep_ops pcie_ep_ops = {
> > + .ep_init = ls_pcie_ep_init,
> > + .raise_irq = ls_pcie_ep_raise_irq,
> > + .get_features = ls_pcie_ep_get_features, };
> > +
> > +static int __init ls_add_pcie_ep(struct ls_pcie_ep *pcie,
> > + struct platform_device *pdev)
> > +{
> > + struct dw_pcie *pci = pcie->pci;
> > + struct device *dev = pci->dev;
> > + struct dw_pcie_ep *ep;
> > + struct resource *res;
> > + int ret;
> > +
> > + ep = &pci->ep;
> > + ep->ops = &pcie_ep_ops;
> > +
> > + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
> > + if (!res)
> > + return -EINVAL;
> > +
> > + ep->phys_base = res->start;
> > + ep->addr_size = resource_size(res);
> > +
> > + ret = dw_pcie_ep_init(ep);
> > + if (ret) {
> > + dev_err(dev, "failed to initialize endpoint\n");
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int __init ls_pcie_ep_probe(struct platform_device *pdev) {
> > + struct device *dev = &pdev->dev;
> > + struct dw_pcie *pci;
> > + struct ls_pcie_ep *pcie;
> > + struct resource *dbi_base;
> > + int ret;
> > +
> > + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
> > + if (!pcie)
> > + return -ENOMEM;
> > +
> > + pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
> > + if (!pci)
> > + return -ENOMEM;
> > +
> > + dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
> > + pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
> > + if (IS_ERR(pci->dbi_base))
> > + return PTR_ERR(pci->dbi_base);
> > +
> > + pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_OFFSET;
> > + pci->dev = dev;
> > + pci->ops = &ls_pcie_ep_ops;
> > + pcie->pci = pci;
> > +
> > + platform_set_drvdata(pdev, pcie);
> > +
> > + ret = ls_add_pcie_ep(pcie, pdev);
> > +
> > + return ret;
> > +}
> > +
> > +static struct platform_driver ls_pcie_ep_driver = {
> > + .driver = {
> > + .name = "layerscape-pcie-ep",
> > + .of_match_table = ls_pcie_ep_of_match,
> > + .suppress_bind_attrs = true,
> > + },
> > +};
> > +builtin_platform_driver_probe(ls_pcie_ep_driver, ls_pcie_ep_probe);
> > --
> > 1.7.1
> >
-----Original Message-----
From: Lorenzo Pieralisi <[email protected]>
Sent: 2019年2月20日 18:06
To: Xiaowei Bao <[email protected]>
Cc: [email protected]; [email protected]; [email protected]; [email protected]; Leo Li <[email protected]>; [email protected]; [email protected]; [email protected]; M.h. Lian <[email protected]>; Mingkai Hu <[email protected]>; Roy Zang <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]
Subject: Re: [PATCHv6 3/4] pci: layerscape: Add the EP mode support.
On Wed, Feb 20, 2019 at 03:09:01AM +0000, Xiaowei Bao wrote:
>
>
> -----Original Message-----
> From: Lorenzo Pieralisi <[email protected]>
> Sent: 2019年2月19日 19:27
> To: Xiaowei Bao <[email protected]>
> Cc: [email protected]; [email protected]; [email protected];
> [email protected]; Leo Li <[email protected]>; [email protected];
> [email protected]; [email protected]; M.h. Lian
> <[email protected]>; Mingkai Hu <[email protected]>; Roy Zang
> <[email protected]>; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected];
> [email protected]; [email protected]
> Subject: Re: [PATCHv6 3/4] pci: layerscape: Add the EP mode support.
>
> On Tue, Jan 22, 2019 at 02:33:27PM +0800, Xiaowei Bao wrote:
> > Add the PCIe EP mode support for layerscape platform.
> >
> > Signed-off-by: Xiaowei Bao <[email protected]>
> > Reviewed-by: Minghuan Lian <[email protected]>
> > Reviewed-by: Zhiqiang Hou <[email protected]>
> > Reviewed-by: Kishon Vijay Abraham I <[email protected]>
> > ---
> > depends on:
> > https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fp
> > at
> > chwork.kernel.org%2Fproject%2Flinux-pci%2Flist%2F%3Fseries%3D66177&a
> > mp
> > ;data=02%7C01%7Cxiaowei.bao%40nxp.com%7C6f8772ba47c74d8ee0aa08d6965d
> > 3e
> > b4%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C0%7C636861724572611193&a
> > mp
> > ;sdata=b3Acj0fu7c9vSoHe9VzeAkEMbMkpyfYPsXtf6fA8Flk%3D&reserved=0
> >
> > v2:
> > - remove the EP mode check function.
> > v3:
> > - modif the return value when enter default case.
> > v4:
> > - no change.
> > v5:
> > - no change.
> > v6:
> > - modify the code base on the submit patch of the EP framework.
>
> Can I apply this series to my pci/endpoint branch (where I queued Kishon's EP features rework patches) ? Can you check please ?
> [Xiaowei Bao] of course, in my patch, I found a compile warning, but
> this series patch have approved by you, I don't know how to do, the
> compile warning: " struct pci_epc *epc = ep->epc;" in
> "ls_pcie_ep_init" function, I am so sorry, could you help me remove
> this code, thanks a lot.
If you want me to apply your patches you need to rebase them against my pci/endpoint branch and make sure the code is correct, I have applied your previous series but as you know it failed because it depends on Kishon's clean-up series.
So rebase your code against my pci/endpoint branch, make sure it compiles with no warnings, test it and send a v7.
[Xiaowei Bao] Hi Lorenzo, I have completed the test with my v7 patch in pci/endpoint branch, fix up the compile warning issue, I will send the v7 patch later. Thanks a lot.
Thanks,
Lorenzo
> Thanks,
> Lorenzo
>
> > drivers/pci/controller/dwc/Makefile | 2 +-
> > drivers/pci/controller/dwc/pci-layerscape-ep.c | 157
> > ++++++++++++++++++++++++
> > 2 files changed, 158 insertions(+), 1 deletions(-) create mode
> > 100644 drivers/pci/controller/dwc/pci-layerscape-ep.c
> >
> > diff --git a/drivers/pci/controller/dwc/Makefile
> > b/drivers/pci/controller/dwc/Makefile
> > index 7bcdcdf..b5f3b83 100644
> > --- a/drivers/pci/controller/dwc/Makefile
> > +++ b/drivers/pci/controller/dwc/Makefile
> > @@ -8,7 +8,7 @@ obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
> > obj-$(CONFIG_PCI_IMX6) += pci-imx6.o
> > obj-$(CONFIG_PCIE_SPEAR13XX) += pcie-spear13xx.o
> > obj-$(CONFIG_PCI_KEYSTONE) += pci-keystone.o
> > -obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
> > +obj-$(CONFIG_PCI_LAYERSCAPE) += pci-layerscape.o
> > +pci-layerscape-ep.o
> > obj-$(CONFIG_PCIE_QCOM) += pcie-qcom.o
> > obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
> > obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o diff --git
> > a/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > new file mode 100644
> > index 0000000..ddc2dbb
> > --- /dev/null
> > +++ b/drivers/pci/controller/dwc/pci-layerscape-ep.c
> > @@ -0,0 +1,157 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * PCIe controller EP driver for Freescale Layerscape SoCs
> > + *
> > + * Copyright (C) 2018 NXP Semiconductor.
> > + *
> > + * Author: Xiaowei Bao <[email protected]> */
> > +
> > +#include <linux/kernel.h>
> > +#include <linux/init.h>
> > +#include <linux/of_pci.h>
> > +#include <linux/of_platform.h>
> > +#include <linux/of_address.h>
> > +#include <linux/pci.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/resource.h>
> > +
> > +#include "pcie-designware.h"
> > +
> > +#define PCIE_DBI2_OFFSET 0x1000 /* DBI2 base address*/
> > +
> > +struct ls_pcie_ep {
> > + struct dw_pcie *pci;
> > +};
> > +
> > +#define to_ls_pcie_ep(x) dev_get_drvdata((x)->dev)
> > +
> > +static int ls_pcie_establish_link(struct dw_pcie *pci) {
> > + return 0;
> > +}
> > +
> > +static const struct dw_pcie_ops ls_pcie_ep_ops = {
> > + .start_link = ls_pcie_establish_link, };
> > +
> > +static const struct of_device_id ls_pcie_ep_of_match[] = {
> > + { .compatible = "fsl,ls-pcie-ep",},
> > + { },
> > +};
> > +
> > +static const struct pci_epc_features ls_pcie_epc_features = {
> > + .linkup_notifier = false,
> > + .msi_capable = true,
> > + .msix_capable = false,
> > +};
> > +
> > +static const struct pci_epc_features*
> > +ls_pcie_ep_get_features(struct dw_pcie_ep *ep) {
> > + return &ls_pcie_epc_features;
> > +}
> > +
> > +static void ls_pcie_ep_init(struct dw_pcie_ep *ep) {
> > + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > + struct pci_epc *epc = ep->epc;
> > + enum pci_barno bar;
> > +
> > + for (bar = BAR_0; bar <= BAR_5; bar++)
> > + dw_pcie_ep_reset_bar(pci, bar);
> > +}
> > +
> > +static int ls_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
> > + enum pci_epc_irq_type type, u16 interrupt_num) {
> > + struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
> > +
> > + switch (type) {
> > + case PCI_EPC_IRQ_LEGACY:
> > + return dw_pcie_ep_raise_legacy_irq(ep, func_no);
> > + case PCI_EPC_IRQ_MSI:
> > + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
> > + case PCI_EPC_IRQ_MSIX:
> > + return dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
> > + default:
> > + dev_err(pci->dev, "UNKNOWN IRQ type\n");
> > + return -EINVAL;
> > + }
> > +}
> > +
> > +static struct dw_pcie_ep_ops pcie_ep_ops = {
> > + .ep_init = ls_pcie_ep_init,
> > + .raise_irq = ls_pcie_ep_raise_irq,
> > + .get_features = ls_pcie_ep_get_features, };
> > +
> > +static int __init ls_add_pcie_ep(struct ls_pcie_ep *pcie,
> > + struct platform_device *pdev)
> > +{
> > + struct dw_pcie *pci = pcie->pci;
> > + struct device *dev = pci->dev;
> > + struct dw_pcie_ep *ep;
> > + struct resource *res;
> > + int ret;
> > +
> > + ep = &pci->ep;
> > + ep->ops = &pcie_ep_ops;
> > +
> > + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "addr_space");
> > + if (!res)
> > + return -EINVAL;
> > +
> > + ep->phys_base = res->start;
> > + ep->addr_size = resource_size(res);
> > +
> > + ret = dw_pcie_ep_init(ep);
> > + if (ret) {
> > + dev_err(dev, "failed to initialize endpoint\n");
> > + return ret;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int __init ls_pcie_ep_probe(struct platform_device *pdev) {
> > + struct device *dev = &pdev->dev;
> > + struct dw_pcie *pci;
> > + struct ls_pcie_ep *pcie;
> > + struct resource *dbi_base;
> > + int ret;
> > +
> > + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
> > + if (!pcie)
> > + return -ENOMEM;
> > +
> > + pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
> > + if (!pci)
> > + return -ENOMEM;
> > +
> > + dbi_base = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
> > + pci->dbi_base = devm_pci_remap_cfg_resource(dev, dbi_base);
> > + if (IS_ERR(pci->dbi_base))
> > + return PTR_ERR(pci->dbi_base);
> > +
> > + pci->dbi_base2 = pci->dbi_base + PCIE_DBI2_OFFSET;
> > + pci->dev = dev;
> > + pci->ops = &ls_pcie_ep_ops;
> > + pcie->pci = pci;
> > +
> > + platform_set_drvdata(pdev, pcie);
> > +
> > + ret = ls_add_pcie_ep(pcie, pdev);
> > +
> > + return ret;
> > +}
> > +
> > +static struct platform_driver ls_pcie_ep_driver = {
> > + .driver = {
> > + .name = "layerscape-pcie-ep",
> > + .of_match_table = ls_pcie_ep_of_match,
> > + .suppress_bind_attrs = true,
> > + },
> > +};
> > +builtin_platform_driver_probe(ls_pcie_ep_driver, ls_pcie_ep_probe);
> > --
> > 1.7.1
> >