On the Amlogic G12A SoC family, (only) the SDIO controller fails to access
the data from DDR, leading to a broken controller.
Add the amlogic,ddr-access-quirk property so signal this particular
controller has this bug and needs a quirk to work properly.
But each MMC controller has 1,5KiB of SRAM after the registers, that can
be used as bounce buffer to avoid direct DDR access from the integrated
DMAs (this SRAM may be used by the boot ROM when DDR is not yet initialized).
The quirk is to disable the chained descriptor for this controller, and
use this SRAM memory zone as buffer for the bounce buffer fallback mode.
The performance hit hasn't been evaluated, but the fix has been tested
using a WiFi AP6398S SDIO module, and the iperf3 Bandwidth measurement gave
55.2 Mbits/sec over a 63 Hours long test, with the SDIO ios set as High-Speed
at 50MHz clock. It gave around 170 Mbits/sec as SDR104 and 200MHz clock.
Neil Armstrong (3):
dt-bindings: mmc: meson-gx: add ddr-access-quirk property
mmc: meson-gx: add ddr-access-quirk
arm64: dts: meson-g12a: add ddr-access-quirk property to SDIO
controller
.../bindings/mmc/amlogic,meson-gx.txt | 4 ++
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 1 +
drivers/mmc/host/meson-gx-mmc.c | 65 +++++++++++++++----
3 files changed, 57 insertions(+), 13 deletions(-)
--
2.21.0
On the Amlogic G12A SoC family, (only) the SDIO controller has a bug which
makes any DDR access from the MMC controller fail.
Add the amlogic,ddr-access-quirk property so signal this particular
controller has this bug and needs a quirk to work properly.
Signed-off-by: Neil Armstrong <[email protected]>
---
Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
index 13e70409e8ac..f8914dab06c6 100644
--- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
+++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
@@ -22,6 +22,10 @@ Required properties:
clock rate requested by the MMC core.
- resets : phandle of the internal reset line
+Optional properties:
+- amlogic,ddr-access-quirk: set when HW cannot access the DDR memory, like on
+ the G12A SDIO controller.
+
Example:
sd_emmc_a: mmc@70000 {
--
2.21.0
On the Amlogic G12A SoC family, (only) the SDIO controller fails to access
the data from DDR, leading to a broken controller.
But each MMC controller has 1,5KiB of SRAM after the registers, that can
be used as bounce buffer to avoid direct DDR access from the integrated
DMAs (this SRAM may be used by the boot ROM when DDR is not yet initialized).
The quirk is to disable the chained descriptor for this controller, and
use this SRAM memory zone as buffer for the bounce buffer fallback mode.
The performance hit hasn't been evaluated, but the fix has been tested
using a WiFi AP6398S SDIO module, and the iperf3 Bandwidth measurement gave
55.2 Mbits/sec over a 63 Hours long test, with the SDIO ios set as High-Speed
at 50MHz clock. It gave 170 Mbits/sec as SDR104 and 200MHz clock.
Signed-off-by: Neil Armstrong <[email protected]>
---
drivers/mmc/host/meson-gx-mmc.c | 65 ++++++++++++++++++++++++++-------
1 file changed, 52 insertions(+), 13 deletions(-)
diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
index c5a8af4ca76b..6ef465304052 100644
--- a/drivers/mmc/host/meson-gx-mmc.c
+++ b/drivers/mmc/host/meson-gx-mmc.c
@@ -129,6 +129,9 @@
#define SD_EMMC_TXD 0x94
#define SD_EMMC_LAST_REG SD_EMMC_TXD
+#define SD_EMMC_SRAM_DATA_BUF_LEN 1536
+#define SD_EMMC_SRAM_DATA_BUF_OFF 0x200
+
#define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */
#define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */
#define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */
@@ -168,6 +171,8 @@ struct meson_host {
unsigned long req_rate;
bool ddr;
+ bool ddr_access_quirk;
+
struct pinctrl *pinctrl;
struct pinctrl_state *pins_default;
struct pinctrl_state *pins_clk_gate;
@@ -232,11 +237,20 @@ static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd)
static void meson_mmc_get_transfer_mode(struct mmc_host *mmc,
struct mmc_request *mrq)
{
+ struct meson_host *host = mmc_priv(mmc);
struct mmc_data *data = mrq->data;
struct scatterlist *sg;
int i;
bool use_desc_chain_mode = true;
+ /*
+ * When Controller DMA cannot directly access DDR memory, disable
+ * support for Chain Mode to directly use the internal SRAM using
+ * the bounce buffer mode.
+ */
+ if (host->ddr_access_quirk)
+ return;
+
/*
* Broken SDIO with AP6255-based WiFi on Khadas VIM Pro has been
* reported. For some strange reason this occurs in descriptor
@@ -1049,6 +1063,10 @@ static int meson_mmc_probe(struct platform_device *pdev)
host->dev = &pdev->dev;
dev_set_drvdata(&pdev->dev, host);
+ /* The G12A SDIO Controller needs an SRAM bounce buffer */
+ host->ddr_access_quirk = device_property_read_bool(&pdev->dev,
+ "amlogic,ddr-access-quirk");
+
/* Get regulators and the supported OCR mask */
host->vqmmc_enabled = false;
ret = mmc_regulator_get_supply(mmc);
@@ -1146,9 +1164,16 @@ static int meson_mmc_probe(struct platform_device *pdev)
goto err_init_clk;
mmc->caps |= MMC_CAP_CMD23;
- mmc->max_blk_count = CMD_CFG_LENGTH_MASK;
+ if (host->ddr_access_quirk) {
+ /* Limit to the available sram memory */
+ mmc->max_segs = SD_EMMC_SRAM_DATA_BUF_LEN / mmc->max_blk_size;
+ mmc->max_blk_count = mmc->max_segs;
+ } else {
+ mmc->max_blk_count = CMD_CFG_LENGTH_MASK;
+ mmc->max_segs = SD_EMMC_DESC_BUF_LEN /
+ sizeof(struct sd_emmc_desc);
+ }
mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size;
- mmc->max_segs = SD_EMMC_DESC_BUF_LEN / sizeof(struct sd_emmc_desc);
mmc->max_seg_size = mmc->max_req_size;
/*
@@ -1158,15 +1183,27 @@ static int meson_mmc_probe(struct platform_device *pdev)
*/
mmc->caps2 &= ~MMC_CAP2_HS400;
- /* data bounce buffer */
- host->bounce_buf_size = mmc->max_req_size;
- host->bounce_buf =
- dma_alloc_coherent(host->dev, host->bounce_buf_size,
- &host->bounce_dma_addr, GFP_KERNEL);
- if (host->bounce_buf == NULL) {
- dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
- ret = -ENOMEM;
- goto err_free_irq;
+ if (host->ddr_access_quirk) {
+ /*
+ * The MMC Controller embeds 1,5KiB of internal SRAM
+ * that can be used to be used as bounce buffer.
+ * In the case of the G12A SDIO controller, use these
+ * instead of the DDR memory
+ */
+ host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN;
+ host->bounce_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF;
+ host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF;
+ } else {
+ /* data bounce buffer */
+ host->bounce_buf_size = mmc->max_req_size;
+ host->bounce_buf =
+ dma_alloc_coherent(host->dev, host->bounce_buf_size,
+ &host->bounce_dma_addr, GFP_KERNEL);
+ if (host->bounce_buf == NULL) {
+ dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
+ ret = -ENOMEM;
+ goto err_free_irq;
+ }
}
host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
@@ -1208,8 +1245,10 @@ static int meson_mmc_remove(struct platform_device *pdev)
dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
host->descs, host->descs_dma_addr);
- dma_free_coherent(host->dev, host->bounce_buf_size,
- host->bounce_buf, host->bounce_dma_addr);
+
+ if (!host->ddr_access_quirk)
+ dma_free_coherent(host->dev, host->bounce_buf_size,
+ host->bounce_buf, host->bounce_dma_addr);
clk_disable_unprepare(host->mmc_clk);
clk_disable_unprepare(host->core_clk);
--
2.21.0
On Mon, 2019-05-13 at 11:15 +0200, Neil Armstrong wrote:
> On the Amlogic G12A SoC family, (only) the SDIO controller fails to access
> the data from DDR, leading to a broken controller.
>
> Add the amlogic,ddr-access-quirk property so signal this particular
> controller has this bug and needs a quirk to work properly.
>
> But each MMC controller has 1,5KiB of SRAM after the registers, that can
> be used as bounce buffer to avoid direct DDR access from the integrated
> DMAs (this SRAM may be used by the boot ROM when DDR is not yet initialized).
>
> The quirk is to disable the chained descriptor for this controller, and
> use this SRAM memory zone as buffer for the bounce buffer fallback mode.
>
> The performance hit hasn't been evaluated, but the fix has been tested
> using a WiFi AP6398S SDIO module, and the iperf3 Bandwidth measurement gave
> 55.2 Mbits/sec over a 63 Hours long test, with the SDIO ios set as High-Speed
> at 50MHz clock. It gave around 170 Mbits/sec as SDR104 and 200MHz clock.
These numbers looks to be limited by the MMC bandwidth of the related modes.
So, if the SRAM quirk introduce a penalty for the controller, it does not appear
to be a limiting factor, AFAICT.
>
> Neil Armstrong (3):
> dt-bindings: mmc: meson-gx: add ddr-access-quirk property
> mmc: meson-gx: add ddr-access-quirk
> arm64: dts: meson-g12a: add ddr-access-quirk property to SDIO
> controller
>
> .../bindings/mmc/amlogic,meson-gx.txt | 4 ++
> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 1 +
> drivers/mmc/host/meson-gx-mmc.c | 65 +++++++++++++++----
> 3 files changed, 57 insertions(+), 13 deletions(-)
>
On Mon, 2019-05-13 at 11:58 +0200, Jerome Brunet wrote:
> > The performance hit hasn't been evaluated, but the fix has been tested
> > using a WiFi AP6398S SDIO module, and the iperf3 Bandwidth measurement gave
> > 55.2 Mbits/sec over a 63 Hours long test, with the SDIO ios set as High-Speed
> > at 50MHz clock. It gave around 170 Mbits/sec as SDR104 and 200MHz clock.
>
> These numbers looks to be limited by the MMC bandwidth of the related modes.
> So, if the SRAM quirk introduce a penalty for the controller, it does not appear
> to be a limiting factor, AFAICT.
Got confused. This comment is completely wrong, please ignore
Neil Armstrong <[email protected]> writes:
> On the Amlogic G12A SoC family, (only) the SDIO controller fails to access
> the data from DDR, leading to a broken controller.
>
> But each MMC controller has 1,5KiB of SRAM after the registers, that can
> be used as bounce buffer to avoid direct DDR access from the integrated
> DMAs (this SRAM may be used by the boot ROM when DDR is not yet initialized).
>
> The quirk is to disable the chained descriptor for this controller, and
> use this SRAM memory zone as buffer for the bounce buffer fallback mode.
>
> The performance hit hasn't been evaluated, but the fix has been tested
> using a WiFi AP6398S SDIO module, and the iperf3 Bandwidth measurement gave
> 55.2 Mbits/sec over a 63 Hours long test, with the SDIO ios set as High-Speed
> at 50MHz clock. It gave 170 Mbits/sec as SDR104 and 200MHz clock.
>
> Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Kevin Hilman <[email protected]>
On 5/13/19 11:15 AM, Neil Armstrong wrote:
> On the Amlogic G12A SoC family, (only) the SDIO controller fails to access
> the data from DDR, leading to a broken controller.
>
> Add the amlogic,ddr-access-quirk property so signal this particular
> controller has this bug and needs a quirk to work properly.
>
> But each MMC controller has 1,5KiB of SRAM after the registers, that can
> be used as bounce buffer to avoid direct DDR access from the integrated
> DMAs (this SRAM may be used by the boot ROM when DDR is not yet initialized).
>
> The quirk is to disable the chained descriptor for this controller, and
> use this SRAM memory zone as buffer for the bounce buffer fallback mode.
>
> The performance hit hasn't been evaluated, but the fix has been tested
> using a WiFi AP6398S SDIO module, and the iperf3 Bandwidth measurement gave
> 55.2 Mbits/sec over a 63 Hours long test, with the SDIO ios set as High-Speed
> at 50MHz clock. It gave around 170 Mbits/sec as SDR104 and 200MHz clock.
>
> Neil Armstrong (3):
> dt-bindings: mmc: meson-gx: add ddr-access-quirk property
> mmc: meson-gx: add ddr-access-quirk
> arm64: dts: meson-g12a: add ddr-access-quirk property to SDIO
> controller
>
> .../bindings/mmc/amlogic,meson-gx.txt | 4 ++
> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 1 +
> drivers/mmc/host/meson-gx-mmc.c | 65 +++++++++++++++----
> 3 files changed, 57 insertions(+), 13 deletions(-)
>
Test with SEI510 board no problem or regression seen
Tested-by: Guillaume La Roque <[email protected]>
Hi Neil,
On Mon, May 13, 2019 at 11:16 AM Neil Armstrong <[email protected]> wrote:
>
> On the Amlogic G12A SoC family, (only) the SDIO controller has a bug which
> makes any DDR access from the MMC controller fail.
>
> Add the amlogic,ddr-access-quirk property so signal this particular
> controller has this bug and needs a quirk to work properly.
>
> Signed-off-by: Neil Armstrong <[email protected]>
Reviewed-by: Martin Blumenstingl <[email protected]>
> ---
> Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
> index 13e70409e8ac..f8914dab06c6 100644
> --- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
> +++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
> @@ -22,6 +22,10 @@ Required properties:
> clock rate requested by the MMC core.
> - resets : phandle of the internal reset line
>
> +Optional properties:
> +- amlogic,ddr-access-quirk: set when HW cannot access the DDR memory, like on
> + the G12A SDIO controller.
(I believe we cannot use a standard property like "dma-ranges" to
disable DMA access)
personally I prefer "amlogic,no-direct-memory-access" or
"amlogic,no-ddr-access", but if Rob is happy with the current naming
then I'm happy as well
Regards
Martin
Hi Neil,
On Mon, May 13, 2019 at 11:16 AM Neil Armstrong <[email protected]> wrote:
[...]
> @@ -1158,15 +1183,27 @@ static int meson_mmc_probe(struct platform_device *pdev)
> */
> mmc->caps2 &= ~MMC_CAP2_HS400;
>
> - /* data bounce buffer */
> - host->bounce_buf_size = mmc->max_req_size;
> - host->bounce_buf =
> - dma_alloc_coherent(host->dev, host->bounce_buf_size,
> - &host->bounce_dma_addr, GFP_KERNEL);
> - if (host->bounce_buf == NULL) {
> - dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
> - ret = -ENOMEM;
> - goto err_free_irq;
> + if (host->ddr_access_quirk) {
> + /*
> + * The MMC Controller embeds 1,5KiB of internal SRAM
> + * that can be used to be used as bounce buffer.
> + * In the case of the G12A SDIO controller, use these
> + * instead of the DDR memory
> + */
> + host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN;
> + host->bounce_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF;
> + host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF;
I'm curious: why do you need to set bounce_dma_addr in this case?
> + } else {
> + /* data bounce buffer */
> + host->bounce_buf_size = mmc->max_req_size;
> + host->bounce_buf =
> + dma_alloc_coherent(host->dev, host->bounce_buf_size,
> + &host->bounce_dma_addr, GFP_KERNEL);
> + if (host->bounce_buf == NULL) {
> + dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
> + ret = -ENOMEM;
> + goto err_free_irq;
> + }
> }
>
> host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
if host->descs cannot be allocated then you need to conditionally skip
dma_free_coherent for the bounce buffer in the goto err_bounce_buf
case a few lines below (just like you did in meson_mmc_remove)
Martin
On Mon, 13 May 2019 at 11:16, Neil Armstrong <[email protected]> wrote:
>
> On the Amlogic G12A SoC family, (only) the SDIO controller fails to access
> the data from DDR, leading to a broken controller.
Could you possibly make it more clear that this is about the internal
DMA support in the controller that is broken?
Did you consider to use the controller without using the DMA mode? Is
that possible?
>
> But each MMC controller has 1,5KiB of SRAM after the registers, that can
> be used as bounce buffer to avoid direct DDR access from the integrated
> DMAs (this SRAM may be used by the boot ROM when DDR is not yet initialized).
I think "DDR" is a confusing terminology, that goes for the DT binding
as well. What about using "DRAM" instead?
In any case, using the SRAM seems like it could work. However, just so
I get this right, it solely dedicated to the SDIO controller or may
someone else also try to use it?
>
> The quirk is to disable the chained descriptor for this controller, and
> use this SRAM memory zone as buffer for the bounce buffer fallback mode.
>
> The performance hit hasn't been evaluated, but the fix has been tested
> using a WiFi AP6398S SDIO module, and the iperf3 Bandwidth measurement gave
> 55.2 Mbits/sec over a 63 Hours long test, with the SDIO ios set as High-Speed
> at 50MHz clock. It gave 170 Mbits/sec as SDR104 and 200MHz clock.
If possible to not use DMA, it would be interesting to compare numbers. :-)
>
> Signed-off-by: Neil Armstrong <[email protected]>
> ---
> drivers/mmc/host/meson-gx-mmc.c | 65 ++++++++++++++++++++++++++-------
> 1 file changed, 52 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
> index c5a8af4ca76b..6ef465304052 100644
> --- a/drivers/mmc/host/meson-gx-mmc.c
> +++ b/drivers/mmc/host/meson-gx-mmc.c
> @@ -129,6 +129,9 @@
> #define SD_EMMC_TXD 0x94
> #define SD_EMMC_LAST_REG SD_EMMC_TXD
>
> +#define SD_EMMC_SRAM_DATA_BUF_LEN 1536
> +#define SD_EMMC_SRAM_DATA_BUF_OFF 0x200
> +
> #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */
> #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */
> #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */
> @@ -168,6 +171,8 @@ struct meson_host {
> unsigned long req_rate;
> bool ddr;
>
> + bool ddr_access_quirk;
> +
> struct pinctrl *pinctrl;
> struct pinctrl_state *pins_default;
> struct pinctrl_state *pins_clk_gate;
> @@ -232,11 +237,20 @@ static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd)
> static void meson_mmc_get_transfer_mode(struct mmc_host *mmc,
> struct mmc_request *mrq)
> {
> + struct meson_host *host = mmc_priv(mmc);
> struct mmc_data *data = mrq->data;
> struct scatterlist *sg;
> int i;
> bool use_desc_chain_mode = true;
>
> + /*
> + * When Controller DMA cannot directly access DDR memory, disable
> + * support for Chain Mode to directly use the internal SRAM using
> + * the bounce buffer mode.
> + */
> + if (host->ddr_access_quirk)
> + return;
> +
> /*
> * Broken SDIO with AP6255-based WiFi on Khadas VIM Pro has been
> * reported. For some strange reason this occurs in descriptor
> @@ -1049,6 +1063,10 @@ static int meson_mmc_probe(struct platform_device *pdev)
> host->dev = &pdev->dev;
> dev_set_drvdata(&pdev->dev, host);
>
> + /* The G12A SDIO Controller needs an SRAM bounce buffer */
> + host->ddr_access_quirk = device_property_read_bool(&pdev->dev,
> + "amlogic,ddr-access-quirk");
> +
> /* Get regulators and the supported OCR mask */
> host->vqmmc_enabled = false;
> ret = mmc_regulator_get_supply(mmc);
> @@ -1146,9 +1164,16 @@ static int meson_mmc_probe(struct platform_device *pdev)
> goto err_init_clk;
>
> mmc->caps |= MMC_CAP_CMD23;
> - mmc->max_blk_count = CMD_CFG_LENGTH_MASK;
> + if (host->ddr_access_quirk) {
> + /* Limit to the available sram memory */
> + mmc->max_segs = SD_EMMC_SRAM_DATA_BUF_LEN / mmc->max_blk_size;
> + mmc->max_blk_count = mmc->max_segs;
> + } else {
> + mmc->max_blk_count = CMD_CFG_LENGTH_MASK;
> + mmc->max_segs = SD_EMMC_DESC_BUF_LEN /
> + sizeof(struct sd_emmc_desc);
> + }
> mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size;
> - mmc->max_segs = SD_EMMC_DESC_BUF_LEN / sizeof(struct sd_emmc_desc);
> mmc->max_seg_size = mmc->max_req_size;
>
> /*
> @@ -1158,15 +1183,27 @@ static int meson_mmc_probe(struct platform_device *pdev)
> */
> mmc->caps2 &= ~MMC_CAP2_HS400;
>
> - /* data bounce buffer */
> - host->bounce_buf_size = mmc->max_req_size;
> - host->bounce_buf =
> - dma_alloc_coherent(host->dev, host->bounce_buf_size,
> - &host->bounce_dma_addr, GFP_KERNEL);
> - if (host->bounce_buf == NULL) {
> - dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
> - ret = -ENOMEM;
> - goto err_free_irq;
> + if (host->ddr_access_quirk) {
> + /*
> + * The MMC Controller embeds 1,5KiB of internal SRAM
> + * that can be used to be used as bounce buffer.
> + * In the case of the G12A SDIO controller, use these
> + * instead of the DDR memory
> + */
> + host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN;
> + host->bounce_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF;
> + host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF;
> + } else {
> + /* data bounce buffer */
> + host->bounce_buf_size = mmc->max_req_size;
> + host->bounce_buf =
> + dma_alloc_coherent(host->dev, host->bounce_buf_size,
> + &host->bounce_dma_addr, GFP_KERNEL);
> + if (host->bounce_buf == NULL) {
> + dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
> + ret = -ENOMEM;
> + goto err_free_irq;
> + }
> }
>
> host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
> @@ -1208,8 +1245,10 @@ static int meson_mmc_remove(struct platform_device *pdev)
>
> dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
> host->descs, host->descs_dma_addr);
> - dma_free_coherent(host->dev, host->bounce_buf_size,
> - host->bounce_buf, host->bounce_dma_addr);
> +
> + if (!host->ddr_access_quirk)
> + dma_free_coherent(host->dev, host->bounce_buf_size,
> + host->bounce_buf, host->bounce_dma_addr);
>
> clk_disable_unprepare(host->mmc_clk);
> clk_disable_unprepare(host->core_clk);
> --
> 2.21.0
>
Kind regards
Uffe
On Mon, 13 May 2019 at 11:16, Neil Armstrong <[email protected]> wrote:
>
> On the Amlogic G12A SoC family, (only) the SDIO controller has a bug which
> makes any DDR access from the MMC controller fail.
>
> Add the amlogic,ddr-access-quirk property so signal this particular
> controller has this bug and needs a quirk to work properly.
>
> Signed-off-by: Neil Armstrong <[email protected]>
> ---
> Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
> index 13e70409e8ac..f8914dab06c6 100644
> --- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
> +++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
> @@ -22,6 +22,10 @@ Required properties:
> clock rate requested by the MMC core.
> - resets : phandle of the internal reset line
>
> +Optional properties:
> +- amlogic,ddr-access-quirk: set when HW cannot access the DDR memory, like on
> + the G12A SDIO controller.
As stated on the other patch, may I suggest to use DRAM instead of DDR.
Moreover, please mention that this is about the internal DMA support
of the controller.
> +
> Example:
>
> sd_emmc_a: mmc@70000 {
> --
> 2.21.0
>
Kind regards
Uffe
On 14/05/2019 19:50, Martin Blumenstingl wrote:
> Hi Neil,
>
> On Mon, May 13, 2019 at 11:16 AM Neil Armstrong <[email protected]> wrote:
>>
>> On the Amlogic G12A SoC family, (only) the SDIO controller has a bug which
>> makes any DDR access from the MMC controller fail.
>>
>> Add the amlogic,ddr-access-quirk property so signal this particular
>> controller has this bug and needs a quirk to work properly.
>>
>> Signed-off-by: Neil Armstrong <[email protected]>
> Reviewed-by: Martin Blumenstingl <[email protected]>
>
>> ---
>> Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
>> index 13e70409e8ac..f8914dab06c6 100644
>> --- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
>> +++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
>> @@ -22,6 +22,10 @@ Required properties:
>> clock rate requested by the MMC core.
>> - resets : phandle of the internal reset line
>>
>> +Optional properties:
>> +- amlogic,ddr-access-quirk: set when HW cannot access the DDR memory, like on
>> + the G12A SDIO controller.
> (I believe we cannot use a standard property like "dma-ranges" to
> disable DMA access)
> personally I prefer "amlogic,no-direct-memory-access" or
> "amlogic,no-ddr-access", but if Rob is happy with the current naming
> then I'm happy as well
I have no preference, I can change it easily,
Neil
>
>
> Regards
> Martin
>
On 15/05/2019 13:37, Ulf Hansson wrote:
> On Mon, 13 May 2019 at 11:16, Neil Armstrong <[email protected]> wrote:
>>
>> On the Amlogic G12A SoC family, (only) the SDIO controller has a bug which
>> makes any DDR access from the MMC controller fail.
>>
>> Add the amlogic,ddr-access-quirk property so signal this particular
>> controller has this bug and needs a quirk to work properly.
>>
>> Signed-off-by: Neil Armstrong <[email protected]>
>> ---
>> Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
>> index 13e70409e8ac..f8914dab06c6 100644
>> --- a/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
>> +++ b/Documentation/devicetree/bindings/mmc/amlogic,meson-gx.txt
>> @@ -22,6 +22,10 @@ Required properties:
>> clock rate requested by the MMC core.
>> - resets : phandle of the internal reset line
>>
>> +Optional properties:
>> +- amlogic,ddr-access-quirk: set when HW cannot access the DDR memory, like on
>> + the G12A SDIO controller.
>
> As stated on the other patch, may I suggest to use DRAM instead of DDR.
Indeed, may be more accurate.
>
> Moreover, please mention that this is about the internal DMA support
> of the controller.
Ok
>
>> +
>> Example:
>>
>> sd_emmc_a: mmc@70000 {
>> --
>> 2.21.0
>>
>
> Kind regards
> Uffe
>
On 14/05/2019 19:58, Martin Blumenstingl wrote:
> Hi Neil,
>
> On Mon, May 13, 2019 at 11:16 AM Neil Armstrong <[email protected]> wrote:
> [...]
>> @@ -1158,15 +1183,27 @@ static int meson_mmc_probe(struct platform_device *pdev)
>> */
>> mmc->caps2 &= ~MMC_CAP2_HS400;
>>
>> - /* data bounce buffer */
>> - host->bounce_buf_size = mmc->max_req_size;
>> - host->bounce_buf =
>> - dma_alloc_coherent(host->dev, host->bounce_buf_size,
>> - &host->bounce_dma_addr, GFP_KERNEL);
>> - if (host->bounce_buf == NULL) {
>> - dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
>> - ret = -ENOMEM;
>> - goto err_free_irq;
>> + if (host->ddr_access_quirk) {
>> + /*
>> + * The MMC Controller embeds 1,5KiB of internal SRAM
>> + * that can be used to be used as bounce buffer.
>> + * In the case of the G12A SDIO controller, use these
>> + * instead of the DDR memory
>> + */
>> + host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN;
>> + host->bounce_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF;
>> + host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF;
> I'm curious: why do you need to set bounce_dma_addr in this case?
We still need the physical bounce buffer address since we write in the registers,
and we need the logical address to memcpy() in the buffer.
>
>> + } else {
>> + /* data bounce buffer */
>> + host->bounce_buf_size = mmc->max_req_size;
>> + host->bounce_buf =
>> + dma_alloc_coherent(host->dev, host->bounce_buf_size,
>> + &host->bounce_dma_addr, GFP_KERNEL);
>> + if (host->bounce_buf == NULL) {
>> + dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
>> + ret = -ENOMEM;
>> + goto err_free_irq;
>> + }
>> }
>>
>> host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
> if host->descs cannot be allocated then you need to conditionally skip
> dma_free_coherent for the bounce buffer in the goto err_bounce_buf
> case a few lines below (just like you did in meson_mmc_remove)
It can be allocated, it's only useless. I can skip it but I don't want
to break any logic in the driver.
>
>
> Martin
>
On 15/05/2019 13:34, Ulf Hansson wrote:
> On Mon, 13 May 2019 at 11:16, Neil Armstrong <[email protected]> wrote:
>>
>> On the Amlogic G12A SoC family, (only) the SDIO controller fails to access
>> the data from DDR, leading to a broken controller.
>
> Could you possibly make it more clear that this is about the internal
> DMA support in the controller that is broken?
>
> Did you consider to use the controller without using the DMA mode? Is
> that possible?
No we can only use the DMA, in block mode (using our bounce buffer mode)
or in descriptor mode.
>
>>
>> But each MMC controller has 1,5KiB of SRAM after the registers, that can
>> be used as bounce buffer to avoid direct DDR access from the integrated
>> DMAs (this SRAM may be used by the boot ROM when DDR is not yet initialized).
>
> I think "DDR" is a confusing terminology, that goes for the DT binding
> as well. What about using "DRAM" instead?
Seems better, I'll wait on Rob's feedback on this a few more days.
>
> In any case, using the SRAM seems like it could work. However, just so
> I get this right, it solely dedicated to the SDIO controller or may
> someone else also try to use it?
This SRAM is dedicated to *each* MMC controller. Not sure if other masters
could access it, but it would be unfortunate.
I'll add these details in the commit log.
>
>>
>> The quirk is to disable the chained descriptor for this controller, and
>> use this SRAM memory zone as buffer for the bounce buffer fallback mode.
>>
>> The performance hit hasn't been evaluated, but the fix has been tested
>> using a WiFi AP6398S SDIO module, and the iperf3 Bandwidth measurement gave
>> 55.2 Mbits/sec over a 63 Hours long test, with the SDIO ios set as High-Speed
>> at 50MHz clock. It gave 170 Mbits/sec as SDR104 and 200MHz clock.
>
> If possible to not use DMA, it would be interesting to compare numbers. :-)
I could activate this quirk on a MMC or SDcard dedicated controller and
compare, but SDIO and MMC/SDcard transactions are really different.
We compared it on the AXG platform with the same MMC controller revision,
CPU freq, DRAM technology, kernel revision and the peak WiFi "speed" was
equivalent, but with a slighly superior CPU usage.
>
>>
>> Signed-off-by: Neil Armstrong <[email protected]>
>> ---
>> drivers/mmc/host/meson-gx-mmc.c | 65 ++++++++++++++++++++++++++-------
>> 1 file changed, 52 insertions(+), 13 deletions(-)
>>
>> diff --git a/drivers/mmc/host/meson-gx-mmc.c b/drivers/mmc/host/meson-gx-mmc.c
>> index c5a8af4ca76b..6ef465304052 100644
>> --- a/drivers/mmc/host/meson-gx-mmc.c
>> +++ b/drivers/mmc/host/meson-gx-mmc.c
>> @@ -129,6 +129,9 @@
>> #define SD_EMMC_TXD 0x94
>> #define SD_EMMC_LAST_REG SD_EMMC_TXD
>>
>> +#define SD_EMMC_SRAM_DATA_BUF_LEN 1536
>> +#define SD_EMMC_SRAM_DATA_BUF_OFF 0x200
>> +
>> #define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */
>> #define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */
>> #define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */
>> @@ -168,6 +171,8 @@ struct meson_host {
>> unsigned long req_rate;
>> bool ddr;
>>
>> + bool ddr_access_quirk;
>> +
>> struct pinctrl *pinctrl;
>> struct pinctrl_state *pins_default;
>> struct pinctrl_state *pins_clk_gate;
>> @@ -232,11 +237,20 @@ static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd)
>> static void meson_mmc_get_transfer_mode(struct mmc_host *mmc,
>> struct mmc_request *mrq)
>> {
>> + struct meson_host *host = mmc_priv(mmc);
>> struct mmc_data *data = mrq->data;
>> struct scatterlist *sg;
>> int i;
>> bool use_desc_chain_mode = true;
>>
>> + /*
>> + * When Controller DMA cannot directly access DDR memory, disable
>> + * support for Chain Mode to directly use the internal SRAM using
>> + * the bounce buffer mode.
>> + */
>> + if (host->ddr_access_quirk)
>> + return;
>> +
>> /*
>> * Broken SDIO with AP6255-based WiFi on Khadas VIM Pro has been
>> * reported. For some strange reason this occurs in descriptor
>> @@ -1049,6 +1063,10 @@ static int meson_mmc_probe(struct platform_device *pdev)
>> host->dev = &pdev->dev;
>> dev_set_drvdata(&pdev->dev, host);
>>
>> + /* The G12A SDIO Controller needs an SRAM bounce buffer */
>> + host->ddr_access_quirk = device_property_read_bool(&pdev->dev,
>> + "amlogic,ddr-access-quirk");
>> +
>> /* Get regulators and the supported OCR mask */
>> host->vqmmc_enabled = false;
>> ret = mmc_regulator_get_supply(mmc);
>> @@ -1146,9 +1164,16 @@ static int meson_mmc_probe(struct platform_device *pdev)
>> goto err_init_clk;
>>
>> mmc->caps |= MMC_CAP_CMD23;
>> - mmc->max_blk_count = CMD_CFG_LENGTH_MASK;
>> + if (host->ddr_access_quirk) {
>> + /* Limit to the available sram memory */
>> + mmc->max_segs = SD_EMMC_SRAM_DATA_BUF_LEN / mmc->max_blk_size;
>> + mmc->max_blk_count = mmc->max_segs;
>> + } else {
>> + mmc->max_blk_count = CMD_CFG_LENGTH_MASK;
>> + mmc->max_segs = SD_EMMC_DESC_BUF_LEN /
>> + sizeof(struct sd_emmc_desc);
>> + }
>> mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size;
>> - mmc->max_segs = SD_EMMC_DESC_BUF_LEN / sizeof(struct sd_emmc_desc);
>> mmc->max_seg_size = mmc->max_req_size;
>>
>> /*
>> @@ -1158,15 +1183,27 @@ static int meson_mmc_probe(struct platform_device *pdev)
>> */
>> mmc->caps2 &= ~MMC_CAP2_HS400;
>>
>> - /* data bounce buffer */
>> - host->bounce_buf_size = mmc->max_req_size;
>> - host->bounce_buf =
>> - dma_alloc_coherent(host->dev, host->bounce_buf_size,
>> - &host->bounce_dma_addr, GFP_KERNEL);
>> - if (host->bounce_buf == NULL) {
>> - dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
>> - ret = -ENOMEM;
>> - goto err_free_irq;
>> + if (host->ddr_access_quirk) {
>> + /*
>> + * The MMC Controller embeds 1,5KiB of internal SRAM
>> + * that can be used to be used as bounce buffer.
>> + * In the case of the G12A SDIO controller, use these
>> + * instead of the DDR memory
>> + */
>> + host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN;
>> + host->bounce_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF;
>> + host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF;
>> + } else {
>> + /* data bounce buffer */
>> + host->bounce_buf_size = mmc->max_req_size;
>> + host->bounce_buf =
>> + dma_alloc_coherent(host->dev, host->bounce_buf_size,
>> + &host->bounce_dma_addr, GFP_KERNEL);
>> + if (host->bounce_buf == NULL) {
>> + dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
>> + ret = -ENOMEM;
>> + goto err_free_irq;
>> + }
>> }
>>
>> host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
>> @@ -1208,8 +1245,10 @@ static int meson_mmc_remove(struct platform_device *pdev)
>>
>> dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
>> host->descs, host->descs_dma_addr);
>> - dma_free_coherent(host->dev, host->bounce_buf_size,
>> - host->bounce_buf, host->bounce_dma_addr);
>> +
>> + if (!host->ddr_access_quirk)
>> + dma_free_coherent(host->dev, host->bounce_buf_size,
>> + host->bounce_buf, host->bounce_dma_addr);
>>
>> clk_disable_unprepare(host->mmc_clk);
>> clk_disable_unprepare(host->core_clk);
>> --
>> 2.21.0
>>
Thanks for reviewing,
>
> Kind regards
> Uffe
>
Hi Neil,
On Wed, May 15, 2019 at 2:45 PM Neil Armstrong <[email protected]> wrote:
>
> On 14/05/2019 19:58, Martin Blumenstingl wrote:
> > Hi Neil,
> >
> > On Mon, May 13, 2019 at 11:16 AM Neil Armstrong <[email protected]> wrote:
> > [...]
> >> @@ -1158,15 +1183,27 @@ static int meson_mmc_probe(struct platform_device *pdev)
> >> */
> >> mmc->caps2 &= ~MMC_CAP2_HS400;
> >>
> >> - /* data bounce buffer */
> >> - host->bounce_buf_size = mmc->max_req_size;
> >> - host->bounce_buf =
> >> - dma_alloc_coherent(host->dev, host->bounce_buf_size,
> >> - &host->bounce_dma_addr, GFP_KERNEL);
> >> - if (host->bounce_buf == NULL) {
> >> - dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
> >> - ret = -ENOMEM;
> >> - goto err_free_irq;
> >> + if (host->ddr_access_quirk) {
> >> + /*
> >> + * The MMC Controller embeds 1,5KiB of internal SRAM
> >> + * that can be used to be used as bounce buffer.
> >> + * In the case of the G12A SDIO controller, use these
> >> + * instead of the DDR memory
> >> + */
> >> + host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN;
> >> + host->bounce_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF;
> >> + host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF;
> > I'm curious: why do you need to set bounce_dma_addr in this case?
>
> We still need the physical bounce buffer address since we write in the registers,
so writing bounce_dma_addr to SD_EMMC_CMD_DAT is needed to make it work?
> and we need the logical address to memcpy() in the buffer.
as far as I understand that is what we use the "bounce_buf" member
for, but I don't see why we need "bounce_dma_addr"
> >
> >> + } else {
> >> + /* data bounce buffer */
> >> + host->bounce_buf_size = mmc->max_req_size;
> >> + host->bounce_buf =
> >> + dma_alloc_coherent(host->dev, host->bounce_buf_size,
> >> + &host->bounce_dma_addr, GFP_KERNEL);
> >> + if (host->bounce_buf == NULL) {
> >> + dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
> >> + ret = -ENOMEM;
> >> + goto err_free_irq;
> >> + }
> >> }
> >>
> >> host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
> > if host->descs cannot be allocated then you need to conditionally skip
> > dma_free_coherent for the bounce buffer in the goto err_bounce_buf
> > case a few lines below (just like you did in meson_mmc_remove)
>
> It can be allocated, it's only useless. I can skip it but I don't want
> to break any logic in the driver.
I wasn't clear in my last email, I meant this error case:
err_bounce_buf:
dma_free_coherent(host->dev, host->bounce_buf_size, ...
when host->ddr_access_quirk is true then you skip the
dma_alloc_coherent call for bounce_buf
Martin
On 15/05/2019 23:18, Martin Blumenstingl wrote:
> Hi Neil,
>
> On Wed, May 15, 2019 at 2:45 PM Neil Armstrong <[email protected]> wrote:
>>
>> On 14/05/2019 19:58, Martin Blumenstingl wrote:
>>> Hi Neil,
>>>
>>> On Mon, May 13, 2019 at 11:16 AM Neil Armstrong <[email protected]> wrote:
>>> [...]
>>>> @@ -1158,15 +1183,27 @@ static int meson_mmc_probe(struct platform_device *pdev)
>>>> */
>>>> mmc->caps2 &= ~MMC_CAP2_HS400;
>>>>
>>>> - /* data bounce buffer */
>>>> - host->bounce_buf_size = mmc->max_req_size;
>>>> - host->bounce_buf =
>>>> - dma_alloc_coherent(host->dev, host->bounce_buf_size,
>>>> - &host->bounce_dma_addr, GFP_KERNEL);
>>>> - if (host->bounce_buf == NULL) {
>>>> - dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
>>>> - ret = -ENOMEM;
>>>> - goto err_free_irq;
>>>> + if (host->ddr_access_quirk) {
>>>> + /*
>>>> + * The MMC Controller embeds 1,5KiB of internal SRAM
>>>> + * that can be used to be used as bounce buffer.
>>>> + * In the case of the G12A SDIO controller, use these
>>>> + * instead of the DDR memory
>>>> + */
>>>> + host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN;
>>>> + host->bounce_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF;
>>>> + host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF;
>>> I'm curious: why do you need to set bounce_dma_addr in this case?
>>
>> We still need the physical bounce buffer address since we write in the registers,
> so writing bounce_dma_addr to SD_EMMC_CMD_DAT is needed to make it work?
>
>> and we need the logical address to memcpy() in the buffer.
> as far as I understand that is what we use the "bounce_buf" member
> for, but I don't see why we need "bounce_dma_addr"
Sorry I don't understand these questions, I haven't changed the
bounce buffer behavior here, I only make it use a local SRAM buffer
instead of an dma_alloc_coherent() allocated buffer.
Having bounce_buf_size/bounce_buf/bounce_dma_addr is still necessary like
an allocated buffer.
>
>>>
>>>> + } else {
>>>> + /* data bounce buffer */
>>>> + host->bounce_buf_size = mmc->max_req_size;
>>>> + host->bounce_buf =
>>>> + dma_alloc_coherent(host->dev, host->bounce_buf_size,
>>>> + &host->bounce_dma_addr, GFP_KERNEL);
>>>> + if (host->bounce_buf == NULL) {
>>>> + dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
>>>> + ret = -ENOMEM;
>>>> + goto err_free_irq;
>>>> + }
>>>> }
>>>>
>>>> host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
>>> if host->descs cannot be allocated then you need to conditionally skip
>>> dma_free_coherent for the bounce buffer in the goto err_bounce_buf
>>> case a few lines below (just like you did in meson_mmc_remove)
>>
>> It can be allocated, it's only useless. I can skip it but I don't want
>> to break any logic in the driver.
> I wasn't clear in my last email, I meant this error case:
> err_bounce_buf:
> dma_free_coherent(host->dev, host->bounce_buf_size, ...
> when host->ddr_access_quirk is true then you skip the
> dma_alloc_coherent call for bounce_buf
Oh, ok, yes, I'll add it.
Neil
>
>
> Martin
>