LinuxLists.cc - [PATCH v6 0/6] Allwinner H6 Mali GPU support

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Subject: [PATCH v6 2/6] iommu: io-pgtable: fix sanity check for non 48-bit mali iommu

Allwinner H6 SoC has a Mali T720MP2 with a 33-bit iommu which
trig the sanity check during the alloc of the pgtable.

Change the sanity check to allow non 48-bit configuration.

Suggested-by: Robin Murphy <[email protected]>
Signed-off-by: Clément Péron <[email protected]>
---
drivers/iommu/io-pgtable-arm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index 4e21efbc4459..74f2ce802e6f 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -1016,7 +1016,7 @@ arm_mali_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg, void *cookie)
{
struct io_pgtable *iop;

- if (cfg->ias != 48 || cfg->oas > 40)
+ if (cfg->ias > 48 || cfg->oas > 40)
return NULL;

cfg->pgsize_bitmap &= (SZ_4K | SZ_2M | SZ_1G);
--
2.17.1

2019-05-21 16:12:54

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Subject: [PATCH v6 5/6] arm64: dts: allwinner: Add ARM Mali GPU node for H6

Add the mali gpu node to the H6 device-tree.

Signed-off-by: Clément Péron <[email protected]>
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 16c5c3d0fd81..6aad06095c40 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -157,6 +157,20 @@
allwinner,sram = <&ve_sram 1>;
};

+ gpu: gpu@1800000 {
+ compatible = "allwinner,sun50i-h6-mali",
+ "arm,mali-t720";
+ reg = <0x01800000 0x4000>;
+ interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "job", "mmu", "gpu";
+ clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>;
+ clock-names = "core", "bus";
+ resets = <&ccu RST_BUS_GPU>;
+ status = "disabled";
+ };
+
syscon: syscon@3000000 {
compatible = "allwinner,sun50i-h6-system-control",
"allwinner,sun50i-a64-system-control";
--
2.17.1

2019-05-21 16:13:00

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Subject: [PATCH v6 6/6] arm64: dts: allwinner: Add mali GPU supply for H6 boards

Enable and add supply to the Mali GPU node on all the
H6 boards.

Regarding the datasheet the maximum time for supply to reach
its voltage is 32ms.

Signed-off-by: Clément Péron <[email protected]>
---
arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 6 ++++++
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts | 6 ++++++
arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi | 6 ++++++
arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 6 ++++++
4 files changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
index 0dc33c90dd60..fe36c6588d8e 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts
@@ -70,6 +70,11 @@
status = "okay";
};

+&gpu {
+ mali-supply = <&reg_dcdcc>;
+ status = "okay";
+};
+
&hdmi {
status = "okay";
};
@@ -206,6 +211,7 @@
};

reg_dcdcc: dcdcc {
+ regulator-enable-ramp-delay = <32000>;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1080000>;
regulator-name = "vdd-gpu";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
index 17d496990108..ea4866b0fa7a 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi-3.dts
@@ -58,6 +58,11 @@
status = "okay";
};

+&gpu {
+ mali-supply = <&reg_dcdcc>;
+ status = "okay";
+};
+
&mmc0 {
vmmc-supply = <&reg_cldo1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */
@@ -165,6 +170,7 @@
};

reg_dcdcc: dcdcc {
+ regulator-enable-ramp-delay = <32000>;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1080000>;
regulator-name = "vdd-gpu";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
index 62e27948a3fa..ec770f07aa82 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-orangepi.dtsi
@@ -55,6 +55,11 @@
status = "okay";
};

+&gpu {
+ mali-supply = <&reg_dcdcc>;
+ status = "okay";
+};
+
&mmc0 {
vmmc-supply = <&reg_cldo1>;
cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;
@@ -163,6 +168,7 @@
};

reg_dcdcc: dcdcc {
+ regulator-enable-ramp-delay = <32000>;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1080000>;
regulator-name = "vdd-gpu";
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
index 4802902e128f..625a29a25c52 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts
@@ -85,6 +85,11 @@
status = "okay";
};

+&gpu {
+ mali-supply = <&reg_dcdcc>;
+ status = "okay";
+};
+
&hdmi {
status = "okay";
};
@@ -215,6 +220,7 @@
};

reg_dcdcc: dcdcc {
+ regulator-enable-ramp-delay = <32000>;
regulator-min-microvolt = <810000>;
regulator-max-microvolt = <1080000>;
regulator-name = "vdd-gpu";
--
2.17.1

2019-05-21 16:13:42

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Subject: [PATCH v6 1/6] drm: panfrost: add optional bus_clock

Allwinner H6 has an ARM Mali-T720 MP2 which required a bus_clock.

Add an optional bus_clock at the init of the panfrost driver.

Signed-off-by: Clément Péron <[email protected]>
---
drivers/gpu/drm/panfrost/panfrost_device.c | 22 ++++++++++++++++++++++
drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
2 files changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/panfrost/panfrost_device.c b/drivers/gpu/drm/panfrost/panfrost_device.c
index 3b2bced1b015..ccb8eb2a518c 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.c
+++ b/drivers/gpu/drm/panfrost/panfrost_device.c
@@ -55,11 +55,33 @@ static int panfrost_clk_init(struct panfrost_device *pfdev)
if (err)
return err;

+ pfdev->bus_clock = devm_clk_get_optional(pfdev->dev, "bus");
+ if (IS_ERR(pfdev->bus_clock)) {
+ dev_err(pfdev->dev, "get bus_clock failed %ld\n",
+ PTR_ERR(pfdev->bus_clock));
+ return PTR_ERR(pfdev->bus_clock);
+ }
+
+ if (pfdev->bus_clock) {
+ rate = clk_get_rate(pfdev->bus_clock);
+ dev_info(pfdev->dev, "bus_clock rate = %lu\n", rate);
+
+ err = clk_prepare_enable(pfdev->bus_clock);
+ if (err)
+ goto disable_clock;
+ }
+
return 0;
+
+disable_clock:
+ clk_disable_unprepare(pfdev->clock);
+
+ return err;
}

static void panfrost_clk_fini(struct panfrost_device *pfdev)
{
+ clk_disable_unprepare(pfdev->bus_clock);
clk_disable_unprepare(pfdev->clock);
}

diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h
index 56f452dfb490..8074f221034b 100644
--- a/drivers/gpu/drm/panfrost/panfrost_device.h
+++ b/drivers/gpu/drm/panfrost/panfrost_device.h
@@ -66,6 +66,7 @@ struct panfrost_device {

void __iomem *iomem;
struct clk *clock;
+ struct clk *bus_clock;
struct regulator *regulator;
struct reset_control *rstc;

--
2.17.1

2019-05-21 16:13:44

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Subject: [PATCH v6 3/6] dt-bindings: gpu: add bus clock for Mali Midgard GPUs

From: Icenowy Zheng <[email protected]>

Some SoCs adds a bus clock gate to the Mali Midgard GPU.

Add the binding for the bus clock.

Signed-off-by: Icenowy Zheng <[email protected]>
Signed-off-by: Clément Péron <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt | 6 ++++++
1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
index 1b1a74129141..2e8bbce35695 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
@@ -31,6 +31,12 @@ Optional properties:

- clocks : Phandle to clock for the Mali Midgard device.

+- clock-names : Specify the names of the clocks specified in clocks
+ when multiple clocks are present.
+ * core: clock driving the GPU itself (When only one clock is present,
+ assume it's this clock.)
+ * bus: bus clock for the GPU
+
- mali-supply : Phandle to regulator for the Mali device. Refer to
Documentation/devicetree/bindings/regulator/regulator.txt for details.

--
2.17.1

2019-05-21 16:14:41

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Subject: [PATCH v6 4/6] dt-bindings: gpu: mali-midgard: Add H6 mali gpu compatible

This add the H6 mali compatible in the dt-bindings to later support
specific implementation.

Signed-off-by: Clément Péron <[email protected]>
Reviewed-by: Rob Herring <[email protected]>
---
.../devicetree/bindings/gpu/arm,mali-midgard.txt | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
index 2e8bbce35695..4bf17e1cf555 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
@@ -15,6 +15,7 @@ Required properties:
+ "arm,mali-t860"
+ "arm,mali-t880"
* which must be preceded by one of the following vendor specifics:
+ + "allwinner,sun50i-h6-mali"
+ "amlogic,meson-gxm-mali"
+ "rockchip,rk3288-mali"
+ "rockchip,rk3399-mali"
@@ -49,9 +50,15 @@ Vendor-specific bindings
------------------------

The Mali GPU is integrated very differently from one SoC to
-another. In order to accomodate those differences, you have the option
+another. In order to accommodate those differences, you have the option
to specify one more vendor-specific compatible, among:

+- "allwinner,sun50i-h6-mali"
+ Required properties:
+ - clocks : phandles to core and bus clocks
+ - clock-names : must contain "core" and "bus"
+ - resets: phandle to GPU reset line
+
- "amlogic,meson-gxm-mali"
Required properties:
- resets : Should contain phandles of :
--
2.17.1

2019-05-22 19:44:31

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Subject: Re: [PATCH v6 0/6] Allwinner H6 Mali GPU support

Hi Rob,

On Wed, 22 May 2019 at 21:27, Rob Herring <[email protected]> wrote:
>
> On Tue, May 21, 2019 at 11:11 AM Clément Péron <[email protected]> wrote:
> >
> > Hi,
> >
> > The Allwinner H6 has a Mali-T720 MP2 which should be supported by
> > the new panfrost driver. This series fix two issues and introduce the
> > dt-bindings but a simple benchmark show that it's still NOT WORKING.
> >
> > I'm pushing it in case someone want to continue the work.
> >
> > This has been tested with Mesa3D 19.1.0-RC2 and a GPU bitness patch[1].
> >
> > One patch is from Icenowy Zheng where I changed the order as required
> > by Rob Herring[2].
> >
> > Thanks,
> > Clement
> >
> > [1] https://gitlab.freedesktop.org/kszaq/mesa/tree/panfrost_64_32
> > [2] https://patchwork.kernel.org/patch/10699829/
> >
> >
> > [ 345.204813] panfrost 1800000.gpu: mmu irq status=1
> > [ 345.209617] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
> > 0x0000000002400400
> > [ 345.209617] Reason: TODO
> > [ 345.209617] raw fault status: 0x800002C1
> > [ 345.209617] decoded fault status: SLAVE FAULT
> > [ 345.209617] exception type 0xC1: TRANSLATION_FAULT_LEVEL1
> > [ 345.209617] access type 0x2: READ
> > [ 345.209617] source id 0x8000
> > [ 345.729957] panfrost 1800000.gpu: gpu sched timeout, js=0,
> > status=0x8, head=0x2400400, tail=0x2400400, sched_job=000000009e204de9
> > [ 346.055876] panfrost 1800000.gpu: mmu irq status=1
> > [ 346.060680] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
> > 0x0000000002C00A00
> > [ 346.060680] Reason: TODO
> > [ 346.060680] raw fault status: 0x810002C1
> > [ 346.060680] decoded fault status: SLAVE FAULT
> > [ 346.060680] exception type 0xC1: TRANSLATION_FAULT_LEVEL1
> > [ 346.060680] access type 0x2: READ
> > [ 346.060680] source id 0x8100
> > [ 346.561955] panfrost 1800000.gpu: gpu sched timeout, js=1,
> > status=0x8, head=0x2c00a00, tail=0x2c00a00, sched_job=00000000b55a9a85
> > [ 346.573913] panfrost 1800000.gpu: mmu irq status=1
> > [ 346.578707] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
> > 0x0000000002C00B80
> >
> > Change in v5:
> > - Remove fix indent
> >
> > Changes in v4:
> > - Add bus_clock probe
> > - Fix sanity check in io-pgtable
> > - Add vramp-delay
> > - Merge all boards into one patch
> > - Remove upstreamed Neil A. patch
> >
> > Change in v3 (Thanks to Maxime Ripard):
> > - Reauthor Icenowy for her path
> >
> > Changes in v2 (Thanks to Maxime Ripard):
> > - Drop GPU OPP Table
> > - Add clocks and clock-names in required
> >
> > Clément Péron (5):
> > drm: panfrost: add optional bus_clock
> > iommu: io-pgtable: fix sanity check for non 48-bit mali iommu
> > dt-bindings: gpu: mali-midgard: Add H6 mali gpu compatible
> > arm64: dts: allwinner: Add ARM Mali GPU node for H6
> > arm64: dts: allwinner: Add mali GPU supply for H6 boards
> >
> > Icenowy Zheng (1):
> > dt-bindings: gpu: add bus clock for Mali Midgard GPUs
>
> I've applied patches 1 and 3 to drm-misc. I was going to do patch 4
> too, but it doesn't apply.

Thanks,

I have tried to applied on drm-misc/for-linux-next but it doesn't apply too.
It looks like commit d5ff1adb3809e2f74a3b57cea2e57c8e37d693c4 is
missing on drm-misc ?
https://github.com/torvalds/linux/commit/d5ff1adb3809e2f74a3b57cea2e57c8e37d693c4#diff-c3172f5d421d492ff91d7bb44dd44917

Clément

>
> Patch 2 can go in via the iommu tree and the rest via the allwinner tree.
>
> Rob

2019-05-22 19:50:01

by Rob Herring

[permalink] [raw]

Subject: Re: [PATCH v6 0/6] Allwinner H6 Mali GPU support

On Tue, May 21, 2019 at 11:11 AM Clément Péron <[email protected]> wrote:
>
> Hi,
>
> The Allwinner H6 has a Mali-T720 MP2 which should be supported by
> the new panfrost driver. This series fix two issues and introduce the
> dt-bindings but a simple benchmark show that it's still NOT WORKING.
>
> I'm pushing it in case someone want to continue the work.
>
> This has been tested with Mesa3D 19.1.0-RC2 and a GPU bitness patch[1].
>
> One patch is from Icenowy Zheng where I changed the order as required
> by Rob Herring[2].
>
> Thanks,
> Clement
>
> [1] https://gitlab.freedesktop.org/kszaq/mesa/tree/panfrost_64_32
> [2] https://patchwork.kernel.org/patch/10699829/
>
>
> [ 345.204813] panfrost 1800000.gpu: mmu irq status=1
> [ 345.209617] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
> 0x0000000002400400
> [ 345.209617] Reason: TODO
> [ 345.209617] raw fault status: 0x800002C1
> [ 345.209617] decoded fault status: SLAVE FAULT
> [ 345.209617] exception type 0xC1: TRANSLATION_FAULT_LEVEL1
> [ 345.209617] access type 0x2: READ
> [ 345.209617] source id 0x8000
> [ 345.729957] panfrost 1800000.gpu: gpu sched timeout, js=0,
> status=0x8, head=0x2400400, tail=0x2400400, sched_job=000000009e204de9
> [ 346.055876] panfrost 1800000.gpu: mmu irq status=1
> [ 346.060680] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
> 0x0000000002C00A00
> [ 346.060680] Reason: TODO
> [ 346.060680] raw fault status: 0x810002C1
> [ 346.060680] decoded fault status: SLAVE FAULT
> [ 346.060680] exception type 0xC1: TRANSLATION_FAULT_LEVEL1
> [ 346.060680] access type 0x2: READ
> [ 346.060680] source id 0x8100
> [ 346.561955] panfrost 1800000.gpu: gpu sched timeout, js=1,
> status=0x8, head=0x2c00a00, tail=0x2c00a00, sched_job=00000000b55a9a85
> [ 346.573913] panfrost 1800000.gpu: mmu irq status=1
> [ 346.578707] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
> 0x0000000002C00B80
>
> Change in v5:
> - Remove fix indent
>
> Changes in v4:
> - Add bus_clock probe
> - Fix sanity check in io-pgtable
> - Add vramp-delay
> - Merge all boards into one patch
> - Remove upstreamed Neil A. patch
>
> Change in v3 (Thanks to Maxime Ripard):
> - Reauthor Icenowy for her path
>
> Changes in v2 (Thanks to Maxime Ripard):
> - Drop GPU OPP Table
> - Add clocks and clock-names in required
>
> Clément Péron (5):
> drm: panfrost: add optional bus_clock
> iommu: io-pgtable: fix sanity check for non 48-bit mali iommu
> dt-bindings: gpu: mali-midgard: Add H6 mali gpu compatible
> arm64: dts: allwinner: Add ARM Mali GPU node for H6
> arm64: dts: allwinner: Add mali GPU supply for H6 boards
>
> Icenowy Zheng (1):
> dt-bindings: gpu: add bus clock for Mali Midgard GPUs

I've applied patches 1 and 3 to drm-misc. I was going to do patch 4
too, but it doesn't apply.

Patch 2 can go in via the iommu tree and the rest via the allwinner tree.

Rob

2019-05-22 20:54:59

by Rob Herring

[permalink] [raw]

Subject: Re: [PATCH v6 0/6] Allwinner H6 Mali GPU support

On Wed, May 22, 2019 at 2:41 PM Clément Péron <[email protected]> wrote:
>
> Hi Rob,
>
> On Wed, 22 May 2019 at 21:27, Rob Herring <[email protected]> wrote:
> >
> > On Tue, May 21, 2019 at 11:11 AM Clément Péron <[email protected]> wrote:
> > >
> > > Hi,
> > >
> > > The Allwinner H6 has a Mali-T720 MP2 which should be supported by
> > > the new panfrost driver. This series fix two issues and introduce the
> > > dt-bindings but a simple benchmark show that it's still NOT WORKING.
> > >
> > > I'm pushing it in case someone want to continue the work.
> > >
> > > This has been tested with Mesa3D 19.1.0-RC2 and a GPU bitness patch[1].
> > >
> > > One patch is from Icenowy Zheng where I changed the order as required
> > > by Rob Herring[2].
> > >
> > > Thanks,
> > > Clement
> > >
> > > [1] https://gitlab.freedesktop.org/kszaq/mesa/tree/panfrost_64_32
> > > [2] https://patchwork.kernel.org/patch/10699829/
> > >
> > >
> > > [ 345.204813] panfrost 1800000.gpu: mmu irq status=1
> > > [ 345.209617] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
> > > 0x0000000002400400
> > > [ 345.209617] Reason: TODO
> > > [ 345.209617] raw fault status: 0x800002C1
> > > [ 345.209617] decoded fault status: SLAVE FAULT
> > > [ 345.209617] exception type 0xC1: TRANSLATION_FAULT_LEVEL1
> > > [ 345.209617] access type 0x2: READ
> > > [ 345.209617] source id 0x8000
> > > [ 345.729957] panfrost 1800000.gpu: gpu sched timeout, js=0,
> > > status=0x8, head=0x2400400, tail=0x2400400, sched_job=000000009e204de9
> > > [ 346.055876] panfrost 1800000.gpu: mmu irq status=1
> > > [ 346.060680] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
> > > 0x0000000002C00A00
> > > [ 346.060680] Reason: TODO
> > > [ 346.060680] raw fault status: 0x810002C1
> > > [ 346.060680] decoded fault status: SLAVE FAULT
> > > [ 346.060680] exception type 0xC1: TRANSLATION_FAULT_LEVEL1
> > > [ 346.060680] access type 0x2: READ
> > > [ 346.060680] source id 0x8100
> > > [ 346.561955] panfrost 1800000.gpu: gpu sched timeout, js=1,
> > > status=0x8, head=0x2c00a00, tail=0x2c00a00, sched_job=00000000b55a9a85
> > > [ 346.573913] panfrost 1800000.gpu: mmu irq status=1
> > > [ 346.578707] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
> > > 0x0000000002C00B80
> > >
> > > Change in v5:
> > > - Remove fix indent
> > >
> > > Changes in v4:
> > > - Add bus_clock probe
> > > - Fix sanity check in io-pgtable
> > > - Add vramp-delay
> > > - Merge all boards into one patch
> > > - Remove upstreamed Neil A. patch
> > >
> > > Change in v3 (Thanks to Maxime Ripard):
> > > - Reauthor Icenowy for her path
> > >
> > > Changes in v2 (Thanks to Maxime Ripard):
> > > - Drop GPU OPP Table
> > > - Add clocks and clock-names in required
> > >
> > > Clément Péron (5):
> > > drm: panfrost: add optional bus_clock
> > > iommu: io-pgtable: fix sanity check for non 48-bit mali iommu
> > > dt-bindings: gpu: mali-midgard: Add H6 mali gpu compatible
> > > arm64: dts: allwinner: Add ARM Mali GPU node for H6
> > > arm64: dts: allwinner: Add mali GPU supply for H6 boards
> > >
> > > Icenowy Zheng (1):
> > > dt-bindings: gpu: add bus clock for Mali Midgard GPUs
> >
> > I've applied patches 1 and 3 to drm-misc. I was going to do patch 4
> > too, but it doesn't apply.
>
> Thanks,
>
> I have tried to applied on drm-misc/for-linux-next but it doesn't apply too.
> It looks like commit d5ff1adb3809e2f74a3b57cea2e57c8e37d693c4 is
> missing on drm-misc ?
> https://github.com/torvalds/linux/commit/d5ff1adb3809e2f74a3b57cea2e57c8e37d693c4#diff-c3172f5d421d492ff91d7bb44dd44917

5.2-rc1 is merged in now and I've applied patch 4.

Rob

2019-05-24 17:28:08

[permalink] [raw]

Subject: Re: [PATCH v6 0/6] Allwinner H6 Mali GPU support

On 21/05/2019 17:10, Clément Péron wrote:
> Hi,
>
> The Allwinner H6 has a Mali-T720 MP2 which should be supported by
> the new panfrost driver. This series fix two issues and introduce the
> dt-bindings but a simple benchmark show that it's still NOT WORKING.
>
> I'm pushing it in case someone want to continue the work.
>
> This has been tested with Mesa3D 19.1.0-RC2 and a GPU bitness patch[1].
>
> One patch is from Icenowy Zheng where I changed the order as required
> by Rob Herring[2].
>
> Thanks,
> Clement
>
> [1] https://gitlab.freedesktop.org/kszaq/mesa/tree/panfrost_64_32
> [2] https://patchwork.kernel.org/patch/10699829/
>
>
> [ 345.204813] panfrost 1800000.gpu: mmu irq status=1
> [ 345.209617] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
> 0x0000000002400400
> [ 345.209617] Reason: TODO
> [ 345.209617] raw fault status: 0x800002C1
> [ 345.209617] decoded fault status: SLAVE FAULT
> [ 345.209617] exception type 0xC1: TRANSLATION_FAULT_LEVEL1
> [ 345.209617] access type 0x2: READ
> [ 345.209617] source id 0x8000
> [ 345.729957] panfrost 1800000.gpu: gpu sched timeout, js=0,
> status=0x8, head=0x2400400, tail=0x2400400, sched_job=000000009e204de9
> [ 346.055876] panfrost 1800000.gpu: mmu irq status=1
> [ 346.060680] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
> 0x0000000002C00A00
> [ 346.060680] Reason: TODO
> [ 346.060680] raw fault status: 0x810002C1
> [ 346.060680] decoded fault status: SLAVE FAULT
> [ 346.060680] exception type 0xC1: TRANSLATION_FAULT_LEVEL1
> [ 346.060680] access type 0x2: READ
> [ 346.060680] source id 0x8100
> [ 346.561955] panfrost 1800000.gpu: gpu sched timeout, js=1,
> status=0x8, head=0x2c00a00, tail=0x2c00a00, sched_job=00000000b55a9a85
> [ 346.573913] panfrost 1800000.gpu: mmu irq status=1
> [ 346.578707] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
> 0x0000000002C00B80

FWIW I seem to have reproduced the same behaviour on a different T720
setup, so this may well be more about the GPU than the platform. There
doesn't look to be anything obviously wrong with the pagetables, but if
I can find some more free time I may have a bit more of a poke around.

Robin.

>
> Change in v5:
> - Remove fix indent
>
> Changes in v4:
> - Add bus_clock probe
> - Fix sanity check in io-pgtable
> - Add vramp-delay
> - Merge all boards into one patch
> - Remove upstreamed Neil A. patch
>
> Change in v3 (Thanks to Maxime Ripard):
> - Reauthor Icenowy for her path
>
> Changes in v2 (Thanks to Maxime Ripard):
> - Drop GPU OPP Table
> - Add clocks and clock-names in required
>
> Clément Péron (5):
> drm: panfrost: add optional bus_clock
> iommu: io-pgtable: fix sanity check for non 48-bit mali iommu
> dt-bindings: gpu: mali-midgard: Add H6 mali gpu compatible
> arm64: dts: allwinner: Add ARM Mali GPU node for H6
> arm64: dts: allwinner: Add mali GPU supply for H6 boards
>
> Icenowy Zheng (1):
> dt-bindings: gpu: add bus clock for Mali Midgard GPUs
>
> .../bindings/gpu/arm,mali-midgard.txt | 15 ++++++++++++-
> .../dts/allwinner/sun50i-h6-beelink-gs1.dts | 6 +++++
> .../dts/allwinner/sun50i-h6-orangepi-3.dts | 6 +++++
> .../dts/allwinner/sun50i-h6-orangepi.dtsi | 6 +++++
> .../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 6 +++++
> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 14 ++++++++++++
> drivers/gpu/drm/panfrost/panfrost_device.c | 22 +++++++++++++++++++
> drivers/gpu/drm/panfrost/panfrost_device.h | 1 +
> drivers/iommu/io-pgtable-arm.c | 2 +-
> 9 files changed, 76 insertions(+), 2 deletions(-)
>

2019-05-29 15:11:32

[permalink] [raw]

Subject: Re: [PATCH v6 0/6] Allwinner H6 Mali GPU support

On Tue, 21 May 2019 at 18:11, Clément Péron <[email protected]> wrote:
>
[snip]
> [ 345.204813] panfrost 1800000.gpu: mmu irq status=1
> [ 345.209617] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
> 0x0000000002400400

From what I can see here, 0x0000000002400400 points to the first byte
of the first submitted job descriptor.

So mapping buffers for the GPU doesn't seem to be working at all on
64-bit T-760.

Steven, Robin, do you have any idea of why this could be?

Thanks,

Tomeu

2019-05-29 15:35:06

[permalink] [raw]

Subject: [PATCH] arm64: dts: allwinner: Add GPU operating points for H6

The GPU driver needs them to change the clock frequency and regulator
voltage depending on the load.

Signed-off-by: Tomeu Vizoso <[email protected]>
Cc: Clément Péron <[email protected]>

---

Feel free to pick up this patch if you are going to keep pushing this
series forward.

Thanks,

Tomeu
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 66 ++++++++++++++++++++
1 file changed, 66 insertions(+)

diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 6aad06095c40..decf7b56e2df 100644
--- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
+++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
@@ -157,6 +157,71 @@
allwinner,sram = <&ve_sram 1>;
};

+ gpu_opp_table: opp-table2 {
+ compatible = "operating-points-v2";
+
+ opp00 {
+ opp-hz = /bits/ 64 <756000000>;
+ opp-microvolt = <1040000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <624000000>;
+ opp-microvolt = <950000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <576000000>;
+ opp-microvolt = <930000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <540000000>;
+ opp-microvolt = <910000>;
+ };
+ opp04 {
+ opp-hz = /bits/ 64 <504000000>;
+ opp-microvolt = <890000>;
+ };
+ opp05 {
+ opp-hz = /bits/ 64 <456000000>;
+ opp-microvolt = <870000>;
+ };
+ opp06 {
+ opp-hz = /bits/ 64 <432000000>;
+ opp-microvolt = <860000>;
+ };
+ opp07 {
+ opp-hz = /bits/ 64 <420000000>;
+ opp-microvolt = <850000>;
+ };
+ opp08 {
+ opp-hz = /bits/ 64 <408000000>;
+ opp-microvolt = <840000>;
+ };
+ opp09 {
+ opp-hz = /bits/ 64 <384000000>;
+ opp-microvolt = <830000>;
+ };
+ opp10 {
+ opp-hz = /bits/ 64 <360000000>;
+ opp-microvolt = <820000>;
+ };
+ opp11 {
+ opp-hz = /bits/ 64 <336000000>;
+ opp-microvolt = <810000>;
+ };
+ opp12 {
+ opp-hz = /bits/ 64 <312000000>;
+ opp-microvolt = <810000>;
+ };
+ opp13 {
+ opp-hz = /bits/ 64 <264000000>;
+ opp-microvolt = <810000>;
+ };
+ opp14 {
+ opp-hz = /bits/ 64 <216000000>;
+ opp-microvolt = <810000>;
+ };
+ };
+
gpu: gpu@1800000 {
compatible = "allwinner,sun50i-h6-mali",
"arm,mali-t720";
@@ -168,6 +233,7 @@
clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>;
clock-names = "core", "bus";
resets = <&ccu RST_BUS_GPU>;
+ operating-points-v2 = <&gpu_opp_table>;
status = "disabled";
};

--
2.20.1

2019-05-29 15:39:50

[permalink] [raw]

Subject: Re: [PATCH] arm64: dts: allwinner: Add GPU operating points for H6

Hi Tomeu,

On Wed, 29 May 2019 at 17:33, Tomeu Vizoso <[email protected]> wrote:
>
> The GPU driver needs them to change the clock frequency and regulator
> voltage depending on the load.

As requested by Maxime, I have dropped these OPP table as It's taken
from vendor and untested with Panfrost.

https://lore.kernel.org/patchwork/patch/1060374/

Regards,
Clément

>
> Signed-off-by: Tomeu Vizoso <[email protected]>
> Cc: Clément Péron <[email protected]>
>
> ---
>
> Feel free to pick up this patch if you are going to keep pushing this
> series forward.
>
> Thanks,
>
> Tomeu
> ---
> arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 66 ++++++++++++++++++++
> 1 file changed, 66 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> index 6aad06095c40..decf7b56e2df 100644
> --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> @@ -157,6 +157,71 @@
> allwinner,sram = <&ve_sram 1>;
> };
>
> + gpu_opp_table: opp-table2 {
> + compatible = "operating-points-v2";
> +
> + opp00 {
> + opp-hz = /bits/ 64 <756000000>;
> + opp-microvolt = <1040000>;
> + };
> + opp01 {
> + opp-hz = /bits/ 64 <624000000>;
> + opp-microvolt = <950000>;
> + };
> + opp02 {
> + opp-hz = /bits/ 64 <576000000>;
> + opp-microvolt = <930000>;
> + };
> + opp03 {
> + opp-hz = /bits/ 64 <540000000>;
> + opp-microvolt = <910000>;
> + };
> + opp04 {
> + opp-hz = /bits/ 64 <504000000>;
> + opp-microvolt = <890000>;
> + };
> + opp05 {
> + opp-hz = /bits/ 64 <456000000>;
> + opp-microvolt = <870000>;
> + };
> + opp06 {
> + opp-hz = /bits/ 64 <432000000>;
> + opp-microvolt = <860000>;
> + };
> + opp07 {
> + opp-hz = /bits/ 64 <420000000>;
> + opp-microvolt = <850000>;
> + };
> + opp08 {
> + opp-hz = /bits/ 64 <408000000>;
> + opp-microvolt = <840000>;
> + };
> + opp09 {
> + opp-hz = /bits/ 64 <384000000>;
> + opp-microvolt = <830000>;
> + };
> + opp10 {
> + opp-hz = /bits/ 64 <360000000>;
> + opp-microvolt = <820000>;
> + };
> + opp11 {
> + opp-hz = /bits/ 64 <336000000>;
> + opp-microvolt = <810000>;
> + };
> + opp12 {
> + opp-hz = /bits/ 64 <312000000>;
> + opp-microvolt = <810000>;
> + };
> + opp13 {
> + opp-hz = /bits/ 64 <264000000>;
> + opp-microvolt = <810000>;
> + };
> + opp14 {
> + opp-hz = /bits/ 64 <216000000>;
> + opp-microvolt = <810000>;
> + };
> + };
> +
> gpu: gpu@1800000 {
> compatible = "allwinner,sun50i-h6-mali",
> "arm,mali-t720";
> @@ -168,6 +233,7 @@
> clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>;
> clock-names = "core", "bus";
> resets = <&ccu RST_BUS_GPU>;
> + operating-points-v2 = <&gpu_opp_table>;
> status = "disabled";
> };
>
> --
> 2.20.1
>

2019-05-29 15:44:49

[permalink] [raw]

Subject: Re: [PATCH] arm64: dts: allwinner: Add GPU operating points for H6

On Wed, 29 May 2019 at 17:37, Clément Péron <[email protected]> wrote:
>
> Hi Tomeu,
>
> On Wed, 29 May 2019 at 17:33, Tomeu Vizoso <[email protected]> wrote:
> >
> > The GPU driver needs them to change the clock frequency and regulator
> > voltage depending on the load.
>
> As requested by Maxime, I have dropped these OPP table as It's taken
> from vendor and untested with Panfrost.
>
> https://lore.kernel.org/patchwork/patch/1060374/

Ok, guess this series should wait then until we can run Panfrost on it
and check how DVFS is working.

Thanks,

Tomeu

> Regards,
> Clément
>
> >
> > Signed-off-by: Tomeu Vizoso <[email protected]>
> > Cc: Clément Péron <[email protected]>
> >
> > ---
> >
> > Feel free to pick up this patch if you are going to keep pushing this
> > series forward.
> >
> > Thanks,
> >
> > Tomeu
> > ---
> > arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 66 ++++++++++++++++++++
> > 1 file changed, 66 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > index 6aad06095c40..decf7b56e2df 100644
> > --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
> > @@ -157,6 +157,71 @@
> > allwinner,sram = <&ve_sram 1>;
> > };
> >
> > + gpu_opp_table: opp-table2 {
> > + compatible = "operating-points-v2";
> > +
> > + opp00 {
> > + opp-hz = /bits/ 64 <756000000>;
> > + opp-microvolt = <1040000>;
> > + };
> > + opp01 {
> > + opp-hz = /bits/ 64 <624000000>;
> > + opp-microvolt = <950000>;
> > + };
> > + opp02 {
> > + opp-hz = /bits/ 64 <576000000>;
> > + opp-microvolt = <930000>;
> > + };
> > + opp03 {
> > + opp-hz = /bits/ 64 <540000000>;
> > + opp-microvolt = <910000>;
> > + };
> > + opp04 {
> > + opp-hz = /bits/ 64 <504000000>;
> > + opp-microvolt = <890000>;
> > + };
> > + opp05 {
> > + opp-hz = /bits/ 64 <456000000>;
> > + opp-microvolt = <870000>;
> > + };
> > + opp06 {
> > + opp-hz = /bits/ 64 <432000000>;
> > + opp-microvolt = <860000>;
> > + };
> > + opp07 {
> > + opp-hz = /bits/ 64 <420000000>;
> > + opp-microvolt = <850000>;
> > + };
> > + opp08 {
> > + opp-hz = /bits/ 64 <408000000>;
> > + opp-microvolt = <840000>;
> > + };
> > + opp09 {
> > + opp-hz = /bits/ 64 <384000000>;
> > + opp-microvolt = <830000>;
> > + };
> > + opp10 {
> > + opp-hz = /bits/ 64 <360000000>;
> > + opp-microvolt = <820000>;
> > + };
> > + opp11 {
> > + opp-hz = /bits/ 64 <336000000>;
> > + opp-microvolt = <810000>;
> > + };
> > + opp12 {
> > + opp-hz = /bits/ 64 <312000000>;
> > + opp-microvolt = <810000>;
> > + };
> > + opp13 {
> > + opp-hz = /bits/ 64 <264000000>;
> > + opp-microvolt = <810000>;
> > + };
> > + opp14 {
> > + opp-hz = /bits/ 64 <216000000>;
> > + opp-microvolt = <810000>;
> > + };
> > + };
> > +
> > gpu: gpu@1800000 {
> > compatible = "allwinner,sun50i-h6-mali",
> > "arm,mali-t720";
> > @@ -168,6 +233,7 @@
> > clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>;
> > clock-names = "core", "bus";
> > resets = <&ccu RST_BUS_GPU>;
> > + operating-points-v2 = <&gpu_opp_table>;
> > status = "disabled";
> > };
> >
> > --
> > 2.20.1
> >

2019-05-29 17:40:31

[permalink] [raw]

Subject: Re: [PATCH v6 0/6] Allwinner H6 Mali GPU support

On 29/05/2019 16:09, Tomeu Vizoso wrote:
> On Tue, 21 May 2019 at 18:11, Clément Péron <[email protected]> wrote:
>>
> [snip]
>> [ 345.204813] panfrost 1800000.gpu: mmu irq status=1
>> [ 345.209617] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
>> 0x0000000002400400
>
> From what I can see here, 0x0000000002400400 points to the first byte
> of the first submitted job descriptor.
>
> So mapping buffers for the GPU doesn't seem to be working at all on
> 64-bit T-760.
>
> Steven, Robin, do you have any idea of why this could be?

I tried rolling back to the old panfrost/nondrm shim, and it works fine
with kbase, and I also found that T-820 falls over in the exact same
manner, so the fact that it seemed to be common to the smaller 33-bit
designs rather than anything to do with the other
job_descriptor_size/v4/v5 complication turned out to be telling.

[ as an aside, are 64-bit jobs actually known not to work on v4 GPUs, or
is it just that nobody's yet observed a 64-bit blob driving one? ]

Long story short, it appears that 'Mali LPAE' is also lacking the start
level notion of VMSA, and expects a full 4-level table even for <40 bits
when level 0 effectively redundant. Thus walking the 3-level table that
io-pgtable comes back with ends up going wildly wrong. The hack below
seems to do the job for me; if Clément can confirm (on T-720 you'll
still need the userspace hack to force 32-bit jobs as well) then I think
I'll cook up a proper refactoring of the allocator to put things right.

Robin.

----->8-----
diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
index 546968d8a349..f29da6e8dc08 100644
--- a/drivers/iommu/io-pgtable-arm.c
+++ b/drivers/iommu/io-pgtable-arm.c
@@ -1023,12 +1023,14 @@ arm_mali_lpae_alloc_pgtable(struct
io_pgtable_cfg *cfg, void *cookie)
iop = arm_64_lpae_alloc_pgtable_s1(cfg, cookie);
if (iop) {
u64 mair, ttbr;
+ struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(&iop->ops);

+ data->levels = 4;
/* Copy values as union fields overlap */
mair = cfg->arm_lpae_s1_cfg.mair[0];
ttbr = cfg->arm_lpae_s1_cfg.ttbr[0];

2019-05-31 12:07:01

[permalink] [raw]

Subject: Re: [PATCH v6 0/6] Allwinner H6 Mali GPU support

On Wed, 29 May 2019 at 19:38, Robin Murphy <[email protected]> wrote:
>
> On 29/05/2019 16:09, Tomeu Vizoso wrote:
> > On Tue, 21 May 2019 at 18:11, Clément Péron <[email protected]> wrote:
> >>
> > [snip]
> >> [ 345.204813] panfrost 1800000.gpu: mmu irq status=1
> >> [ 345.209617] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
> >> 0x0000000002400400
> >
> > From what I can see here, 0x0000000002400400 points to the first byte
> > of the first submitted job descriptor.
> >
> > So mapping buffers for the GPU doesn't seem to be working at all on
> > 64-bit T-760.
> >
> > Steven, Robin, do you have any idea of why this could be?
>
> I tried rolling back to the old panfrost/nondrm shim, and it works fine
> with kbase, and I also found that T-820 falls over in the exact same
> manner, so the fact that it seemed to be common to the smaller 33-bit
> designs rather than anything to do with the other
> job_descriptor_size/v4/v5 complication turned out to be telling.

Is this complication something you can explain? I don't know what v4
and v5 are meant here.

> [ as an aside, are 64-bit jobs actually known not to work on v4 GPUs, or
> is it just that nobody's yet observed a 64-bit blob driving one? ]

I'm looking right now at getting Panfrost working on T720 with 64-bit
descriptors, with the ultimate goal of making Panfrost
64-bit-descriptor only so we can have a single build of Mesa in
distros.

> Long story short, it appears that 'Mali LPAE' is also lacking the start
> level notion of VMSA, and expects a full 4-level table even for <40 bits
> when level 0 effectively redundant. Thus walking the 3-level table that
> io-pgtable comes back with ends up going wildly wrong. The hack below
> seems to do the job for me; if Clément can confirm (on T-720 you'll
> still need the userspace hack to force 32-bit jobs as well) then I think
> I'll cook up a proper refactoring of the allocator to put things right.

Mmaps seem to work with this patch, thanks.

The main complication I'm facing right now seems to be that the SFBD
descriptor on T720 seems to be different from the one we already had
(tested on T6xx?).

Cheers,

Tomeu

> Robin.
>
>
> ----->8-----
> diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
> index 546968d8a349..f29da6e8dc08 100644
> --- a/drivers/iommu/io-pgtable-arm.c
> +++ b/drivers/iommu/io-pgtable-arm.c
> @@ -1023,12 +1023,14 @@ arm_mali_lpae_alloc_pgtable(struct
> io_pgtable_cfg *cfg, void *cookie)
> iop = arm_64_lpae_alloc_pgtable_s1(cfg, cookie);
> if (iop) {
> u64 mair, ttbr;
> + struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(&iop->ops);
>
> + data->levels = 4;
> /* Copy values as union fields overlap */
> mair = cfg->arm_lpae_s1_cfg.mair[0];
> ttbr = cfg->arm_lpae_s1_cfg.ttbr[0];
>
> _______________________________________________
> dri-devel mailing list
> [email protected]
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

2019-05-31 13:48:58

[permalink] [raw]

Subject: Re: [PATCH v6 0/6] Allwinner H6 Mali GPU support

On 31/05/2019 13:04, Tomeu Vizoso wrote:
> On Wed, 29 May 2019 at 19:38, Robin Murphy <[email protected]> wrote:
>>
>> On 29/05/2019 16:09, Tomeu Vizoso wrote:
>>> On Tue, 21 May 2019 at 18:11, Clément Péron <[email protected]> wrote:
>>>>
>>> [snip]
>>>> [ 345.204813] panfrost 1800000.gpu: mmu irq status=1
>>>> [ 345.209617] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
>>>> 0x0000000002400400
>>>
>>> From what I can see here, 0x0000000002400400 points to the first byte
>>> of the first submitted job descriptor.
>>>
>>> So mapping buffers for the GPU doesn't seem to be working at all on
>>> 64-bit T-760.
>>>
>>> Steven, Robin, do you have any idea of why this could be?
>>
>> I tried rolling back to the old panfrost/nondrm shim, and it works fine
>> with kbase, and I also found that T-820 falls over in the exact same
>> manner, so the fact that it seemed to be common to the smaller 33-bit
>> designs rather than anything to do with the other
>> job_descriptor_size/v4/v5 complication turned out to be telling.
>
> Is this complication something you can explain? I don't know what v4
> and v5 are meant here.

I was alluding to BASE_HW_FEATURE_V4, which I believe refers to the
Midgard architecture version - the older versions implemented by T6xx
and T720 seem to be collectively treated as "v4", while T760 and T8xx
would effectively be "v5".

>> [ as an aside, are 64-bit jobs actually known not to work on v4 GPUs, or
>> is it just that nobody's yet observed a 64-bit blob driving one? ]
>
> I'm looking right now at getting Panfrost working on T720 with 64-bit
> descriptors, with the ultimate goal of making Panfrost
> 64-bit-descriptor only so we can have a single build of Mesa in
> distros.

Cool, I'll keep an eye out, and hope that it might be enough for T620 on
Juno, too :)

>> Long story short, it appears that 'Mali LPAE' is also lacking the start
>> level notion of VMSA, and expects a full 4-level table even for <40 bits
>> when level 0 effectively redundant. Thus walking the 3-level table that
>> io-pgtable comes back with ends up going wildly wrong. The hack below
>> seems to do the job for me; if Clément can confirm (on T-720 you'll
>> still need the userspace hack to force 32-bit jobs as well) then I think
>> I'll cook up a proper refactoring of the allocator to put things right.
>
> Mmaps seem to work with this patch, thanks.
>
> The main complication I'm facing right now seems to be that the SFBD
> descriptor on T720 seems to be different from the one we already had
> (tested on T6xx?).

OK - with the 32-bit hack pointed to up-thread, a quick kmscube test
gave me the impression that T720 works fine, but on closer inspection
some parts of glmark2 do seem to go a bit wonky (although I suspect at
least some of it is just down to the FPGA setup being both very slow and
lacking in memory bandwidth), and the "nv12-1img" mode of kmscube turns
out to render in some delightfully wrong colours.

I'll try to get a 'proper' version of the io-pgtable patch posted soon.

Thanks,
Robin.

>
> Cheers,
>
> Tomeu
>
>> Robin.
>>
>>
>> ----->8-----
>> diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
>> index 546968d8a349..f29da6e8dc08 100644
>> --- a/drivers/iommu/io-pgtable-arm.c
>> +++ b/drivers/iommu/io-pgtable-arm.c
>> @@ -1023,12 +1023,14 @@ arm_mali_lpae_alloc_pgtable(struct
>> io_pgtable_cfg *cfg, void *cookie)
>> iop = arm_64_lpae_alloc_pgtable_s1(cfg, cookie);
>> if (iop) {
>> u64 mair, ttbr;
>> + struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(&iop->ops);
>>
>> + data->levels = 4;
>> /* Copy values as union fields overlap */
>> mair = cfg->arm_lpae_s1_cfg.mair[0];
>> ttbr = cfg->arm_lpae_s1_cfg.ttbr[0];
>>
>> _______________________________________________
>> dri-devel mailing list
>> [email protected]
>> https://lists.freedesktop.org/mailman/listinfo/dri-devel

2019-06-03 17:55:43

[permalink] [raw]

Subject: Re: [PATCH v6 0/6] Allwinner H6 Mali GPU support

Hi Maxime, Joerg,

On Wed, 22 May 2019 at 21:27, Rob Herring <[email protected]> wrote:
>
> On Tue, May 21, 2019 at 11:11 AM Clément Péron <[email protected]> wrote:
> >
> > Hi,
> >
> > The Allwinner H6 has a Mali-T720 MP2 which should be supported by
> > the new panfrost driver. This series fix two issues and introduce the
> > dt-bindings but a simple benchmark show that it's still NOT WORKING.
> >
> > I'm pushing it in case someone want to continue the work.
> >
> > This has been tested with Mesa3D 19.1.0-RC2 and a GPU bitness patch[1].
> >
> > One patch is from Icenowy Zheng where I changed the order as required
> > by Rob Herring[2].
> >
> > Thanks,
> > Clement
> >
> > [1] https://gitlab.freedesktop.org/kszaq/mesa/tree/panfrost_64_32
> > [2] https://patchwork.kernel.org/patch/10699829/
> >
> >
> > [ 345.204813] panfrost 1800000.gpu: mmu irq status=1
> > [ 345.209617] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
> > 0x0000000002400400
> > [ 345.209617] Reason: TODO
> > [ 345.209617] raw fault status: 0x800002C1
> > [ 345.209617] decoded fault status: SLAVE FAULT
> > [ 345.209617] exception type 0xC1: TRANSLATION_FAULT_LEVEL1
> > [ 345.209617] access type 0x2: READ
> > [ 345.209617] source id 0x8000
> > [ 345.729957] panfrost 1800000.gpu: gpu sched timeout, js=0,
> > status=0x8, head=0x2400400, tail=0x2400400, sched_job=000000009e204de9
> > [ 346.055876] panfrost 1800000.gpu: mmu irq status=1
> > [ 346.060680] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
> > 0x0000000002C00A00
> > [ 346.060680] Reason: TODO
> > [ 346.060680] raw fault status: 0x810002C1
> > [ 346.060680] decoded fault status: SLAVE FAULT
> > [ 346.060680] exception type 0xC1: TRANSLATION_FAULT_LEVEL1
> > [ 346.060680] access type 0x2: READ
> > [ 346.060680] source id 0x8100
> > [ 346.561955] panfrost 1800000.gpu: gpu sched timeout, js=1,
> > status=0x8, head=0x2c00a00, tail=0x2c00a00, sched_job=00000000b55a9a85
> > [ 346.573913] panfrost 1800000.gpu: mmu irq status=1
> > [ 346.578707] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
> > 0x0000000002C00B80
> >
> > Change in v5:
> > - Remove fix indent
> >
> > Changes in v4:
> > - Add bus_clock probe
> > - Fix sanity check in io-pgtable
> > - Add vramp-delay
> > - Merge all boards into one patch
> > - Remove upstreamed Neil A. patch
> >
> > Change in v3 (Thanks to Maxime Ripard):
> > - Reauthor Icenowy for her path
> >
> > Changes in v2 (Thanks to Maxime Ripard):
> > - Drop GPU OPP Table
> > - Add clocks and clock-names in required
> >
> > Clément Péron (5):
> > drm: panfrost: add optional bus_clock
> > iommu: io-pgtable: fix sanity check for non 48-bit mali iommu
> > dt-bindings: gpu: mali-midgard: Add H6 mali gpu compatible
> > arm64: dts: allwinner: Add ARM Mali GPU node for H6
> > arm64: dts: allwinner: Add mali GPU supply for H6 boards
> >
> > Icenowy Zheng (1):
> > dt-bindings: gpu: add bus clock for Mali Midgard GPUs
>
> I've applied patches 1 and 3 to drm-misc. I was going to do patch 4
> too, but it doesn't apply.
>
> Patch 2 can go in via the iommu tree and the rest via the allwinner tree.

Is this OK for you to pick up this series?

Thanks,
Clément

>
> Rob

2019-06-10 13:40:38

[permalink] [raw]

Subject: Re: [PATCH v6 0/6] Allwinner H6 Mali GPU support

On Wed, 29 May 2019 at 19:38, Robin Murphy <[email protected]> wrote:
>
> On 29/05/2019 16:09, Tomeu Vizoso wrote:
> > On Tue, 21 May 2019 at 18:11, Clément Péron <[email protected]> wrote:
> >>
> > [snip]
> >> [ 345.204813] panfrost 1800000.gpu: mmu irq status=1
> >> [ 345.209617] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
> >> 0x0000000002400400
> >
> > From what I can see here, 0x0000000002400400 points to the first byte
> > of the first submitted job descriptor.
> >
> > So mapping buffers for the GPU doesn't seem to be working at all on
> > 64-bit T-760.
> >
> > Steven, Robin, do you have any idea of why this could be?
>
> I tried rolling back to the old panfrost/nondrm shim, and it works fine
> with kbase, and I also found that T-820 falls over in the exact same
> manner, so the fact that it seemed to be common to the smaller 33-bit
> designs rather than anything to do with the other
> job_descriptor_size/v4/v5 complication turned out to be telling.
>
> [ as an aside, are 64-bit jobs actually known not to work on v4 GPUs, or
> is it just that nobody's yet observed a 64-bit blob driving one? ]

Do you know if 64-bit descriptors work on v4 GPUs with our kernel
driver but with the DDK?

Wonder if there something else to be fixed in the kernel for that scenario.

Thanks,

Tomeu

> Long story short, it appears that 'Mali LPAE' is also lacking the start
> level notion of VMSA, and expects a full 4-level table even for <40 bits
> when level 0 effectively redundant. Thus walking the 3-level table that
> io-pgtable comes back with ends up going wildly wrong. The hack below
> seems to do the job for me; if Clément can confirm (on T-720 you'll
> still need the userspace hack to force 32-bit jobs as well) then I think
> I'll cook up a proper refactoring of the allocator to put things right.
>
> Robin.
>
>
> ----->8-----
> diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
> index 546968d8a349..f29da6e8dc08 100644
> --- a/drivers/iommu/io-pgtable-arm.c
> +++ b/drivers/iommu/io-pgtable-arm.c
> @@ -1023,12 +1023,14 @@ arm_mali_lpae_alloc_pgtable(struct
> io_pgtable_cfg *cfg, void *cookie)
> iop = arm_64_lpae_alloc_pgtable_s1(cfg, cookie);
> if (iop) {
> u64 mair, ttbr;
> + struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(&iop->ops);
>
> + data->levels = 4;
> /* Copy values as union fields overlap */
> mair = cfg->arm_lpae_s1_cfg.mair[0];
> ttbr = cfg->arm_lpae_s1_cfg.ttbr[0];
>
> _______________________________________________
> dri-devel mailing list
> [email protected]
> https://lists.freedesktop.org/mailman/listinfo/dri-devel

2019-08-28 11:30:46

by Neil Armstrong

[permalink] [raw]

Subject: Re: [PATCH v6 0/6] Allwinner H6 Mali GPU support

Hi Robyn,

On 31/05/2019 15:47, Robin Murphy wrote:
> On 31/05/2019 13:04, Tomeu Vizoso wrote:
>> On Wed, 29 May 2019 at 19:38, Robin Murphy <[email protected]> wrote:
>>>
>>> On 29/05/2019 16:09, Tomeu Vizoso wrote:
>>>> On Tue, 21 May 2019 at 18:11, Clément Péron <[email protected]> wrote:
>>>>>
>>>> [snip]
>>>>> [ 345.204813] panfrost 1800000.gpu: mmu irq status=1
>>>>> [ 345.209617] panfrost 1800000.gpu: Unhandled Page fault in AS0 at VA
>>>>> 0x0000000002400400
>>>>
>>>> From what I can see here, 0x0000000002400400 points to the first byte
>>>> of the first submitted job descriptor.
>>>>
>>>> So mapping buffers for the GPU doesn't seem to be working at all on
>>>> 64-bit T-760.
>>>>
>>>> Steven, Robin, do you have any idea of why this could be?
>>>
>>> I tried rolling back to the old panfrost/nondrm shim, and it works fine
>>> with kbase, and I also found that T-820 falls over in the exact same
>>> manner, so the fact that it seemed to be common to the smaller 33-bit
>>> designs rather than anything to do with the other
>>> job_descriptor_size/v4/v5 complication turned out to be telling.
>>
>> Is this complication something you can explain? I don't know what v4
>> and v5 are meant here.
>
> I was alluding to BASE_HW_FEATURE_V4, which I believe refers to the Midgard architecture version - the older versions implemented by T6xx and T720 seem to be collectively treated as "v4", while T760 and T8xx would effectively be "v5".
>
>>> [ as an aside, are 64-bit jobs actually known not to work on v4 GPUs, or
>>> is it just that nobody's yet observed a 64-bit blob driving one? ]
>>
>> I'm looking right now at getting Panfrost working on T720 with 64-bit
>> descriptors, with the ultimate goal of making Panfrost
>> 64-bit-descriptor only so we can have a single build of Mesa in
>> distros.
>
> Cool, I'll keep an eye out, and hope that it might be enough for T620 on Juno, too :)
>
>>> Long story short, it appears that 'Mali LPAE' is also lacking the start
>>> level notion of VMSA, and expects a full 4-level table even for <40 bits
>>> when level 0 effectively redundant. Thus walking the 3-level table that
>>> io-pgtable comes back with ends up going wildly wrong. The hack below
>>> seems to do the job for me; if Clément can confirm (on T-720 you'll
>>> still need the userspace hack to force 32-bit jobs as well) then I think
>>> I'll cook up a proper refactoring of the allocator to put things right.
>>
>> Mmaps seem to work with this patch, thanks.
>>
>> The main complication I'm facing right now seems to be that the SFBD
>> descriptor on T720 seems to be different from the one we already had
>> (tested on T6xx?).
>
> OK - with the 32-bit hack pointed to up-thread, a quick kmscube test gave me the impression that T720 works fine, but on closer inspection some parts of glmark2 do seem to go a bit wonky (although I suspect at least some of it is just down to the FPGA setup being both very slow and lacking in memory bandwidth), and the "nv12-1img" mode of kmscube turns out to render in some delightfully wrong colours.
>
> I'll try to get a 'proper' version of the io-pgtable patch posted soon.

I'm trying to collect all the fixes needed to make T820 work again, and
I was wondering if you finally have a proper patch for this and "cfg->ias > 48"
hack ? Or one I can test ?

Thanks,
Neil

>
> Thanks,
> Robin.
>
>>
>> Cheers,
>>
>> Tomeu
>>
>>> Robin.
>>>
>>>
>>> ----->8-----
>>> diff --git a/drivers/iommu/io-pgtable-arm.c b/drivers/iommu/io-pgtable-arm.c
>>> index 546968d8a349..f29da6e8dc08 100644
>>> --- a/drivers/iommu/io-pgtable-arm.c
>>> +++ b/drivers/iommu/io-pgtable-arm.c
>>> @@ -1023,12 +1023,14 @@ arm_mali_lpae_alloc_pgtable(struct
>>> io_pgtable_cfg *cfg, void *cookie)
>>>          iop = arm_64_lpae_alloc_pgtable_s1(cfg, cookie);
>>>          if (iop) {
>>>                  u64 mair, ttbr;
>>> +               struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(&iop->ops);
>>>
>>> +               data->levels = 4;
>>>                  /* Copy values as union fields overlap */
>>>                  mair = cfg->arm_lpae_s1_cfg.mair[0];
>>>                  ttbr = cfg->arm_lpae_s1_cfg.ttbr[0];
>>>
>>> _______________________________________________
>>> dri-devel mailing list
>>> [email protected]
>>> https://lists.freedesktop.org/mailman/listinfo/dri-devel

2019-08-28 11:50:30