There are errors with cppcheck
"Shifting signed 32-bit value by 31 bits is undefined behaviour errors"
This is just a mirror changing.
Phong Tran (15):
arm: perf: cleanup cppcheck shifting error
ARM: davinci: cleanup cppcheck shifting errors
ARM: ep93xx: cleanup cppcheck shifting errors
ARM: exynos: cleanup cppcheck shifting error
ARM: footbridge: cleanup cppcheck shifting error
ARM: imx: cleanup cppcheck shifting errors
ARM: ks8695: cleanup cppcheck shifting error
ARM: mmp: cleanup cppcheck shifting errors
ARM: omap2: cleanup cppcheck shifting error
ARM: orion5x: cleanup cppcheck shifting errors
ARM: pxa: cleanup cppcheck shifting errors
ARM: vexpress: cleanup cppcheck shifting error
ARM: mm: cleanup cppcheck shifting errors
ARM: bpf: cleanup cppcheck shifting error
ARM: vfp: cleanup cppcheck shifting errors
arch/arm/kernel/perf_event_v7.c | 6 +-
arch/arm/mach-davinci/ddr2.h | 6 +-
arch/arm/mach-ep93xx/soc.h | 132 ++++++++++++++++++-------------------
arch/arm/mach-exynos/suspend.c | 2 +-
arch/arm/mach-footbridge/dc21285.c | 2 +-
arch/arm/mach-imx/iomux-mx3.h | 64 +++++++++---------
arch/arm/mach-ks8695/regs-pci.h | 4 +-
arch/arm/mach-mmp/pm-mmp2.h | 40 +++++------
arch/arm/mach-mmp/pm-pxa910.h | 76 ++++++++++-----------
arch/arm/mach-omap2/powerdomain.c | 2 +-
arch/arm/mach-orion5x/pci.c | 8 +--
arch/arm/mach-pxa/irq.c | 4 +-
arch/arm/mach-vexpress/spc.c | 12 ++--
arch/arm/mm/fault.h | 6 +-
arch/arm/net/bpf_jit_32.c | 2 +-
arch/arm/vfp/vfpinstr.h | 28 ++++----
16 files changed, 197 insertions(+), 197 deletions(-)
--
2.11.0
fix "Shifting signed 32-bit value by 31 bits is undefined behaviour
errors"
[arch/arm/kernel/perf_event_v7.c:1080]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
[arch/arm/kernel/perf_event_v7.c:1436]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
[arch/arm/kernel/perf_event_v7.c:1783]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/kernel/perf_event_v7.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index a4fb0f8b8f84..83dc472a39b2 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -697,9 +697,9 @@ static struct attribute_group armv7_pmuv2_events_attr_group = {
/*
* Event filters for PMUv2
*/
-#define ARMV7_EXCLUDE_PL1 (1 << 31)
-#define ARMV7_EXCLUDE_USER (1 << 30)
-#define ARMV7_INCLUDE_HYP (1 << 27)
+#define ARMV7_EXCLUDE_PL1 (1U << 31)
+#define ARMV7_EXCLUDE_USER (1U << 30)
+#define ARMV7_INCLUDE_HYP (1U << 27)
/*
* Secure debug enable reg
--
2.11.0
[arch/arm/mach-ep93xx/clock.c:102]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-ep93xx/clock.c:132]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-ep93xx/clock.c:140]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-ep93xx/core.c:1001]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-ep93xx/core.c:1002]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-ep93xx/soc.h | 132 ++++++++++++++++++++++-----------------------
1 file changed, 66 insertions(+), 66 deletions(-)
diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h
index f2dace1c9154..831ea5266281 100644
--- a/arch/arm/mach-ep93xx/soc.h
+++ b/arch/arm/mach-ep93xx/soc.h
@@ -109,89 +109,89 @@
#define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x))
#define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00)
#define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04)
-#define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31)
-#define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29)
-#define EP93XX_SYSCON_PWRCNT_USH_EN (1<<28)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 (1<<27)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 (1<<26)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 (1<<25)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 (1<<24)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 (1<<23)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 (1<<22)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 (1<<21)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 (1<<20)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 (1<<19)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 (1<<18)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 (1<<17)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 (1<<16)
+#define EP93XX_SYSCON_PWRCNT_FIR_EN (1U<<31)
+#define EP93XX_SYSCON_PWRCNT_UARTBAUD (1U<<29)
+#define EP93XX_SYSCON_PWRCNT_USH_EN (1U<<28)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 (1U<<27)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 (1U<<26)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 (1U<<25)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 (1U<<24)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 (1U<<23)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 (1U<<22)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 (1U<<21)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 (1U<<20)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 (1U<<19)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 (1U<<18)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 (1U<<17)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 (1U<<16)
#define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08)
#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c)
#define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20)
-#define EP93XX_SYSCON_CLKSET1_NBYP1 (1<<23)
+#define EP93XX_SYSCON_CLKSET1_NBYP1 (1U<<23)
#define EP93XX_SYSCON_CLKSET2 EP93XX_SYSCON_REG(0x24)
-#define EP93XX_SYSCON_CLKSET2_NBYP2 (1<<19)
-#define EP93XX_SYSCON_CLKSET2_PLL2_EN (1<<18)
+#define EP93XX_SYSCON_CLKSET2_NBYP2 (1U<<19)
+#define EP93XX_SYSCON_CLKSET2_PLL2_EN (1U<<18)
#define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80)
-#define EP93XX_SYSCON_DEVCFG_SWRST (1<<31)
-#define EP93XX_SYSCON_DEVCFG_D1ONG (1<<30)
-#define EP93XX_SYSCON_DEVCFG_D0ONG (1<<29)
-#define EP93XX_SYSCON_DEVCFG_IONU2 (1<<28)
-#define EP93XX_SYSCON_DEVCFG_GONK (1<<27)
-#define EP93XX_SYSCON_DEVCFG_TONG (1<<26)
-#define EP93XX_SYSCON_DEVCFG_MONG (1<<25)
-#define EP93XX_SYSCON_DEVCFG_U3EN (1<<24)
-#define EP93XX_SYSCON_DEVCFG_CPENA (1<<23)
-#define EP93XX_SYSCON_DEVCFG_A2ONG (1<<22)
-#define EP93XX_SYSCON_DEVCFG_A1ONG (1<<21)
-#define EP93XX_SYSCON_DEVCFG_U2EN (1<<20)
-#define EP93XX_SYSCON_DEVCFG_EXVC (1<<19)
-#define EP93XX_SYSCON_DEVCFG_U1EN (1<<18)
-#define EP93XX_SYSCON_DEVCFG_TIN (1<<17)
-#define EP93XX_SYSCON_DEVCFG_HC3IN (1<<15)
-#define EP93XX_SYSCON_DEVCFG_HC3EN (1<<14)
-#define EP93XX_SYSCON_DEVCFG_HC1IN (1<<13)
-#define EP93XX_SYSCON_DEVCFG_HC1EN (1<<12)
-#define EP93XX_SYSCON_DEVCFG_HONIDE (1<<11)
-#define EP93XX_SYSCON_DEVCFG_GONIDE (1<<10)
-#define EP93XX_SYSCON_DEVCFG_PONG (1<<9)
-#define EP93XX_SYSCON_DEVCFG_EONIDE (1<<8)
-#define EP93XX_SYSCON_DEVCFG_I2SONSSP (1<<7)
-#define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1<<6)
-#define EP93XX_SYSCON_DEVCFG_RASONP3 (1<<4)
-#define EP93XX_SYSCON_DEVCFG_RAS (1<<3)
-#define EP93XX_SYSCON_DEVCFG_ADCPD (1<<2)
-#define EP93XX_SYSCON_DEVCFG_KEYS (1<<1)
-#define EP93XX_SYSCON_DEVCFG_SHENA (1<<0)
+#define EP93XX_SYSCON_DEVCFG_SWRST (1U<<31)
+#define EP93XX_SYSCON_DEVCFG_D1ONG (1U<<30)
+#define EP93XX_SYSCON_DEVCFG_D0ONG (1U<<29)
+#define EP93XX_SYSCON_DEVCFG_IONU2 (1U<<28)
+#define EP93XX_SYSCON_DEVCFG_GONK (1U<<27)
+#define EP93XX_SYSCON_DEVCFG_TONG (1U<<26)
+#define EP93XX_SYSCON_DEVCFG_MONG (1U<<25)
+#define EP93XX_SYSCON_DEVCFG_U3EN (1U<<24)
+#define EP93XX_SYSCON_DEVCFG_CPENA (1U<<23)
+#define EP93XX_SYSCON_DEVCFG_A2ONG (1U<<22)
+#define EP93XX_SYSCON_DEVCFG_A1ONG (1U<<21)
+#define EP93XX_SYSCON_DEVCFG_U2EN (1U<<20)
+#define EP93XX_SYSCON_DEVCFG_EXVC (1U<<19)
+#define EP93XX_SYSCON_DEVCFG_U1EN (1U<<18)
+#define EP93XX_SYSCON_DEVCFG_TIN (1U<<17)
+#define EP93XX_SYSCON_DEVCFG_HC3IN (1U<<15)
+#define EP93XX_SYSCON_DEVCFG_HC3EN (1U<<14)
+#define EP93XX_SYSCON_DEVCFG_HC1IN (1U<<13)
+#define EP93XX_SYSCON_DEVCFG_HC1EN (1U<<12)
+#define EP93XX_SYSCON_DEVCFG_HONIDE (1U<<11)
+#define EP93XX_SYSCON_DEVCFG_GONIDE (1U<<10)
+#define EP93XX_SYSCON_DEVCFG_PONG (1U<<9)
+#define EP93XX_SYSCON_DEVCFG_EONIDE (1U<<8)
+#define EP93XX_SYSCON_DEVCFG_I2SONSSP (1U<<7)
+#define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1U<<6)
+#define EP93XX_SYSCON_DEVCFG_RASONP3 (1U<<4)
+#define EP93XX_SYSCON_DEVCFG_RAS (1U<<3)
+#define EP93XX_SYSCON_DEVCFG_ADCPD (1U<<2)
+#define EP93XX_SYSCON_DEVCFG_KEYS (1U<<1)
+#define EP93XX_SYSCON_DEVCFG_SHENA (1U<<0)
#define EP93XX_SYSCON_VIDCLKDIV EP93XX_SYSCON_REG(0x84)
-#define EP93XX_SYSCON_CLKDIV_ENABLE (1<<15)
-#define EP93XX_SYSCON_CLKDIV_ESEL (1<<14)
-#define EP93XX_SYSCON_CLKDIV_PSEL (1<<13)
+#define EP93XX_SYSCON_CLKDIV_ENABLE (1U<<15)
+#define EP93XX_SYSCON_CLKDIV_ESEL (1U<<14)
+#define EP93XX_SYSCON_CLKDIV_PSEL (1U<<13)
#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8
#define EP93XX_SYSCON_I2SCLKDIV EP93XX_SYSCON_REG(0x8c)
-#define EP93XX_SYSCON_I2SCLKDIV_SENA (1<<31)
-#define EP93XX_SYSCON_I2SCLKDIV_ORIDE (1<<29)
-#define EP93XX_SYSCON_I2SCLKDIV_SPOL (1<<19)
+#define EP93XX_SYSCON_I2SCLKDIV_SENA (1U<<31)
+#define EP93XX_SYSCON_I2SCLKDIV_ORIDE (1U<<29)
+#define EP93XX_SYSCON_I2SCLKDIV_SPOL (1U<<19)
#define EP93XX_I2SCLKDIV_SDIV (1 << 16)
#define EP93XX_I2SCLKDIV_LRDIV32 (0 << 17)
#define EP93XX_I2SCLKDIV_LRDIV64 (1 << 17)
#define EP93XX_I2SCLKDIV_LRDIV128 (2 << 17)
#define EP93XX_I2SCLKDIV_LRDIV_MASK (3 << 17)
#define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN (1<<15)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1U<<31)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1U<<16)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN (1U<<15)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1U<<0)
#define EP93XX_SYSCON_SYSCFG EP93XX_SYSCON_REG(0x9c)
#define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000)
#define EP93XX_SYSCON_SYSCFG_REV_SHIFT (28)
-#define EP93XX_SYSCON_SYSCFG_SBOOT (1<<8)
-#define EP93XX_SYSCON_SYSCFG_LCSN7 (1<<7)
-#define EP93XX_SYSCON_SYSCFG_LCSN6 (1<<6)
-#define EP93XX_SYSCON_SYSCFG_LASDO (1<<5)
-#define EP93XX_SYSCON_SYSCFG_LEEDA (1<<4)
-#define EP93XX_SYSCON_SYSCFG_LEECLK (1<<3)
-#define EP93XX_SYSCON_SYSCFG_LCSN2 (1<<1)
-#define EP93XX_SYSCON_SYSCFG_LCSN1 (1<<0)
+#define EP93XX_SYSCON_SYSCFG_SBOOT (1U<<8)
+#define EP93XX_SYSCON_SYSCFG_LCSN7 (1U<<7)
+#define EP93XX_SYSCON_SYSCFG_LCSN6 (1U<<6)
+#define EP93XX_SYSCON_SYSCFG_LASDO (1U<<5)
+#define EP93XX_SYSCON_SYSCFG_LEEDA (1U<<4)
+#define EP93XX_SYSCON_SYSCFG_LEECLK (1U<<3)
+#define EP93XX_SYSCON_SYSCFG_LCSN2 (1U<<1)
+#define EP93XX_SYSCON_SYSCFG_LCSN1 (1U<<0)
#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
/* EP93xx System Controller software locked register write */
--
2.11.0
[arch/arm/mach-footbridge/dc21285.c:236]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-footbridge/dc21285.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index 8b81a17f675d..a6c86175e76c 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -230,7 +230,7 @@ static irqreturn_t dc21285_parity_irq(int irq, void *dev_id)
printk("\n");
cmd = *CSR_PCICMD & 0xffff;
- *CSR_PCICMD = cmd | 1 << 31;
+ *CSR_PCICMD = cmd | 1U << 31;
/*
* back off this interrupt
--
2.11.0
[arch/arm/mach-davinci/cpuidle.c:41]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
[arch/arm/mach-davinci/cpuidle.c:43]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-davinci/ddr2.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-davinci/ddr2.h b/arch/arm/mach-davinci/ddr2.h
index 4f7d7824b0c9..76d78ffe2702 100644
--- a/arch/arm/mach-davinci/ddr2.h
+++ b/arch/arm/mach-davinci/ddr2.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
#define DDR2_SDRCR_OFFSET 0xc
-#define DDR2_SRPD_BIT (1 << 23)
-#define DDR2_MCLKSTOPEN_BIT (1 << 30)
-#define DDR2_LPMODEN_BIT (1 << 31)
+#define DDR2_SRPD_BIT (1U << 23)
+#define DDR2_MCLKSTOPEN_BIT (1U << 30)
+#define DDR2_LPMODEN_BIT (1U << 31)
--
2.11.0
[arch/arm/mach-imx/iomux-mx3.h:93]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-imx/iomux-mx3.h | 64 +++++++++++++++++++++----------------------
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/arch/arm/mach-imx/iomux-mx3.h b/arch/arm/mach-imx/iomux-mx3.h
index 99270a183d47..c30951dd110d 100644
--- a/arch/arm/mach-imx/iomux-mx3.h
+++ b/arch/arm/mach-imx/iomux-mx3.h
@@ -59,38 +59,38 @@ enum iomux_pad_config {
* various IOMUX general purpose functions
*/
enum iomux_gp_func {
- MUX_PGP_FIRI = 1 << 0,
- MUX_DDR_MODE = 1 << 1,
- MUX_PGP_CSPI_BB = 1 << 2,
- MUX_PGP_ATA_1 = 1 << 3,
- MUX_PGP_ATA_2 = 1 << 4,
- MUX_PGP_ATA_3 = 1 << 5,
- MUX_PGP_ATA_4 = 1 << 6,
- MUX_PGP_ATA_5 = 1 << 7,
- MUX_PGP_ATA_6 = 1 << 8,
- MUX_PGP_ATA_7 = 1 << 9,
- MUX_PGP_ATA_8 = 1 << 10,
- MUX_PGP_UH2 = 1 << 11,
- MUX_SDCTL_CSD0_SEL = 1 << 12,
- MUX_SDCTL_CSD1_SEL = 1 << 13,
- MUX_CSPI1_UART3 = 1 << 14,
- MUX_EXTDMAREQ2_MBX_SEL = 1 << 15,
- MUX_TAMPER_DETECT_EN = 1 << 16,
- MUX_PGP_USB_4WIRE = 1 << 17,
- MUX_PGP_USB_COMMON = 1 << 18,
- MUX_SDHC_MEMSTICK1 = 1 << 19,
- MUX_SDHC_MEMSTICK2 = 1 << 20,
- MUX_PGP_SPLL_BYP = 1 << 21,
- MUX_PGP_UPLL_BYP = 1 << 22,
- MUX_PGP_MSHC1_CLK_SEL = 1 << 23,
- MUX_PGP_MSHC2_CLK_SEL = 1 << 24,
- MUX_CSPI3_UART5_SEL = 1 << 25,
- MUX_PGP_ATA_9 = 1 << 26,
- MUX_PGP_USB_SUSPEND = 1 << 27,
- MUX_PGP_USB_OTG_LOOPBACK = 1 << 28,
- MUX_PGP_USB_HS1_LOOPBACK = 1 << 29,
- MUX_PGP_USB_HS2_LOOPBACK = 1 << 30,
- MUX_CLKO_DDR_MODE = 1 << 31,
+ MUX_PGP_FIRI = 1U << 0,
+ MUX_DDR_MODE = 1U << 1,
+ MUX_PGP_CSPI_BB = 1U << 2,
+ MUX_PGP_ATA_1 = 1U << 3,
+ MUX_PGP_ATA_2 = 1U << 4,
+ MUX_PGP_ATA_3 = 1U << 5,
+ MUX_PGP_ATA_4 = 1U << 6,
+ MUX_PGP_ATA_5 = 1U << 7,
+ MUX_PGP_ATA_6 = 1U << 8,
+ MUX_PGP_ATA_7 = 1U << 9,
+ MUX_PGP_ATA_8 = 1U << 10,
+ MUX_PGP_UH2 = 1U << 11,
+ MUX_SDCTL_CSD0_SEL = 1U << 12,
+ MUX_SDCTL_CSD1_SEL = 1U << 13,
+ MUX_CSPI1_UART3 = 1U << 14,
+ MUX_EXTDMAREQ2_MBX_SEL = 1U << 15,
+ MUX_TAMPER_DETECT_EN = 1U << 16,
+ MUX_PGP_USB_4WIRE = 1U << 17,
+ MUX_PGP_USB_COMMON = 1U << 18,
+ MUX_SDHC_MEMSTICK1 = 1U << 19,
+ MUX_SDHC_MEMSTICK2 = 1U << 20,
+ MUX_PGP_SPLL_BYP = 1U << 21,
+ MUX_PGP_UPLL_BYP = 1U << 22,
+ MUX_PGP_MSHC1_CLK_SEL = 1U << 23,
+ MUX_PGP_MSHC2_CLK_SEL = 1U << 24,
+ MUX_CSPI3_UART5_SEL = 1U << 25,
+ MUX_PGP_ATA_9 = 1U << 26,
+ MUX_PGP_USB_SUSPEND = 1U << 27,
+ MUX_PGP_USB_OTG_LOOPBACK = 1U << 28,
+ MUX_PGP_USB_HS1_LOOPBACK = 1U << 29,
+ MUX_PGP_USB_HS2_LOOPBACK = 1U << 30,
+ MUX_CLKO_DDR_MODE = 1U << 31,
};
/*
--
2.11.0
[arch/arm/mach-ks8695/pci.c:33]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-ks8695/regs-pci.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-ks8695/regs-pci.h b/arch/arm/mach-ks8695/regs-pci.h
index 75a9db6edbd9..9ddab054c6fc 100644
--- a/arch/arm/mach-ks8695/regs-pci.h
+++ b/arch/arm/mach-ks8695/regs-pci.h
@@ -45,9 +45,9 @@
-#define CFRV_GUEST (1 << 23)
+#define CFRV_GUEST (1U << 23)
#define PBCA_TYPE1 (1)
-#define PBCA_ENABLE (1 << 31)
+#define PBCA_ENABLE (1U << 31)
--
2.11.0
[arch/arm/mach-exynos/suspend.c:288]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-exynos/suspend.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index be122af0de8f..8b93d130f79c 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -285,7 +285,7 @@ static void exynos_pm_set_wakeup_mask(void)
* Set wake-up mask registers
* EXYNOS_EINT_WAKEUP_MASK is set by pinctrl driver in late suspend.
*/
- pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
+ pmu_raw_writel(exynos_irqwake_intmask & ~(1U << 31), S5P_WAKEUP_MASK);
}
static void exynos_pm_enter_sleep_mode(void)
--
2.11.0
[arch/arm/mach-omap2/powerdomain.c:190]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-omap2/powerdomain.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 1cbac76136d4..4e2eb39bc698 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -35,7 +35,7 @@
#include "soc.h"
#include "pm.h"
-#define PWRDM_TRACE_STATES_FLAG (1<<31)
+#define PWRDM_TRACE_STATES_FLAG (1U<<31)
void pwrdms_save_context(void);
void pwrdms_restore_context(void);
--
2.11.0
[arch/arm/mach-orion5x/pci.c:281]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-orion5x/pci.c:305]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-orion5x/pci.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 76951bfbacf5..1b2c077ee7b8 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -200,13 +200,13 @@ static int __init pcie_setup(struct pci_sys_data *sys)
/*
* PCI_MODE bits
*/
-#define PCI_MODE_64BIT (1 << 2)
-#define PCI_MODE_PCIX ((1 << 4) | (1 << 5))
+#define PCI_MODE_64BIT (1U << 2)
+#define PCI_MODE_PCIX ((1U << 4) | (1U << 5))
/*
* PCI_CMD bits
*/
-#define PCI_CMD_HOST_REORDER (1 << 29)
+#define PCI_CMD_HOST_REORDER (1U << 29)
/*
* PCI_P2P_CONF bits
@@ -223,7 +223,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
-#define PCI_CONF_ADDR_EN (1 << 31)
+#define PCI_CONF_ADDR_EN (1U << 31)
/*
* Internal configuration space
--
2.11.0
[arch/arm/mach-mmp/pm-mmp2.c:121]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-mmp/pm-mmp2.c:136]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-mmp/pm-mmp2.c:244]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-mmp/pm-pxa910.c:141]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
[arch/arm/mach-mmp/pm-pxa910.c:159]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-mmp/pm-mmp2.h | 40 +++++++++++------------
arch/arm/mach-mmp/pm-pxa910.h | 76 +++++++++++++++++++++----------------------
2 files changed, 58 insertions(+), 58 deletions(-)
diff --git a/arch/arm/mach-mmp/pm-mmp2.h b/arch/arm/mach-mmp/pm-mmp2.h
index 70299a9450d3..87fd1c81547d 100644
--- a/arch/arm/mach-mmp/pm-mmp2.h
+++ b/arch/arm/mach-mmp/pm-mmp2.h
@@ -12,37 +12,37 @@
#include "addr-map.h"
#define APMU_PJ_IDLE_CFG APMU_REG(0x018)
-#define APMU_PJ_IDLE_CFG_PJ_IDLE (1 << 1)
-#define APMU_PJ_IDLE_CFG_PJ_PWRDWN (1 << 5)
+#define APMU_PJ_IDLE_CFG_PJ_IDLE (1U << 1)
+#define APMU_PJ_IDLE_CFG_PJ_PWRDWN (1U << 5)
#define APMU_PJ_IDLE_CFG_PWR_SW(x) ((x) << 16)
-#define APMU_PJ_IDLE_CFG_L2_PWR_SW (1 << 19)
+#define APMU_PJ_IDLE_CFG_L2_PWR_SW (1U << 19)
#define APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK (3 << 28)
#define APMU_SRAM_PWR_DWN APMU_REG(0x08c)
#define MPMU_SCCR MPMU_REG(0x038)
#define MPMU_PCR_PJ MPMU_REG(0x1000)
-#define MPMU_PCR_PJ_AXISD (1 << 31)
-#define MPMU_PCR_PJ_SLPEN (1 << 29)
-#define MPMU_PCR_PJ_SPSD (1 << 28)
-#define MPMU_PCR_PJ_DDRCORSD (1 << 27)
-#define MPMU_PCR_PJ_APBSD (1 << 26)
-#define MPMU_PCR_PJ_INTCLR (1 << 24)
-#define MPMU_PCR_PJ_SLPWP0 (1 << 23)
-#define MPMU_PCR_PJ_SLPWP1 (1 << 22)
-#define MPMU_PCR_PJ_SLPWP2 (1 << 21)
-#define MPMU_PCR_PJ_SLPWP3 (1 << 20)
-#define MPMU_PCR_PJ_VCTCXOSD (1 << 19)
-#define MPMU_PCR_PJ_SLPWP4 (1 << 18)
-#define MPMU_PCR_PJ_SLPWP5 (1 << 17)
-#define MPMU_PCR_PJ_SLPWP6 (1 << 16)
-#define MPMU_PCR_PJ_SLPWP7 (1 << 15)
+#define MPMU_PCR_PJ_AXISD (1U << 31)
+#define MPMU_PCR_PJ_SLPEN (1U << 29)
+#define MPMU_PCR_PJ_SPSD (1U << 28)
+#define MPMU_PCR_PJ_DDRCORSD (1U << 27)
+#define MPMU_PCR_PJ_APBSD (1U << 26)
+#define MPMU_PCR_PJ_INTCLR (1U << 24)
+#define MPMU_PCR_PJ_SLPWP0 (1U << 23)
+#define MPMU_PCR_PJ_SLPWP1 (1U << 22)
+#define MPMU_PCR_PJ_SLPWP2 (1U << 21)
+#define MPMU_PCR_PJ_SLPWP3 (1U << 20)
+#define MPMU_PCR_PJ_VCTCXOSD (1U << 19)
+#define MPMU_PCR_PJ_SLPWP4 (1U << 18)
+#define MPMU_PCR_PJ_SLPWP5 (1U << 17)
+#define MPMU_PCR_PJ_SLPWP6 (1U << 16)
+#define MPMU_PCR_PJ_SLPWP7 (1U << 15)
#define MPMU_PLL2_CTRL1 MPMU_REG(0x0414)
#define MPMU_CGR_PJ MPMU_REG(0x1024)
#define MPMU_WUCRM_PJ MPMU_REG(0x104c)
-#define MPMU_WUCRM_PJ_WAKEUP(x) (1 << (x))
-#define MPMU_WUCRM_PJ_RTC_ALARM (1 << 17)
+#define MPMU_WUCRM_PJ_WAKEUP(x) (1U << (x))
+#define MPMU_WUCRM_PJ_RTC_ALARM (1U << 17)
enum {
POWER_MODE_ACTIVE = 0,
diff --git a/arch/arm/mach-mmp/pm-pxa910.h b/arch/arm/mach-mmp/pm-pxa910.h
index 8e6344adaf51..0958cde1ca6e 100644
--- a/arch/arm/mach-mmp/pm-pxa910.h
+++ b/arch/arm/mach-mmp/pm-pxa910.h
@@ -10,54 +10,54 @@
#define __PXA910_PM_H__
#define APMU_MOH_IDLE_CFG APMU_REG(0x0018)
-#define APMU_MOH_IDLE_CFG_MOH_IDLE (1 << 1)
-#define APMU_MOH_IDLE_CFG_MOH_PWRDWN (1 << 5)
-#define APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN (1 << 6)
+#define APMU_MOH_IDLE_CFG_MOH_IDLE (1U << 1)
+#define APMU_MOH_IDLE_CFG_MOH_PWRDWN (1U << 5)
+#define APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN (1U << 6)
#define APMU_MOH_IDLE_CFG_MOH_PWR_SW(x) (((x) & 0x3) << 16)
#define APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(x) (((x) & 0x3) << 18)
-#define APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ (1 << 21)
-#define APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN (1 << 20)
+#define APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ (1U << 21)
+#define APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN (1U << 20)
#define APMU_SQU_CLK_GATE_CTRL APMU_REG(0x001c)
#define APMU_MC_HW_SLP_TYPE APMU_REG(0x00b0)
#define MPMU_FCCR MPMU_REG(0x0008)
#define MPMU_APCR MPMU_REG(0x1000)
-#define MPMU_APCR_AXISD (1 << 31)
-#define MPMU_APCR_DSPSD (1 << 30)
-#define MPMU_APCR_SLPEN (1 << 29)
-#define MPMU_APCR_DTCMSD (1 << 28)
-#define MPMU_APCR_DDRCORSD (1 << 27)
-#define MPMU_APCR_APBSD (1 << 26)
-#define MPMU_APCR_BBSD (1 << 25)
-#define MPMU_APCR_SLPWP0 (1 << 23)
-#define MPMU_APCR_SLPWP1 (1 << 22)
-#define MPMU_APCR_SLPWP2 (1 << 21)
-#define MPMU_APCR_SLPWP3 (1 << 20)
-#define MPMU_APCR_VCTCXOSD (1 << 19)
-#define MPMU_APCR_SLPWP4 (1 << 18)
-#define MPMU_APCR_SLPWP5 (1 << 17)
-#define MPMU_APCR_SLPWP6 (1 << 16)
-#define MPMU_APCR_SLPWP7 (1 << 15)
-#define MPMU_APCR_MSASLPEN (1 << 14)
-#define MPMU_APCR_STBYEN (1 << 13)
+#define MPMU_APCR_AXISD (1U << 31)
+#define MPMU_APCR_DSPSD (1U << 30)
+#define MPMU_APCR_SLPEN (1U << 29)
+#define MPMU_APCR_DTCMSD (1U << 28)
+#define MPMU_APCR_DDRCORSD (1U << 27)
+#define MPMU_APCR_APBSD (1U << 26)
+#define MPMU_APCR_BBSD (1U << 25)
+#define MPMU_APCR_SLPWP0 (1U << 23)
+#define MPMU_APCR_SLPWP1 (1U << 22)
+#define MPMU_APCR_SLPWP2 (1U << 21)
+#define MPMU_APCR_SLPWP3 (1U << 20)
+#define MPMU_APCR_VCTCXOSD (1U << 19)
+#define MPMU_APCR_SLPWP4 (1U << 18)
+#define MPMU_APCR_SLPWP5 (1U << 17)
+#define MPMU_APCR_SLPWP6 (1U << 16)
+#define MPMU_APCR_SLPWP7 (1U << 15)
+#define MPMU_APCR_MSASLPEN (1U << 14)
+#define MPMU_APCR_STBYEN (1U << 13)
#define MPMU_AWUCRM MPMU_REG(0x104c)
-#define MPMU_AWUCRM_AP_ASYNC_INT (1 << 25)
-#define MPMU_AWUCRM_AP_FULL_IDLE (1 << 24)
-#define MPMU_AWUCRM_SDH1 (1 << 23)
-#define MPMU_AWUCRM_SDH2 (1 << 22)
-#define MPMU_AWUCRM_KEYPRESS (1 << 21)
-#define MPMU_AWUCRM_TRACKBALL (1 << 20)
-#define MPMU_AWUCRM_NEWROTARY (1 << 19)
-#define MPMU_AWUCRM_RTC_ALARM (1 << 17)
-#define MPMU_AWUCRM_AP2_TIMER_3 (1 << 13)
-#define MPMU_AWUCRM_AP2_TIMER_2 (1 << 12)
-#define MPMU_AWUCRM_AP2_TIMER_1 (1 << 11)
-#define MPMU_AWUCRM_AP1_TIMER_3 (1 << 10)
-#define MPMU_AWUCRM_AP1_TIMER_2 (1 << 9)
-#define MPMU_AWUCRM_AP1_TIMER_1 (1 << 8)
-#define MPMU_AWUCRM_WAKEUP(x) (1 << ((x) & 0x7))
+#define MPMU_AWUCRM_AP_ASYNC_INT (1U << 25)
+#define MPMU_AWUCRM_AP_FULL_IDLE (1U << 24)
+#define MPMU_AWUCRM_SDH1 (1U << 23)
+#define MPMU_AWUCRM_SDH2 (1U << 22)
+#define MPMU_AWUCRM_KEYPRESS (1U << 21)
+#define MPMU_AWUCRM_TRACKBALL (1U << 20)
+#define MPMU_AWUCRM_NEWROTARY (1U << 19)
+#define MPMU_AWUCRM_RTC_ALARM (1U << 17)
+#define MPMU_AWUCRM_AP2_TIMER_3 (1U << 13)
+#define MPMU_AWUCRM_AP2_TIMER_2 (1U << 12)
+#define MPMU_AWUCRM_AP2_TIMER_1 (1U << 11)
+#define MPMU_AWUCRM_AP1_TIMER_3 (1U << 10)
+#define MPMU_AWUCRM_AP1_TIMER_2 (1U << 9)
+#define MPMU_AWUCRM_AP1_TIMER_1 (1U << 8)
+#define MPMU_AWUCRM_WAKEUP(x) (1U << ((x) & 0x7))
enum {
POWER_MODE_ACTIVE = 0,
--
2.11.0
[arch/arm/mach-vexpress/spc.c:366]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-vexpress/spc.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-vexpress/spc.c
index 0f5381d13494..f8911dae776c 100644
--- a/arch/arm/mach-vexpress/spc.c
+++ b/arch/arm/mach-vexpress/spc.c
@@ -57,8 +57,8 @@
/* SPC CPU/cluster reset statue */
#define STANDBYWFI_STAT 0x3c
-#define STANDBYWFI_STAT_A15_CPU_MASK(cpu) (1 << (cpu))
-#define STANDBYWFI_STAT_A7_CPU_MASK(cpu) (1 << (3 + (cpu)))
+#define STANDBYWFI_STAT_A15_CPU_MASK(cpu) (1U << (cpu))
+#define STANDBYWFI_STAT_A7_CPU_MASK(cpu) (1U << (3 + (cpu)))
/* SPC system config interface registers */
#define SYSCFG_WDATA 0x70
@@ -69,7 +69,7 @@
#define A7_PERFVAL_BASE 0xC30
/* Config interface control bits */
-#define SYSCFG_START (1 << 31)
+#define SYSCFG_START (1U << 31)
#define SYSCFG_SCC (6 << 20)
#define SYSCFG_STAT (14 << 20)
@@ -90,8 +90,8 @@
#define CA15_DVFS 0
#define CA7_DVFS 1
#define SPC_SYS_CFG 2
-#define STAT_COMPLETE(type) ((1 << 0) << (type << 2))
-#define STAT_ERR(type) ((1 << 1) << (type << 2))
+#define STAT_COMPLETE(type) ((1U << 0) << (type << 2))
+#define STAT_ERR(type) ((1U << 1) << (type << 2))
#define RESPONSE_MASK(type) (STAT_COMPLETE(type) | STAT_ERR(type))
struct ve_spc_opp {
@@ -162,7 +162,7 @@ void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set)
if (cluster >= MAX_CLUSTERS)
return;
- mask = 1 << cpu;
+ mask = 1U << cpu;
if (!cluster_is_a15(cluster))
mask <<= 4;
--
2.11.0
[arch/arm/mm/alignment.c:875]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
[arch/arm/mm/fault.c:556]: (error) Shifting signed 32-bit value by 31
bits is undefined behaviour
[arch/arm/mm/fault.c:585]: (error) Shifting signed 32-bit value by 31
bits is undefined behaviour
[arch/arm/mm/fault.c:219]: (error) Shifting signed 32-bit value by 31
bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mm/fault.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mm/fault.h b/arch/arm/mm/fault.h
index c063708fa503..159c4e7bff09 100644
--- a/arch/arm/mm/fault.h
+++ b/arch/arm/mm/fault.h
@@ -5,9 +5,9 @@
/*
* Fault status register encodings. We steal bit 31 for our own purposes.
*/
-#define FSR_LNX_PF (1 << 31)
-#define FSR_WRITE (1 << 11)
-#define FSR_FS4 (1 << 10)
+#define FSR_LNX_PF (1U << 31)
+#define FSR_WRITE (1U << 11)
+#define FSR_FS4 (1U << 10)
#define FSR_FS3_0 (15)
#define FSR_FS5_0 (0x3f)
--
2.11.0
[arch/arm/net/bpf_jit_32.c:618]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/net/bpf_jit_32.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
index adff54c312bf..9c3f8fb871e5 100644
--- a/arch/arm/net/bpf_jit_32.c
+++ b/arch/arm/net/bpf_jit_32.c
@@ -612,7 +612,7 @@ static inline void emit_a32_mov_se_i64(const bool is64, const s8 dst[],
const u32 val, struct jit_ctx *ctx) {
u64 val64 = val;
- if (is64 && (val & (1<<31)))
+ if (is64 && (val & (1U<<31)))
val64 |= 0xffffffff00000000ULL;
emit_a32_mov_i64(dst, val64, ctx);
}
--
2.11.0
[arch/arm/mach-pxa/irq.c:117]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
[arch/arm/mach-pxa/irq.c:131]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-pxa/irq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 74efc3ab595f..2e2afe16069c 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -35,9 +35,9 @@
#define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \
((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \
(0x144 + (((i) - 64) << 2)))
-#define ICHP_VAL_IRQ (1 << 31)
+#define ICHP_VAL_IRQ (1U << 31)
#define ICHP_IRQ(i) (((i) >> 16) & 0x7fff)
-#define IPR_VALID (1 << 31)
+#define IPR_VALID (1U << 31)
#define MAX_INTERNAL_IRQS 128
--
2.11.0
[arch/arm/vfp/vfpdouble.c:397]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
[arch/arm/vfp/vfpdouble.c:407]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
[arch/arm/vfp/vfpmodule.c:263]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
[arch/arm/vfp/vfpmodule.c:264]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
[arch/arm/vfp/vfpsingle.c:441]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
[arch/arm/vfp/vfpsingle.c:451]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/vfp/vfpinstr.h | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/arch/arm/vfp/vfpinstr.h b/arch/arm/vfp/vfpinstr.h
index 38dc154e39ff..377ab0ced8d8 100644
--- a/arch/arm/vfp/vfpinstr.h
+++ b/arch/arm/vfp/vfpinstr.h
@@ -8,8 +8,8 @@
* VFP instruction masks.
*/
#define INST_CPRTDO(inst) (((inst) & 0x0f000000) == 0x0e000000)
-#define INST_CPRT(inst) ((inst) & (1 << 4))
-#define INST_CPRT_L(inst) ((inst) & (1 << 20))
+#define INST_CPRT(inst) ((inst) & (1U << 4))
+#define INST_CPRT_L(inst) ((inst) & (1U << 20))
#define INST_CPRT_Rd(inst) (((inst) & (15 << 12)) >> 12)
#define INST_CPRT_OP(inst) (((inst) >> 21) & 7)
#define INST_CPNUM(inst) ((inst) & 0xf00)
@@ -27,7 +27,7 @@
#define FOP_FDIV (0x00800000)
#define FOP_EXT (0x00b00040)
-#define FOP_TO_IDX(inst) ((inst & 0x00b00000) >> 20 | (inst & (1 << 6)) >> 4)
+#define FOP_TO_IDX(inst) ((inst & 0x00b00000) >> 20 | (inst & (1U << 6)) >> 4)
#define FEXT_MASK (0x000f0080)
#define FEXT_FCPY (0x00000000)
@@ -46,21 +46,21 @@
#define FEXT_FTOSI (0x000d0000)
#define FEXT_FTOSIZ (0x000d0080)
-#define FEXT_TO_IDX(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
+#define FEXT_TO_IDX(inst) ((inst & 0x000f0000) >> 15 | (inst & (1U << 7)) >> 7)
-#define vfp_get_sd(inst) ((inst & 0x0000f000) >> 11 | (inst & (1 << 22)) >> 22)
-#define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12 | (inst & (1 << 22)) >> 18)
-#define vfp_get_sm(inst) ((inst & 0x0000000f) << 1 | (inst & (1 << 5)) >> 5)
-#define vfp_get_dm(inst) ((inst & 0x0000000f) | (inst & (1 << 5)) >> 1)
-#define vfp_get_sn(inst) ((inst & 0x000f0000) >> 15 | (inst & (1 << 7)) >> 7)
-#define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16 | (inst & (1 << 7)) >> 3)
+#define vfp_get_sd(inst) ((inst & 0x0000f000) >> 11 | (inst & (1U << 22)) >> 22)
+#define vfp_get_dd(inst) ((inst & 0x0000f000) >> 12 | (inst & (1U << 22)) >> 18)
+#define vfp_get_sm(inst) ((inst & 0x0000000f) << 1 | (inst & (1U << 5)) >> 5)
+#define vfp_get_dm(inst) ((inst & 0x0000000f) | (inst & (1U << 5)) >> 1)
+#define vfp_get_sn(inst) ((inst & 0x000f0000) >> 15 | (inst & (1U << 7)) >> 7)
+#define vfp_get_dn(inst) ((inst & 0x000f0000) >> 16 | (inst & (1U << 7)) >> 3)
#define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00)
-#define FPSCR_N (1 << 31)
-#define FPSCR_Z (1 << 30)
-#define FPSCR_C (1 << 29)
-#define FPSCR_V (1 << 28)
+#define FPSCR_N (1U << 31)
+#define FPSCR_Z (1U << 30)
+#define FPSCR_C (1U << 29)
+#define FPSCR_V (1U << 28)
/*
* Since we aren't building with -mfpu=vfp, we need to code
--
2.11.0
Hi!
On Sun, 23 Jun 2019 22:13:01 +0700
Phong Tran <[email protected]> wrote:
> [arch/arm/mach-ep93xx/clock.c:102]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
> [arch/arm/mach-ep93xx/clock.c:132]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
> [arch/arm/mach-ep93xx/clock.c:140]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
> [arch/arm/mach-ep93xx/core.c:1001]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
> [arch/arm/mach-ep93xx/core.c:1002]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
>
> Signed-off-by: Phong Tran <[email protected]>
> ---
> arch/arm/mach-ep93xx/soc.h | 132 ++++++++++++++++++++++-----------------------
> 1 file changed, 66 insertions(+), 66 deletions(-)
>
> diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h
> index f2dace1c9154..831ea5266281 100644
> --- a/arch/arm/mach-ep93xx/soc.h
> +++ b/arch/arm/mach-ep93xx/soc.h
> @@ -109,89 +109,89 @@
> #define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x))
> #define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00)
> #define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04)
> -#define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31)
> -#define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29)
> -#define EP93XX_SYSCON_PWRCNT_USH_EN (1<<28)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 (1<<27)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 (1<<26)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 (1<<25)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 (1<<24)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 (1<<23)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 (1<<22)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 (1<<21)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 (1<<20)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 (1<<19)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 (1<<18)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 (1<<17)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 (1<<16)
> +#define EP93XX_SYSCON_PWRCNT_FIR_EN (1U<<31)
Could you please use BIT() for this?
> +#define EP93XX_SYSCON_PWRCNT_UARTBAUD (1U<<29)
> +#define EP93XX_SYSCON_PWRCNT_USH_EN (1U<<28)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 (1U<<27)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 (1U<<26)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 (1U<<25)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 (1U<<24)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 (1U<<23)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 (1U<<22)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 (1U<<21)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 (1U<<20)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 (1U<<19)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 (1U<<18)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 (1U<<17)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 (1U<<16)
> #define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08)
> #define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c)
> #define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20)
> -#define EP93XX_SYSCON_CLKSET1_NBYP1 (1<<23)
> +#define EP93XX_SYSCON_CLKSET1_NBYP1 (1U<<23)
> #define EP93XX_SYSCON_CLKSET2 EP93XX_SYSCON_REG(0x24)
> -#define EP93XX_SYSCON_CLKSET2_NBYP2 (1<<19)
> -#define EP93XX_SYSCON_CLKSET2_PLL2_EN (1<<18)
> +#define EP93XX_SYSCON_CLKSET2_NBYP2 (1U<<19)
> +#define EP93XX_SYSCON_CLKSET2_PLL2_EN (1U<<18)
> #define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80)
> -#define EP93XX_SYSCON_DEVCFG_SWRST (1<<31)
> -#define EP93XX_SYSCON_DEVCFG_D1ONG (1<<30)
> -#define EP93XX_SYSCON_DEVCFG_D0ONG (1<<29)
> -#define EP93XX_SYSCON_DEVCFG_IONU2 (1<<28)
> -#define EP93XX_SYSCON_DEVCFG_GONK (1<<27)
> -#define EP93XX_SYSCON_DEVCFG_TONG (1<<26)
> -#define EP93XX_SYSCON_DEVCFG_MONG (1<<25)
> -#define EP93XX_SYSCON_DEVCFG_U3EN (1<<24)
> -#define EP93XX_SYSCON_DEVCFG_CPENA (1<<23)
> -#define EP93XX_SYSCON_DEVCFG_A2ONG (1<<22)
> -#define EP93XX_SYSCON_DEVCFG_A1ONG (1<<21)
> -#define EP93XX_SYSCON_DEVCFG_U2EN (1<<20)
> -#define EP93XX_SYSCON_DEVCFG_EXVC (1<<19)
> -#define EP93XX_SYSCON_DEVCFG_U1EN (1<<18)
> -#define EP93XX_SYSCON_DEVCFG_TIN (1<<17)
> -#define EP93XX_SYSCON_DEVCFG_HC3IN (1<<15)
> -#define EP93XX_SYSCON_DEVCFG_HC3EN (1<<14)
> -#define EP93XX_SYSCON_DEVCFG_HC1IN (1<<13)
> -#define EP93XX_SYSCON_DEVCFG_HC1EN (1<<12)
> -#define EP93XX_SYSCON_DEVCFG_HONIDE (1<<11)
> -#define EP93XX_SYSCON_DEVCFG_GONIDE (1<<10)
> -#define EP93XX_SYSCON_DEVCFG_PONG (1<<9)
> -#define EP93XX_SYSCON_DEVCFG_EONIDE (1<<8)
> -#define EP93XX_SYSCON_DEVCFG_I2SONSSP (1<<7)
> -#define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1<<6)
> -#define EP93XX_SYSCON_DEVCFG_RASONP3 (1<<4)
> -#define EP93XX_SYSCON_DEVCFG_RAS (1<<3)
> -#define EP93XX_SYSCON_DEVCFG_ADCPD (1<<2)
> -#define EP93XX_SYSCON_DEVCFG_KEYS (1<<1)
> -#define EP93XX_SYSCON_DEVCFG_SHENA (1<<0)
> +#define EP93XX_SYSCON_DEVCFG_SWRST (1U<<31)
> +#define EP93XX_SYSCON_DEVCFG_D1ONG (1U<<30)
> +#define EP93XX_SYSCON_DEVCFG_D0ONG (1U<<29)
> +#define EP93XX_SYSCON_DEVCFG_IONU2 (1U<<28)
> +#define EP93XX_SYSCON_DEVCFG_GONK (1U<<27)
> +#define EP93XX_SYSCON_DEVCFG_TONG (1U<<26)
> +#define EP93XX_SYSCON_DEVCFG_MONG (1U<<25)
> +#define EP93XX_SYSCON_DEVCFG_U3EN (1U<<24)
> +#define EP93XX_SYSCON_DEVCFG_CPENA (1U<<23)
> +#define EP93XX_SYSCON_DEVCFG_A2ONG (1U<<22)
> +#define EP93XX_SYSCON_DEVCFG_A1ONG (1U<<21)
> +#define EP93XX_SYSCON_DEVCFG_U2EN (1U<<20)
> +#define EP93XX_SYSCON_DEVCFG_EXVC (1U<<19)
> +#define EP93XX_SYSCON_DEVCFG_U1EN (1U<<18)
> +#define EP93XX_SYSCON_DEVCFG_TIN (1U<<17)
> +#define EP93XX_SYSCON_DEVCFG_HC3IN (1U<<15)
> +#define EP93XX_SYSCON_DEVCFG_HC3EN (1U<<14)
> +#define EP93XX_SYSCON_DEVCFG_HC1IN (1U<<13)
> +#define EP93XX_SYSCON_DEVCFG_HC1EN (1U<<12)
> +#define EP93XX_SYSCON_DEVCFG_HONIDE (1U<<11)
> +#define EP93XX_SYSCON_DEVCFG_GONIDE (1U<<10)
> +#define EP93XX_SYSCON_DEVCFG_PONG (1U<<9)
> +#define EP93XX_SYSCON_DEVCFG_EONIDE (1U<<8)
> +#define EP93XX_SYSCON_DEVCFG_I2SONSSP (1U<<7)
> +#define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1U<<6)
> +#define EP93XX_SYSCON_DEVCFG_RASONP3 (1U<<4)
> +#define EP93XX_SYSCON_DEVCFG_RAS (1U<<3)
> +#define EP93XX_SYSCON_DEVCFG_ADCPD (1U<<2)
> +#define EP93XX_SYSCON_DEVCFG_KEYS (1U<<1)
> +#define EP93XX_SYSCON_DEVCFG_SHENA (1U<<0)
> #define EP93XX_SYSCON_VIDCLKDIV EP93XX_SYSCON_REG(0x84)
> -#define EP93XX_SYSCON_CLKDIV_ENABLE (1<<15)
> -#define EP93XX_SYSCON_CLKDIV_ESEL (1<<14)
> -#define EP93XX_SYSCON_CLKDIV_PSEL (1<<13)
> +#define EP93XX_SYSCON_CLKDIV_ENABLE (1U<<15)
> +#define EP93XX_SYSCON_CLKDIV_ESEL (1U<<14)
> +#define EP93XX_SYSCON_CLKDIV_PSEL (1U<<13)
> #define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8
> #define EP93XX_SYSCON_I2SCLKDIV EP93XX_SYSCON_REG(0x8c)
> -#define EP93XX_SYSCON_I2SCLKDIV_SENA (1<<31)
> -#define EP93XX_SYSCON_I2SCLKDIV_ORIDE (1<<29)
> -#define EP93XX_SYSCON_I2SCLKDIV_SPOL (1<<19)
> +#define EP93XX_SYSCON_I2SCLKDIV_SENA (1U<<31)
> +#define EP93XX_SYSCON_I2SCLKDIV_ORIDE (1U<<29)
> +#define EP93XX_SYSCON_I2SCLKDIV_SPOL (1U<<19)
> #define EP93XX_I2SCLKDIV_SDIV (1 << 16)
> #define EP93XX_I2SCLKDIV_LRDIV32 (0 << 17)
> #define EP93XX_I2SCLKDIV_LRDIV64 (1 << 17)
> #define EP93XX_I2SCLKDIV_LRDIV128 (2 << 17)
> #define EP93XX_I2SCLKDIV_LRDIV_MASK (3 << 17)
> #define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90)
> -#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31)
> -#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16)
> -#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN (1<<15)
> -#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
> +#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1U<<31)
> +#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1U<<16)
> +#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN (1U<<15)
> +#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1U<<0)
> #define EP93XX_SYSCON_SYSCFG EP93XX_SYSCON_REG(0x9c)
> #define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000)
> #define EP93XX_SYSCON_SYSCFG_REV_SHIFT (28)
> -#define EP93XX_SYSCON_SYSCFG_SBOOT (1<<8)
> -#define EP93XX_SYSCON_SYSCFG_LCSN7 (1<<7)
> -#define EP93XX_SYSCON_SYSCFG_LCSN6 (1<<6)
> -#define EP93XX_SYSCON_SYSCFG_LASDO (1<<5)
> -#define EP93XX_SYSCON_SYSCFG_LEEDA (1<<4)
> -#define EP93XX_SYSCON_SYSCFG_LEECLK (1<<3)
> -#define EP93XX_SYSCON_SYSCFG_LCSN2 (1<<1)
> -#define EP93XX_SYSCON_SYSCFG_LCSN1 (1<<0)
> +#define EP93XX_SYSCON_SYSCFG_SBOOT (1U<<8)
> +#define EP93XX_SYSCON_SYSCFG_LCSN7 (1U<<7)
> +#define EP93XX_SYSCON_SYSCFG_LCSN6 (1U<<6)
> +#define EP93XX_SYSCON_SYSCFG_LASDO (1U<<5)
> +#define EP93XX_SYSCON_SYSCFG_LEEDA (1U<<4)
> +#define EP93XX_SYSCON_SYSCFG_LEECLK (1U<<3)
> +#define EP93XX_SYSCON_SYSCFG_LCSN2 (1U<<1)
> +#define EP93XX_SYSCON_SYSCFG_LCSN1 (1U<<0)
> #define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
>
> /* EP93xx System Controller software locked register write */
--
Alexander Sverdlin.
On Sun, Jun 23, 2019 at 10:13:08PM +0700, Phong Tran wrote:
> [arch/arm/mach-orion5x/pci.c:281]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
> [arch/arm/mach-orion5x/pci.c:305]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
>
> Signed-off-by: Phong Tran <[email protected]>
Maybe using the BIT() macro would be better, but this is O.K.
Reviewed-by: Andrew Lunn <[email protected]>
Andrew
On Sun, 23 Jun 2019 at 17:14, Phong Tran <[email protected]> wrote:
>
> [arch/arm/mach-exynos/suspend.c:288]: (error) Shifting signed 32-bit
> value by 31 bits is undefined behaviour
>
> Signed-off-by: Phong Tran <[email protected]>
> ---
> arch/arm/mach-exynos/suspend.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Let's switch to BIT macro. It will solve the problem and is preferred
way of coding.
Best regards,
Krzysztof
On Sun, Jun 23, 2019 at 10:13:04PM +0700, Phong Tran wrote:
> [arch/arm/mach-imx/iomux-mx3.h:93]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
>
> Signed-off-by: Phong Tran <[email protected]>
Applied, thanks.
On Sun, Jun 23, 2019 at 10:12:59PM +0700, Phong Tran wrote:
> fix "Shifting signed 32-bit value by 31 bits is undefined behaviour
> errors"
>
> [arch/arm/kernel/perf_event_v7.c:1080]: (error) Shifting signed 32-bit
> value by 31 bits is undefined behaviour
> [arch/arm/kernel/perf_event_v7.c:1436]: (error) Shifting signed 32-bit
> value by 31 bits is undefined behaviour
> [arch/arm/kernel/perf_event_v7.c:1783]: (error) Shifting signed 32-bit
> value by 31 bits is undefined behaviour
I don't think that is true; the kernel uses -fno-strict-overflow (which
implies -fwrapv) and that takes away all the signed UB.
Hi Phong,
> [arch/arm/mach-orion5x/pci.c:281]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
> [arch/arm/mach-orion5x/pci.c:305]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
>
While Andrew was Ok with this version, I will wait for your v2 using
BIT() marcro.
Thanks,
Gregory
> Signed-off-by: Phong Tran <[email protected]>
> ---
> arch/arm/mach-orion5x/pci.c | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
> index 76951bfbacf5..1b2c077ee7b8 100644
> --- a/arch/arm/mach-orion5x/pci.c
> +++ b/arch/arm/mach-orion5x/pci.c
> @@ -200,13 +200,13 @@ static int __init pcie_setup(struct pci_sys_data *sys)
> /*
> * PCI_MODE bits
> */
> -#define PCI_MODE_64BIT (1 << 2)
> -#define PCI_MODE_PCIX ((1 << 4) | (1 << 5))
> +#define PCI_MODE_64BIT (1U << 2)
> +#define PCI_MODE_PCIX ((1U << 4) | (1U << 5))
>
> /*
> * PCI_CMD bits
> */
> -#define PCI_CMD_HOST_REORDER (1 << 29)
> +#define PCI_CMD_HOST_REORDER (1U << 29)
>
> /*
> * PCI_P2P_CONF bits
> @@ -223,7 +223,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
> #define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
> #define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
> #define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
> -#define PCI_CONF_ADDR_EN (1 << 31)
> +#define PCI_CONF_ADDR_EN (1U << 31)
>
> /*
> * Internal configuration space
> --
> 2.11.0
>
--
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
On Sun, 2019-06-23 at 22:13 +0700, Phong Tran wrote:
> [arch/arm/mach-mmp/pm-mmp2.c:121]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
> [arch/arm/mach-mmp/pm-mmp2.c:136]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
> [arch/arm/mach-mmp/pm-mmp2.c:244]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
> [arch/arm/mach-mmp/pm-pxa910.c:141]: (error) Shifting signed 32-bit
> value by 31 bits is undefined behaviour
> [arch/arm/mach-mmp/pm-pxa910.c:159]: (error) Shifting signed 32-bit
> value by 31 bits is undefined behaviour
>
> Signed-off-by: Phong Tran <[email protected]>
Like others already pointed out, you may want to send out a v2 that
would use the BIT() macro. Either way works for me:
Acked-by: Lubomir Rintel <[email protected]> [mmp]
Thank you
Lubo
> ---
> arch/arm/mach-mmp/pm-mmp2.h | 40 +++++++++++------------
> arch/arm/mach-mmp/pm-pxa910.h | 76 +++++++++++++++++++++----------------------
> 2 files changed, 58 insertions(+), 58 deletions(-)
>
> diff --git a/arch/arm/mach-mmp/pm-mmp2.h b/arch/arm/mach-mmp/pm-mmp2.h
> index 70299a9450d3..87fd1c81547d 100644
> --- a/arch/arm/mach-mmp/pm-mmp2.h
> +++ b/arch/arm/mach-mmp/pm-mmp2.h
> @@ -12,37 +12,37 @@
> #include "addr-map.h"
>
> #define APMU_PJ_IDLE_CFG APMU_REG(0x018)
> -#define APMU_PJ_IDLE_CFG_PJ_IDLE (1 << 1)
> -#define APMU_PJ_IDLE_CFG_PJ_PWRDWN (1 << 5)
> +#define APMU_PJ_IDLE_CFG_PJ_IDLE (1U << 1)
> +#define APMU_PJ_IDLE_CFG_PJ_PWRDWN (1U << 5)
> #define APMU_PJ_IDLE_CFG_PWR_SW(x) ((x) << 16)
> -#define APMU_PJ_IDLE_CFG_L2_PWR_SW (1 << 19)
> +#define APMU_PJ_IDLE_CFG_L2_PWR_SW (1U << 19)
> #define APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK (3 << 28)
>
> #define APMU_SRAM_PWR_DWN APMU_REG(0x08c)
>
> #define MPMU_SCCR MPMU_REG(0x038)
> #define MPMU_PCR_PJ MPMU_REG(0x1000)
> -#define MPMU_PCR_PJ_AXISD (1 << 31)
> -#define MPMU_PCR_PJ_SLPEN (1 << 29)
> -#define MPMU_PCR_PJ_SPSD (1 << 28)
> -#define MPMU_PCR_PJ_DDRCORSD (1 << 27)
> -#define MPMU_PCR_PJ_APBSD (1 << 26)
> -#define MPMU_PCR_PJ_INTCLR (1 << 24)
> -#define MPMU_PCR_PJ_SLPWP0 (1 << 23)
> -#define MPMU_PCR_PJ_SLPWP1 (1 << 22)
> -#define MPMU_PCR_PJ_SLPWP2 (1 << 21)
> -#define MPMU_PCR_PJ_SLPWP3 (1 << 20)
> -#define MPMU_PCR_PJ_VCTCXOSD (1 << 19)
> -#define MPMU_PCR_PJ_SLPWP4 (1 << 18)
> -#define MPMU_PCR_PJ_SLPWP5 (1 << 17)
> -#define MPMU_PCR_PJ_SLPWP6 (1 << 16)
> -#define MPMU_PCR_PJ_SLPWP7 (1 << 15)
> +#define MPMU_PCR_PJ_AXISD (1U << 31)
> +#define MPMU_PCR_PJ_SLPEN (1U << 29)
> +#define MPMU_PCR_PJ_SPSD (1U << 28)
> +#define MPMU_PCR_PJ_DDRCORSD (1U << 27)
> +#define MPMU_PCR_PJ_APBSD (1U << 26)
> +#define MPMU_PCR_PJ_INTCLR (1U << 24)
> +#define MPMU_PCR_PJ_SLPWP0 (1U << 23)
> +#define MPMU_PCR_PJ_SLPWP1 (1U << 22)
> +#define MPMU_PCR_PJ_SLPWP2 (1U << 21)
> +#define MPMU_PCR_PJ_SLPWP3 (1U << 20)
> +#define MPMU_PCR_PJ_VCTCXOSD (1U << 19)
> +#define MPMU_PCR_PJ_SLPWP4 (1U << 18)
> +#define MPMU_PCR_PJ_SLPWP5 (1U << 17)
> +#define MPMU_PCR_PJ_SLPWP6 (1U << 16)
> +#define MPMU_PCR_PJ_SLPWP7 (1U << 15)
>
> #define MPMU_PLL2_CTRL1 MPMU_REG(0x0414)
> #define MPMU_CGR_PJ MPMU_REG(0x1024)
> #define MPMU_WUCRM_PJ MPMU_REG(0x104c)
> -#define MPMU_WUCRM_PJ_WAKEUP(x) (1 << (x))
> -#define MPMU_WUCRM_PJ_RTC_ALARM (1 << 17)
> +#define MPMU_WUCRM_PJ_WAKEUP(x) (1U << (x))
> +#define MPMU_WUCRM_PJ_RTC_ALARM (1U << 17)
>
> enum {
> POWER_MODE_ACTIVE = 0,
> diff --git a/arch/arm/mach-mmp/pm-pxa910.h b/arch/arm/mach-mmp/pm-pxa910.h
> index 8e6344adaf51..0958cde1ca6e 100644
> --- a/arch/arm/mach-mmp/pm-pxa910.h
> +++ b/arch/arm/mach-mmp/pm-pxa910.h
> @@ -10,54 +10,54 @@
> #define __PXA910_PM_H__
>
> #define APMU_MOH_IDLE_CFG APMU_REG(0x0018)
> -#define APMU_MOH_IDLE_CFG_MOH_IDLE (1 << 1)
> -#define APMU_MOH_IDLE_CFG_MOH_PWRDWN (1 << 5)
> -#define APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN (1 << 6)
> +#define APMU_MOH_IDLE_CFG_MOH_IDLE (1U << 1)
> +#define APMU_MOH_IDLE_CFG_MOH_PWRDWN (1U << 5)
> +#define APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN (1U << 6)
> #define APMU_MOH_IDLE_CFG_MOH_PWR_SW(x) (((x) & 0x3) << 16)
> #define APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(x) (((x) & 0x3) << 18)
> -#define APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ (1 << 21)
> -#define APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN (1 << 20)
> +#define APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ (1U << 21)
> +#define APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN (1U << 20)
>
> #define APMU_SQU_CLK_GATE_CTRL APMU_REG(0x001c)
> #define APMU_MC_HW_SLP_TYPE APMU_REG(0x00b0)
>
> #define MPMU_FCCR MPMU_REG(0x0008)
> #define MPMU_APCR MPMU_REG(0x1000)
> -#define MPMU_APCR_AXISD (1 << 31)
> -#define MPMU_APCR_DSPSD (1 << 30)
> -#define MPMU_APCR_SLPEN (1 << 29)
> -#define MPMU_APCR_DTCMSD (1 << 28)
> -#define MPMU_APCR_DDRCORSD (1 << 27)
> -#define MPMU_APCR_APBSD (1 << 26)
> -#define MPMU_APCR_BBSD (1 << 25)
> -#define MPMU_APCR_SLPWP0 (1 << 23)
> -#define MPMU_APCR_SLPWP1 (1 << 22)
> -#define MPMU_APCR_SLPWP2 (1 << 21)
> -#define MPMU_APCR_SLPWP3 (1 << 20)
> -#define MPMU_APCR_VCTCXOSD (1 << 19)
> -#define MPMU_APCR_SLPWP4 (1 << 18)
> -#define MPMU_APCR_SLPWP5 (1 << 17)
> -#define MPMU_APCR_SLPWP6 (1 << 16)
> -#define MPMU_APCR_SLPWP7 (1 << 15)
> -#define MPMU_APCR_MSASLPEN (1 << 14)
> -#define MPMU_APCR_STBYEN (1 << 13)
> +#define MPMU_APCR_AXISD (1U << 31)
> +#define MPMU_APCR_DSPSD (1U << 30)
> +#define MPMU_APCR_SLPEN (1U << 29)
> +#define MPMU_APCR_DTCMSD (1U << 28)
> +#define MPMU_APCR_DDRCORSD (1U << 27)
> +#define MPMU_APCR_APBSD (1U << 26)
> +#define MPMU_APCR_BBSD (1U << 25)
> +#define MPMU_APCR_SLPWP0 (1U << 23)
> +#define MPMU_APCR_SLPWP1 (1U << 22)
> +#define MPMU_APCR_SLPWP2 (1U << 21)
> +#define MPMU_APCR_SLPWP3 (1U << 20)
> +#define MPMU_APCR_VCTCXOSD (1U << 19)
> +#define MPMU_APCR_SLPWP4 (1U << 18)
> +#define MPMU_APCR_SLPWP5 (1U << 17)
> +#define MPMU_APCR_SLPWP6 (1U << 16)
> +#define MPMU_APCR_SLPWP7 (1U << 15)
> +#define MPMU_APCR_MSASLPEN (1U << 14)
> +#define MPMU_APCR_STBYEN (1U << 13)
>
> #define MPMU_AWUCRM MPMU_REG(0x104c)
> -#define MPMU_AWUCRM_AP_ASYNC_INT (1 << 25)
> -#define MPMU_AWUCRM_AP_FULL_IDLE (1 << 24)
> -#define MPMU_AWUCRM_SDH1 (1 << 23)
> -#define MPMU_AWUCRM_SDH2 (1 << 22)
> -#define MPMU_AWUCRM_KEYPRESS (1 << 21)
> -#define MPMU_AWUCRM_TRACKBALL (1 << 20)
> -#define MPMU_AWUCRM_NEWROTARY (1 << 19)
> -#define MPMU_AWUCRM_RTC_ALARM (1 << 17)
> -#define MPMU_AWUCRM_AP2_TIMER_3 (1 << 13)
> -#define MPMU_AWUCRM_AP2_TIMER_2 (1 << 12)
> -#define MPMU_AWUCRM_AP2_TIMER_1 (1 << 11)
> -#define MPMU_AWUCRM_AP1_TIMER_3 (1 << 10)
> -#define MPMU_AWUCRM_AP1_TIMER_2 (1 << 9)
> -#define MPMU_AWUCRM_AP1_TIMER_1 (1 << 8)
> -#define MPMU_AWUCRM_WAKEUP(x) (1 << ((x) & 0x7))
> +#define MPMU_AWUCRM_AP_ASYNC_INT (1U << 25)
> +#define MPMU_AWUCRM_AP_FULL_IDLE (1U << 24)
> +#define MPMU_AWUCRM_SDH1 (1U << 23)
> +#define MPMU_AWUCRM_SDH2 (1U << 22)
> +#define MPMU_AWUCRM_KEYPRESS (1U << 21)
> +#define MPMU_AWUCRM_TRACKBALL (1U << 20)
> +#define MPMU_AWUCRM_NEWROTARY (1U << 19)
> +#define MPMU_AWUCRM_RTC_ALARM (1U << 17)
> +#define MPMU_AWUCRM_AP2_TIMER_3 (1U << 13)
> +#define MPMU_AWUCRM_AP2_TIMER_2 (1U << 12)
> +#define MPMU_AWUCRM_AP2_TIMER_1 (1U << 11)
> +#define MPMU_AWUCRM_AP1_TIMER_3 (1U << 10)
> +#define MPMU_AWUCRM_AP1_TIMER_2 (1U << 9)
> +#define MPMU_AWUCRM_AP1_TIMER_1 (1U << 8)
> +#define MPMU_AWUCRM_WAKEUP(x) (1U << ((x) & 0x7))
>
> enum {
> POWER_MODE_ACTIVE = 0,
There are errors with cppcheck
"Shifting signed 32-bit value by 31 bits is undefined behaviour errors"
This is just a mirror changing.
V2: Using BIT() macro instead of (1UL << nr)
Phong Tran (15):
arm: perf: cleanup cppcheck shifting error
ARM: davinci: cleanup cppcheck shifting errors
ARM: ep93xx: cleanup cppcheck shifting errors
ARM: exynos: cleanup cppcheck shifting error
ARM: footbridge: cleanup cppcheck shifting error
ARM: imx: cleanup cppcheck shifting errors
ARM: ks8695: cleanup cppcheck shifting error
ARM: mmp: cleanup cppcheck shifting errors
ARM: omap2: cleanup cppcheck shifting error
ARM: orion5x: cleanup cppcheck shifting errors
ARM: pxa: cleanup cppcheck shifting errors
ARM: vexpress: cleanup cppcheck shifting error
ARM: mm: cleanup cppcheck shifting errors
ARM: bpf: cleanup cppcheck shifting error
ARM: vfp: cleanup cppcheck shifting errors
arch/arm/kernel/perf_event_v7.c | 6 +-
arch/arm/mach-davinci/ddr2.h | 6 +-
arch/arm/mach-ep93xx/soc.h | 132 ++++++++++++++++++-------------------
arch/arm/mach-exynos/suspend.c | 2 +-
arch/arm/mach-footbridge/dc21285.c | 2 +-
arch/arm/mach-imx/iomux-mx3.h | 64 +++++++++---------
arch/arm/mach-ks8695/regs-pci.h | 4 +-
arch/arm/mach-mmp/pm-mmp2.h | 40 +++++------
arch/arm/mach-mmp/pm-pxa910.h | 76 ++++++++++-----------
arch/arm/mach-omap2/powerdomain.c | 2 +-
arch/arm/mach-orion5x/pci.c | 8 +--
arch/arm/mach-pxa/irq.c | 4 +-
arch/arm/mach-vexpress/spc.c | 12 ++--
arch/arm/mm/fault.h | 6 +-
arch/arm/net/bpf_jit_32.c | 2 +-
arch/arm/vfp/vfpinstr.h | 8 +--
16 files changed, 187 insertions(+), 187 deletions(-)
--
2.11.0
[arch/arm/mach-davinci/cpuidle.c:41]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
[arch/arm/mach-davinci/cpuidle.c:43]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-davinci/ddr2.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mach-davinci/ddr2.h b/arch/arm/mach-davinci/ddr2.h
index 4f7d7824b0c9..f2f56d16d7d5 100644
--- a/arch/arm/mach-davinci/ddr2.h
+++ b/arch/arm/mach-davinci/ddr2.h
@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0 */
#define DDR2_SDRCR_OFFSET 0xc
-#define DDR2_SRPD_BIT (1 << 23)
-#define DDR2_MCLKSTOPEN_BIT (1 << 30)
-#define DDR2_LPMODEN_BIT (1 << 31)
+#define DDR2_SRPD_BIT BIT(23)
+#define DDR2_MCLKSTOPEN_BIT BIT(30)
+#define DDR2_LPMODEN_BIT BIT(31)
--
2.11.0
[arch/arm/mach-footbridge/dc21285.c:236]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-footbridge/dc21285.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index 8b81a17f675d..edea41e0256f 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -230,7 +230,7 @@ static irqreturn_t dc21285_parity_irq(int irq, void *dev_id)
printk("\n");
cmd = *CSR_PCICMD & 0xffff;
- *CSR_PCICMD = cmd | 1 << 31;
+ *CSR_PCICMD = cmd | BIT(31);
/*
* back off this interrupt
--
2.11.0
[arch/arm/mach-mmp/pm-mmp2.c:121]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-mmp/pm-mmp2.c:136]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-mmp/pm-mmp2.c:244]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-mmp/pm-pxa910.c:141]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
[arch/arm/mach-mmp/pm-pxa910.c:159]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-mmp/pm-mmp2.h | 40 +++++++++++------------
arch/arm/mach-mmp/pm-pxa910.h | 76 +++++++++++++++++++++----------------------
2 files changed, 58 insertions(+), 58 deletions(-)
diff --git a/arch/arm/mach-mmp/pm-mmp2.h b/arch/arm/mach-mmp/pm-mmp2.h
index 70299a9450d3..631ba71abdbd 100644
--- a/arch/arm/mach-mmp/pm-mmp2.h
+++ b/arch/arm/mach-mmp/pm-mmp2.h
@@ -12,37 +12,37 @@
#include "addr-map.h"
#define APMU_PJ_IDLE_CFG APMU_REG(0x018)
-#define APMU_PJ_IDLE_CFG_PJ_IDLE (1 << 1)
-#define APMU_PJ_IDLE_CFG_PJ_PWRDWN (1 << 5)
+#define APMU_PJ_IDLE_CFG_PJ_IDLE BIT(1)
+#define APMU_PJ_IDLE_CFG_PJ_PWRDWN BIT(5)
#define APMU_PJ_IDLE_CFG_PWR_SW(x) ((x) << 16)
-#define APMU_PJ_IDLE_CFG_L2_PWR_SW (1 << 19)
+#define APMU_PJ_IDLE_CFG_L2_PWR_SW BIT(19)
#define APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK (3 << 28)
#define APMU_SRAM_PWR_DWN APMU_REG(0x08c)
#define MPMU_SCCR MPMU_REG(0x038)
#define MPMU_PCR_PJ MPMU_REG(0x1000)
-#define MPMU_PCR_PJ_AXISD (1 << 31)
-#define MPMU_PCR_PJ_SLPEN (1 << 29)
-#define MPMU_PCR_PJ_SPSD (1 << 28)
-#define MPMU_PCR_PJ_DDRCORSD (1 << 27)
-#define MPMU_PCR_PJ_APBSD (1 << 26)
-#define MPMU_PCR_PJ_INTCLR (1 << 24)
-#define MPMU_PCR_PJ_SLPWP0 (1 << 23)
-#define MPMU_PCR_PJ_SLPWP1 (1 << 22)
-#define MPMU_PCR_PJ_SLPWP2 (1 << 21)
-#define MPMU_PCR_PJ_SLPWP3 (1 << 20)
-#define MPMU_PCR_PJ_VCTCXOSD (1 << 19)
-#define MPMU_PCR_PJ_SLPWP4 (1 << 18)
-#define MPMU_PCR_PJ_SLPWP5 (1 << 17)
-#define MPMU_PCR_PJ_SLPWP6 (1 << 16)
-#define MPMU_PCR_PJ_SLPWP7 (1 << 15)
+#define MPMU_PCR_PJ_AXISD BIT(31)
+#define MPMU_PCR_PJ_SLPEN BIT(29)
+#define MPMU_PCR_PJ_SPSD BIT(28)
+#define MPMU_PCR_PJ_DDRCORSD BIT(27)
+#define MPMU_PCR_PJ_APBSD BIT(26)
+#define MPMU_PCR_PJ_INTCLR BIT(24)
+#define MPMU_PCR_PJ_SLPWP0 BIT(23)
+#define MPMU_PCR_PJ_SLPWP1 BIT(22)
+#define MPMU_PCR_PJ_SLPWP2 BIT(21)
+#define MPMU_PCR_PJ_SLPWP3 BIT(20)
+#define MPMU_PCR_PJ_VCTCXOSD BIT(19)
+#define MPMU_PCR_PJ_SLPWP4 BIT(18)
+#define MPMU_PCR_PJ_SLPWP5 BIT(17)
+#define MPMU_PCR_PJ_SLPWP6 BIT(16)
+#define MPMU_PCR_PJ_SLPWP7 BIT(15)
#define MPMU_PLL2_CTRL1 MPMU_REG(0x0414)
#define MPMU_CGR_PJ MPMU_REG(0x1024)
#define MPMU_WUCRM_PJ MPMU_REG(0x104c)
-#define MPMU_WUCRM_PJ_WAKEUP(x) (1 << (x))
-#define MPMU_WUCRM_PJ_RTC_ALARM (1 << 17)
+#define MPMU_WUCRM_PJ_WAKEUP(x) BIT((x))
+#define MPMU_WUCRM_PJ_RTC_ALARM BIT(17)
enum {
POWER_MODE_ACTIVE = 0,
diff --git a/arch/arm/mach-mmp/pm-pxa910.h b/arch/arm/mach-mmp/pm-pxa910.h
index 8e6344adaf51..f4a0b9811e87 100644
--- a/arch/arm/mach-mmp/pm-pxa910.h
+++ b/arch/arm/mach-mmp/pm-pxa910.h
@@ -10,54 +10,54 @@
#define __PXA910_PM_H__
#define APMU_MOH_IDLE_CFG APMU_REG(0x0018)
-#define APMU_MOH_IDLE_CFG_MOH_IDLE (1 << 1)
-#define APMU_MOH_IDLE_CFG_MOH_PWRDWN (1 << 5)
-#define APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN (1 << 6)
+#define APMU_MOH_IDLE_CFG_MOH_IDLE BIT(1)
+#define APMU_MOH_IDLE_CFG_MOH_PWRDWN BIT(5)
+#define APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN BIT(6)
#define APMU_MOH_IDLE_CFG_MOH_PWR_SW(x) (((x) & 0x3) << 16)
#define APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(x) (((x) & 0x3) << 18)
-#define APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ (1 << 21)
-#define APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN (1 << 20)
+#define APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ BIT(21)
+#define APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN BIT(20)
#define APMU_SQU_CLK_GATE_CTRL APMU_REG(0x001c)
#define APMU_MC_HW_SLP_TYPE APMU_REG(0x00b0)
#define MPMU_FCCR MPMU_REG(0x0008)
#define MPMU_APCR MPMU_REG(0x1000)
-#define MPMU_APCR_AXISD (1 << 31)
-#define MPMU_APCR_DSPSD (1 << 30)
-#define MPMU_APCR_SLPEN (1 << 29)
-#define MPMU_APCR_DTCMSD (1 << 28)
-#define MPMU_APCR_DDRCORSD (1 << 27)
-#define MPMU_APCR_APBSD (1 << 26)
-#define MPMU_APCR_BBSD (1 << 25)
-#define MPMU_APCR_SLPWP0 (1 << 23)
-#define MPMU_APCR_SLPWP1 (1 << 22)
-#define MPMU_APCR_SLPWP2 (1 << 21)
-#define MPMU_APCR_SLPWP3 (1 << 20)
-#define MPMU_APCR_VCTCXOSD (1 << 19)
-#define MPMU_APCR_SLPWP4 (1 << 18)
-#define MPMU_APCR_SLPWP5 (1 << 17)
-#define MPMU_APCR_SLPWP6 (1 << 16)
-#define MPMU_APCR_SLPWP7 (1 << 15)
-#define MPMU_APCR_MSASLPEN (1 << 14)
-#define MPMU_APCR_STBYEN (1 << 13)
+#define MPMU_APCR_AXISD BIT(31)
+#define MPMU_APCR_DSPSD BIT(30)
+#define MPMU_APCR_SLPEN BIT(29)
+#define MPMU_APCR_DTCMSD BIT(28)
+#define MPMU_APCR_DDRCORSD BIT(27)
+#define MPMU_APCR_APBSD BIT(26)
+#define MPMU_APCR_BBSD BIT(25)
+#define MPMU_APCR_SLPWP0 BIT(23)
+#define MPMU_APCR_SLPWP1 BIT(22)
+#define MPMU_APCR_SLPWP2 BIT(21)
+#define MPMU_APCR_SLPWP3 BIT(20)
+#define MPMU_APCR_VCTCXOSD BIT(19)
+#define MPMU_APCR_SLPWP4 BIT(18)
+#define MPMU_APCR_SLPWP5 BIT(17)
+#define MPMU_APCR_SLPWP6 BIT(16)
+#define MPMU_APCR_SLPWP7 BIT(15)
+#define MPMU_APCR_MSASLPEN BIT(14)
+#define MPMU_APCR_STBYEN BIT(13)
#define MPMU_AWUCRM MPMU_REG(0x104c)
-#define MPMU_AWUCRM_AP_ASYNC_INT (1 << 25)
-#define MPMU_AWUCRM_AP_FULL_IDLE (1 << 24)
-#define MPMU_AWUCRM_SDH1 (1 << 23)
-#define MPMU_AWUCRM_SDH2 (1 << 22)
-#define MPMU_AWUCRM_KEYPRESS (1 << 21)
-#define MPMU_AWUCRM_TRACKBALL (1 << 20)
-#define MPMU_AWUCRM_NEWROTARY (1 << 19)
-#define MPMU_AWUCRM_RTC_ALARM (1 << 17)
-#define MPMU_AWUCRM_AP2_TIMER_3 (1 << 13)
-#define MPMU_AWUCRM_AP2_TIMER_2 (1 << 12)
-#define MPMU_AWUCRM_AP2_TIMER_1 (1 << 11)
-#define MPMU_AWUCRM_AP1_TIMER_3 (1 << 10)
-#define MPMU_AWUCRM_AP1_TIMER_2 (1 << 9)
-#define MPMU_AWUCRM_AP1_TIMER_1 (1 << 8)
-#define MPMU_AWUCRM_WAKEUP(x) (1 << ((x) & 0x7))
+#define MPMU_AWUCRM_AP_ASYNC_INT BIT(25)
+#define MPMU_AWUCRM_AP_FULL_IDLE BIT(24)
+#define MPMU_AWUCRM_SDH1 BIT(23)
+#define MPMU_AWUCRM_SDH2 BIT(22)
+#define MPMU_AWUCRM_KEYPRESS BIT(21)
+#define MPMU_AWUCRM_TRACKBALL BIT(20)
+#define MPMU_AWUCRM_NEWROTARY BIT(19)
+#define MPMU_AWUCRM_RTC_ALARM BIT(17)
+#define MPMU_AWUCRM_AP2_TIMER_3 BIT(13)
+#define MPMU_AWUCRM_AP2_TIMER_2 BIT(12)
+#define MPMU_AWUCRM_AP2_TIMER_1 BIT(11)
+#define MPMU_AWUCRM_AP1_TIMER_3 BIT(10)
+#define MPMU_AWUCRM_AP1_TIMER_2 BIT(9)
+#define MPMU_AWUCRM_AP1_TIMER_1 BIT(8)
+#define MPMU_AWUCRM_WAKEUP(x) BIT(((x) & 0x7))
enum {
POWER_MODE_ACTIVE = 0,
--
2.11.0
[arch/arm/mach-ep93xx/clock.c:102]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-ep93xx/clock.c:132]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-ep93xx/clock.c:140]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-ep93xx/core.c:1001]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-ep93xx/core.c:1002]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-ep93xx/soc.h | 132 ++++++++++++++++++++++-----------------------
1 file changed, 66 insertions(+), 66 deletions(-)
diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h
index f2dace1c9154..250c82f8b0a1 100644
--- a/arch/arm/mach-ep93xx/soc.h
+++ b/arch/arm/mach-ep93xx/soc.h
@@ -109,89 +109,89 @@
#define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x))
#define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00)
#define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04)
-#define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31)
-#define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29)
-#define EP93XX_SYSCON_PWRCNT_USH_EN (1<<28)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 (1<<27)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 (1<<26)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 (1<<25)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 (1<<24)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 (1<<23)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 (1<<22)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 (1<<21)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 (1<<20)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 (1<<19)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 (1<<18)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 (1<<17)
-#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 (1<<16)
+#define EP93XX_SYSCON_PWRCNT_FIR_EN BIT(31)
+#define EP93XX_SYSCON_PWRCNT_UARTBAUD BIT(29)
+#define EP93XX_SYSCON_PWRCNT_USH_EN BIT(28)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 BIT(27)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 BIT(26)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 BIT(25)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 BIT(24)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 BIT(23)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 BIT(22)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 BIT(21)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 BIT(20)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 BIT(19)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 BIT(18)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 BIT(17)
+#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 BIT(16)
#define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08)
#define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c)
#define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20)
-#define EP93XX_SYSCON_CLKSET1_NBYP1 (1<<23)
+#define EP93XX_SYSCON_CLKSET1_NBYP1 BIT(23)
#define EP93XX_SYSCON_CLKSET2 EP93XX_SYSCON_REG(0x24)
-#define EP93XX_SYSCON_CLKSET2_NBYP2 (1<<19)
-#define EP93XX_SYSCON_CLKSET2_PLL2_EN (1<<18)
+#define EP93XX_SYSCON_CLKSET2_NBYP2 BIT(19)
+#define EP93XX_SYSCON_CLKSET2_PLL2_EN BIT(18)
#define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80)
-#define EP93XX_SYSCON_DEVCFG_SWRST (1<<31)
-#define EP93XX_SYSCON_DEVCFG_D1ONG (1<<30)
-#define EP93XX_SYSCON_DEVCFG_D0ONG (1<<29)
-#define EP93XX_SYSCON_DEVCFG_IONU2 (1<<28)
-#define EP93XX_SYSCON_DEVCFG_GONK (1<<27)
-#define EP93XX_SYSCON_DEVCFG_TONG (1<<26)
-#define EP93XX_SYSCON_DEVCFG_MONG (1<<25)
-#define EP93XX_SYSCON_DEVCFG_U3EN (1<<24)
-#define EP93XX_SYSCON_DEVCFG_CPENA (1<<23)
-#define EP93XX_SYSCON_DEVCFG_A2ONG (1<<22)
-#define EP93XX_SYSCON_DEVCFG_A1ONG (1<<21)
-#define EP93XX_SYSCON_DEVCFG_U2EN (1<<20)
-#define EP93XX_SYSCON_DEVCFG_EXVC (1<<19)
-#define EP93XX_SYSCON_DEVCFG_U1EN (1<<18)
-#define EP93XX_SYSCON_DEVCFG_TIN (1<<17)
-#define EP93XX_SYSCON_DEVCFG_HC3IN (1<<15)
-#define EP93XX_SYSCON_DEVCFG_HC3EN (1<<14)
-#define EP93XX_SYSCON_DEVCFG_HC1IN (1<<13)
-#define EP93XX_SYSCON_DEVCFG_HC1EN (1<<12)
-#define EP93XX_SYSCON_DEVCFG_HONIDE (1<<11)
-#define EP93XX_SYSCON_DEVCFG_GONIDE (1<<10)
-#define EP93XX_SYSCON_DEVCFG_PONG (1<<9)
-#define EP93XX_SYSCON_DEVCFG_EONIDE (1<<8)
-#define EP93XX_SYSCON_DEVCFG_I2SONSSP (1<<7)
-#define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1<<6)
-#define EP93XX_SYSCON_DEVCFG_RASONP3 (1<<4)
-#define EP93XX_SYSCON_DEVCFG_RAS (1<<3)
-#define EP93XX_SYSCON_DEVCFG_ADCPD (1<<2)
-#define EP93XX_SYSCON_DEVCFG_KEYS (1<<1)
-#define EP93XX_SYSCON_DEVCFG_SHENA (1<<0)
+#define EP93XX_SYSCON_DEVCFG_SWRST BIT(31)
+#define EP93XX_SYSCON_DEVCFG_D1ONG BIT(30)
+#define EP93XX_SYSCON_DEVCFG_D0ONG BIT(29)
+#define EP93XX_SYSCON_DEVCFG_IONU2 BIT(28)
+#define EP93XX_SYSCON_DEVCFG_GONK BIT(27)
+#define EP93XX_SYSCON_DEVCFG_TONG BIT(26)
+#define EP93XX_SYSCON_DEVCFG_MONG BIT(25)
+#define EP93XX_SYSCON_DEVCFG_U3EN BIT(24)
+#define EP93XX_SYSCON_DEVCFG_CPENA BIT(23)
+#define EP93XX_SYSCON_DEVCFG_A2ONG BIT(22)
+#define EP93XX_SYSCON_DEVCFG_A1ONG BIT(21)
+#define EP93XX_SYSCON_DEVCFG_U2EN BIT(20)
+#define EP93XX_SYSCON_DEVCFG_EXVC BIT(19)
+#define EP93XX_SYSCON_DEVCFG_U1EN BIT(18)
+#define EP93XX_SYSCON_DEVCFG_TIN BIT(17)
+#define EP93XX_SYSCON_DEVCFG_HC3IN BIT(15)
+#define EP93XX_SYSCON_DEVCFG_HC3EN BIT(14)
+#define EP93XX_SYSCON_DEVCFG_HC1IN BIT(13)
+#define EP93XX_SYSCON_DEVCFG_HC1EN BIT(12)
+#define EP93XX_SYSCON_DEVCFG_HONIDE BIT(11)
+#define EP93XX_SYSCON_DEVCFG_GONIDE BIT(10)
+#define EP93XX_SYSCON_DEVCFG_PONG BIT(9)
+#define EP93XX_SYSCON_DEVCFG_EONIDE BIT(8)
+#define EP93XX_SYSCON_DEVCFG_I2SONSSP BIT(7)
+#define EP93XX_SYSCON_DEVCFG_I2SONAC97 BIT(6)
+#define EP93XX_SYSCON_DEVCFG_RASONP3 BIT(4)
+#define EP93XX_SYSCON_DEVCFG_RAS BIT(3)
+#define EP93XX_SYSCON_DEVCFG_ADCPD BIT(2)
+#define EP93XX_SYSCON_DEVCFG_KEYS BIT(1)
+#define EP93XX_SYSCON_DEVCFG_SHENA BIT(0)
#define EP93XX_SYSCON_VIDCLKDIV EP93XX_SYSCON_REG(0x84)
-#define EP93XX_SYSCON_CLKDIV_ENABLE (1<<15)
-#define EP93XX_SYSCON_CLKDIV_ESEL (1<<14)
-#define EP93XX_SYSCON_CLKDIV_PSEL (1<<13)
+#define EP93XX_SYSCON_CLKDIV_ENABLE BIT(15)
+#define EP93XX_SYSCON_CLKDIV_ESEL BIT(14)
+#define EP93XX_SYSCON_CLKDIV_PSEL BIT(13)
#define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8
#define EP93XX_SYSCON_I2SCLKDIV EP93XX_SYSCON_REG(0x8c)
-#define EP93XX_SYSCON_I2SCLKDIV_SENA (1<<31)
-#define EP93XX_SYSCON_I2SCLKDIV_ORIDE (1<<29)
-#define EP93XX_SYSCON_I2SCLKDIV_SPOL (1<<19)
+#define EP93XX_SYSCON_I2SCLKDIV_SENA BIT(31)
+#define EP93XX_SYSCON_I2SCLKDIV_ORIDE BIT(29)
+#define EP93XX_SYSCON_I2SCLKDIV_SPOL BIT(19)
#define EP93XX_I2SCLKDIV_SDIV (1 << 16)
#define EP93XX_I2SCLKDIV_LRDIV32 (0 << 17)
#define EP93XX_I2SCLKDIV_LRDIV64 (1 << 17)
#define EP93XX_I2SCLKDIV_LRDIV128 (2 << 17)
#define EP93XX_I2SCLKDIV_LRDIV_MASK (3 << 17)
#define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN (1<<15)
-#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN BIT(31)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV BIT(16)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN BIT(15)
+#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV BIT(0)
#define EP93XX_SYSCON_SYSCFG EP93XX_SYSCON_REG(0x9c)
#define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000)
#define EP93XX_SYSCON_SYSCFG_REV_SHIFT (28)
-#define EP93XX_SYSCON_SYSCFG_SBOOT (1<<8)
-#define EP93XX_SYSCON_SYSCFG_LCSN7 (1<<7)
-#define EP93XX_SYSCON_SYSCFG_LCSN6 (1<<6)
-#define EP93XX_SYSCON_SYSCFG_LASDO (1<<5)
-#define EP93XX_SYSCON_SYSCFG_LEEDA (1<<4)
-#define EP93XX_SYSCON_SYSCFG_LEECLK (1<<3)
-#define EP93XX_SYSCON_SYSCFG_LCSN2 (1<<1)
-#define EP93XX_SYSCON_SYSCFG_LCSN1 (1<<0)
+#define EP93XX_SYSCON_SYSCFG_SBOOT BIT(8)
+#define EP93XX_SYSCON_SYSCFG_LCSN7 BIT(7)
+#define EP93XX_SYSCON_SYSCFG_LCSN6 BIT(6)
+#define EP93XX_SYSCON_SYSCFG_LASDO BIT(5)
+#define EP93XX_SYSCON_SYSCFG_LEEDA BIT(4)
+#define EP93XX_SYSCON_SYSCFG_LEECLK BIT(3)
+#define EP93XX_SYSCON_SYSCFG_LCSN2 BIT(1)
+#define EP93XX_SYSCON_SYSCFG_LCSN1 BIT(0)
#define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
/* EP93xx System Controller software locked register write */
--
2.11.0
fix "Shifting signed 32-bit value by 31 bits is undefined behaviour
errors"
[arch/arm/kernel/perf_event_v7.c:1080]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
[arch/arm/kernel/perf_event_v7.c:1436]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
[arch/arm/kernel/perf_event_v7.c:1783]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/kernel/perf_event_v7.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index a4fb0f8b8f84..2924d7910b10 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -697,9 +697,9 @@ static struct attribute_group armv7_pmuv2_events_attr_group = {
/*
* Event filters for PMUv2
*/
-#define ARMV7_EXCLUDE_PL1 (1 << 31)
-#define ARMV7_EXCLUDE_USER (1 << 30)
-#define ARMV7_INCLUDE_HYP (1 << 27)
+#define ARMV7_EXCLUDE_PL1 BIT(31)
+#define ARMV7_EXCLUDE_USER BIT(30)
+#define ARMV7_INCLUDE_HYP BIT(27)
/*
* Secure debug enable reg
--
2.11.0
[arch/arm/mach-exynos/suspend.c:288]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-exynos/suspend.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index be122af0de8f..b6a73dc5bde4 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -285,7 +285,7 @@ static void exynos_pm_set_wakeup_mask(void)
* Set wake-up mask registers
* EXYNOS_EINT_WAKEUP_MASK is set by pinctrl driver in late suspend.
*/
- pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
+ pmu_raw_writel(exynos_irqwake_intmask & ~(BIT(31)), S5P_WAKEUP_MASK);
}
static void exynos_pm_enter_sleep_mode(void)
--
2.11.0
[arch/arm/mach-pxa/irq.c:117]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
[arch/arm/mach-pxa/irq.c:131]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-pxa/irq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 74efc3ab595f..cbbb5cfecb60 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -35,9 +35,9 @@
#define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \
((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \
(0x144 + (((i) - 64) << 2)))
-#define ICHP_VAL_IRQ (1 << 31)
+#define ICHP_VAL_IRQ BIT(31)
#define ICHP_IRQ(i) (((i) >> 16) & 0x7fff)
-#define IPR_VALID (1 << 31)
+#define IPR_VALID BIT(31)
#define MAX_INTERNAL_IRQS 128
--
2.11.0
[arch/arm/mach-vexpress/spc.c:366]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-vexpress/spc.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-vexpress/spc.c
index 0f5381d13494..425ce633667a 100644
--- a/arch/arm/mach-vexpress/spc.c
+++ b/arch/arm/mach-vexpress/spc.c
@@ -57,8 +57,8 @@
/* SPC CPU/cluster reset statue */
#define STANDBYWFI_STAT 0x3c
-#define STANDBYWFI_STAT_A15_CPU_MASK(cpu) (1 << (cpu))
-#define STANDBYWFI_STAT_A7_CPU_MASK(cpu) (1 << (3 + (cpu)))
+#define STANDBYWFI_STAT_A15_CPU_MASK(cpu) BIT((cpu))
+#define STANDBYWFI_STAT_A7_CPU_MASK(cpu) BIT((3 + (cpu)))
/* SPC system config interface registers */
#define SYSCFG_WDATA 0x70
@@ -69,7 +69,7 @@
#define A7_PERFVAL_BASE 0xC30
/* Config interface control bits */
-#define SYSCFG_START (1 << 31)
+#define SYSCFG_START BIT(31)
#define SYSCFG_SCC (6 << 20)
#define SYSCFG_STAT (14 << 20)
@@ -90,8 +90,8 @@
#define CA15_DVFS 0
#define CA7_DVFS 1
#define SPC_SYS_CFG 2
-#define STAT_COMPLETE(type) ((1 << 0) << (type << 2))
-#define STAT_ERR(type) ((1 << 1) << (type << 2))
+#define STAT_COMPLETE(type) (BIT(0) << (type << 2))
+#define STAT_ERR(type) (BIT(1) << (type << 2))
#define RESPONSE_MASK(type) (STAT_COMPLETE(type) | STAT_ERR(type))
struct ve_spc_opp {
@@ -162,7 +162,7 @@ void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set)
if (cluster >= MAX_CLUSTERS)
return;
- mask = 1 << cpu;
+ mask = BIT(cpu);
if (!cluster_is_a15(cluster))
mask <<= 4;
--
2.11.0
[arch/arm/mach-orion5x/pci.c:281]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
[arch/arm/mach-orion5x/pci.c:305]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
---
arch/arm/mach-orion5x/pci.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 76951bfbacf5..f47668530d5e 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -200,13 +200,13 @@ static int __init pcie_setup(struct pci_sys_data *sys)
/*
* PCI_MODE bits
*/
-#define PCI_MODE_64BIT (1 << 2)
-#define PCI_MODE_PCIX ((1 << 4) | (1 << 5))
+#define PCI_MODE_64BIT BIT(2)
+#define PCI_MODE_PCIX (BIT(4) | BIT(5))
/*
* PCI_CMD bits
*/
-#define PCI_CMD_HOST_REORDER (1 << 29)
+#define PCI_CMD_HOST_REORDER BIT(29)
/*
* PCI_P2P_CONF bits
@@ -223,7 +223,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
-#define PCI_CONF_ADDR_EN (1 << 31)
+#define PCI_CONF_ADDR_EN BIT(31)
/*
* Internal configuration space
--
2.11.0
[arch/arm/mach-imx/iomux-mx3.h:93]: (error) Shifting signed 32-bit value
by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-imx/iomux-mx3.h | 64 +++++++++++++++++++++----------------------
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/arch/arm/mach-imx/iomux-mx3.h b/arch/arm/mach-imx/iomux-mx3.h
index 99270a183d47..028b683866c3 100644
--- a/arch/arm/mach-imx/iomux-mx3.h
+++ b/arch/arm/mach-imx/iomux-mx3.h
@@ -59,38 +59,38 @@ enum iomux_pad_config {
* various IOMUX general purpose functions
*/
enum iomux_gp_func {
- MUX_PGP_FIRI = 1 << 0,
- MUX_DDR_MODE = 1 << 1,
- MUX_PGP_CSPI_BB = 1 << 2,
- MUX_PGP_ATA_1 = 1 << 3,
- MUX_PGP_ATA_2 = 1 << 4,
- MUX_PGP_ATA_3 = 1 << 5,
- MUX_PGP_ATA_4 = 1 << 6,
- MUX_PGP_ATA_5 = 1 << 7,
- MUX_PGP_ATA_6 = 1 << 8,
- MUX_PGP_ATA_7 = 1 << 9,
- MUX_PGP_ATA_8 = 1 << 10,
- MUX_PGP_UH2 = 1 << 11,
- MUX_SDCTL_CSD0_SEL = 1 << 12,
- MUX_SDCTL_CSD1_SEL = 1 << 13,
- MUX_CSPI1_UART3 = 1 << 14,
- MUX_EXTDMAREQ2_MBX_SEL = 1 << 15,
- MUX_TAMPER_DETECT_EN = 1 << 16,
- MUX_PGP_USB_4WIRE = 1 << 17,
- MUX_PGP_USB_COMMON = 1 << 18,
- MUX_SDHC_MEMSTICK1 = 1 << 19,
- MUX_SDHC_MEMSTICK2 = 1 << 20,
- MUX_PGP_SPLL_BYP = 1 << 21,
- MUX_PGP_UPLL_BYP = 1 << 22,
- MUX_PGP_MSHC1_CLK_SEL = 1 << 23,
- MUX_PGP_MSHC2_CLK_SEL = 1 << 24,
- MUX_CSPI3_UART5_SEL = 1 << 25,
- MUX_PGP_ATA_9 = 1 << 26,
- MUX_PGP_USB_SUSPEND = 1 << 27,
- MUX_PGP_USB_OTG_LOOPBACK = 1 << 28,
- MUX_PGP_USB_HS1_LOOPBACK = 1 << 29,
- MUX_PGP_USB_HS2_LOOPBACK = 1 << 30,
- MUX_CLKO_DDR_MODE = 1 << 31,
+ MUX_PGP_FIRI = BIT(0),
+ MUX_DDR_MODE = BIT(1),
+ MUX_PGP_CSPI_BB = BIT(2),
+ MUX_PGP_ATA_1 = BIT(3),
+ MUX_PGP_ATA_2 = BIT(4),
+ MUX_PGP_ATA_3 = BIT(5),
+ MUX_PGP_ATA_4 = BIT(6),
+ MUX_PGP_ATA_5 = BIT(7),
+ MUX_PGP_ATA_6 = BIT(8),
+ MUX_PGP_ATA_7 = BIT(9),
+ MUX_PGP_ATA_8 = BIT(10),
+ MUX_PGP_UH2 = BIT(11),
+ MUX_SDCTL_CSD0_SEL = BIT(12),
+ MUX_SDCTL_CSD1_SEL = BIT(13),
+ MUX_CSPI1_UART3 = BIT(14),
+ MUX_EXTDMAREQ2_MBX_SEL = BIT(15),
+ MUX_TAMPER_DETECT_EN = BIT(16),
+ MUX_PGP_USB_4WIRE = BIT(17),
+ MUX_PGP_USB_COMMON = BIT(18),
+ MUX_SDHC_MEMSTICK1 = BIT(19),
+ MUX_SDHC_MEMSTICK2 = BIT(20),
+ MUX_PGP_SPLL_BYP = BIT(21),
+ MUX_PGP_UPLL_BYP = BIT(22),
+ MUX_PGP_MSHC1_CLK_SEL = BIT(23),
+ MUX_PGP_MSHC2_CLK_SEL = BIT(24),
+ MUX_CSPI3_UART5_SEL = BIT(25),
+ MUX_PGP_ATA_9 = BIT(26),
+ MUX_PGP_USB_SUSPEND = BIT(27),
+ MUX_PGP_USB_OTG_LOOPBACK = BIT(28),
+ MUX_PGP_USB_HS1_LOOPBACK = BIT(29),
+ MUX_PGP_USB_HS2_LOOPBACK = BIT(30),
+ MUX_CLKO_DDR_MODE = BIT(31),
};
/*
--
2.11.0
[arch/arm/mach-ks8695/pci.c:33]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-ks8695/regs-pci.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-ks8695/regs-pci.h b/arch/arm/mach-ks8695/regs-pci.h
index 75a9db6edbd9..7d28a83bb574 100644
--- a/arch/arm/mach-ks8695/regs-pci.h
+++ b/arch/arm/mach-ks8695/regs-pci.h
@@ -45,9 +45,9 @@
-#define CFRV_GUEST (1 << 23)
+#define CFRV_GUEST BIT(23)
#define PBCA_TYPE1 (1)
-#define PBCA_ENABLE (1 << 31)
+#define PBCA_ENABLE BIT(31)
--
2.11.0
On Mon, Jun 24, 2019 at 08:51:00PM +0700, Phong Tran wrote:
> [arch/arm/mach-orion5x/pci.c:281]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
> [arch/arm/mach-orion5x/pci.c:305]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
>
> Signed-off-by: Phong Tran <[email protected]>
> Reviewed-by: Andrew Lunn <[email protected]>
Thanks for swapping to the BIT macro.
Andrew
[arch/arm/net/bpf_jit_32.c:618]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/net/bpf_jit_32.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
index adff54c312bf..4e8ad26305ca 100644
--- a/arch/arm/net/bpf_jit_32.c
+++ b/arch/arm/net/bpf_jit_32.c
@@ -612,7 +612,7 @@ static inline void emit_a32_mov_se_i64(const bool is64, const s8 dst[],
const u32 val, struct jit_ctx *ctx) {
u64 val64 = val;
- if (is64 && (val & (1<<31)))
+ if (is64 && (val & (BIT(31))))
val64 |= 0xffffffff00000000ULL;
emit_a32_mov_i64(dst, val64, ctx);
}
--
2.11.0
[arch/arm/mach-omap2/powerdomain.c:190]: (error) Shifting signed 32-bit
value by 31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-omap2/powerdomain.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 1cbac76136d4..886961726380 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -35,7 +35,7 @@
#include "soc.h"
#include "pm.h"
-#define PWRDM_TRACE_STATES_FLAG (1<<31)
+#define PWRDM_TRACE_STATES_FLAG BIT(31)
void pwrdms_save_context(void);
void pwrdms_restore_context(void);
--
2.11.0
[arch/arm/mm/alignment.c:875]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
[arch/arm/mm/fault.c:556]: (error) Shifting signed 32-bit value by 31
bits is undefined behaviour
[arch/arm/mm/fault.c:585]: (error) Shifting signed 32-bit value by 31
bits is undefined behaviour
[arch/arm/mm/fault.c:219]: (error) Shifting signed 32-bit value by 31
bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mm/fault.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mm/fault.h b/arch/arm/mm/fault.h
index c063708fa503..8a706cb7f21d 100644
--- a/arch/arm/mm/fault.h
+++ b/arch/arm/mm/fault.h
@@ -5,9 +5,9 @@
/*
* Fault status register encodings. We steal bit 31 for our own purposes.
*/
-#define FSR_LNX_PF (1 << 31)
-#define FSR_WRITE (1 << 11)
-#define FSR_FS4 (1 << 10)
+#define FSR_LNX_PF BIT(31)
+#define FSR_WRITE BIT(11)
+#define FSR_FS4 BIT(10)
#define FSR_FS3_0 (15)
#define FSR_FS5_0 (0x3f)
--
2.11.0
[arch/arm/vfp/vfpdouble.c:397]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
[arch/arm/vfp/vfpdouble.c:407]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
[arch/arm/vfp/vfpmodule.c:263]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
[arch/arm/vfp/vfpmodule.c:264]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
[arch/arm/vfp/vfpsingle.c:441]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
[arch/arm/vfp/vfpsingle.c:451]: (error) Shifting signed 32-bit value by
31 bits is undefined behaviour
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/vfp/vfpinstr.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/vfp/vfpinstr.h b/arch/arm/vfp/vfpinstr.h
index 38dc154e39ff..8951637c58ff 100644
--- a/arch/arm/vfp/vfpinstr.h
+++ b/arch/arm/vfp/vfpinstr.h
@@ -57,10 +57,10 @@
#define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00)
-#define FPSCR_N (1 << 31)
-#define FPSCR_Z (1 << 30)
-#define FPSCR_C (1 << 29)
-#define FPSCR_V (1 << 28)
+#define FPSCR_N BIT(31)
+#define FPSCR_Z BIT(30)
+#define FPSCR_C BIT(29)
+#define FPSCR_V BIT(28)
/*
* Since we aren't building with -mfpu=vfp, we need to code
--
2.11.0
On Mon, Jun 24, 2019 at 08:50:54PM +0700, Phong Tran wrote:
> [arch/arm/mach-exynos/suspend.c:288]: (error) Shifting signed 32-bit
> value by 31 bits is undefined behaviour
>
> Signed-off-by: Phong Tran <[email protected]>
> ---
> arch/arm/mach-exynos/suspend.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
> index be122af0de8f..b6a73dc5bde4 100644
> --- a/arch/arm/mach-exynos/suspend.c
> +++ b/arch/arm/mach-exynos/suspend.c
> @@ -285,7 +285,7 @@ static void exynos_pm_set_wakeup_mask(void)
> * Set wake-up mask registers
> * EXYNOS_EINT_WAKEUP_MASK is set by pinctrl driver in late suspend.
> */
> - pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
> + pmu_raw_writel(exynos_irqwake_intmask & ~(BIT(31)), S5P_WAKEUP_MASK);
Parens around BIT() are no longer required.
> }
>
> static void exynos_pm_enter_sleep_mode(void)
> --
> 2.11.0
>
>
--
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On Mon, Jun 24, 2019 at 08:50:58PM +0700, Phong Tran wrote:
> #define MPMU_PLL2_CTRL1 MPMU_REG(0x0414)
> #define MPMU_CGR_PJ MPMU_REG(0x1024)
> #define MPMU_WUCRM_PJ MPMU_REG(0x104c)
> -#define MPMU_WUCRM_PJ_WAKEUP(x) (1 << (x))
> -#define MPMU_WUCRM_PJ_RTC_ALARM (1 << 17)
> +#define MPMU_WUCRM_PJ_WAKEUP(x) BIT((x))
Extra parens not required.
> +#define MPMU_AWUCRM_WAKEUP(x) BIT(((x) & 0x7))
Ditto.
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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On Mon, Jun 24, 2019 at 08:51:02PM +0700, Phong Tran wrote:
> [arch/arm/mach-vexpress/spc.c:366]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
>
> Signed-off-by: Phong Tran <[email protected]>
> ---
> arch/arm/mach-vexpress/spc.c | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-vexpress/spc.c
> index 0f5381d13494..425ce633667a 100644
> --- a/arch/arm/mach-vexpress/spc.c
> +++ b/arch/arm/mach-vexpress/spc.c
> @@ -57,8 +57,8 @@
>
> /* SPC CPU/cluster reset statue */
> #define STANDBYWFI_STAT 0x3c
> -#define STANDBYWFI_STAT_A15_CPU_MASK(cpu) (1 << (cpu))
> -#define STANDBYWFI_STAT_A7_CPU_MASK(cpu) (1 << (3 + (cpu)))
> +#define STANDBYWFI_STAT_A15_CPU_MASK(cpu) BIT((cpu))
> +#define STANDBYWFI_STAT_A7_CPU_MASK(cpu) BIT((3 + (cpu)))
I guess you did this using a script, however, in the above two cases,
you don't need the extra parens - it was necessary in the original
though.
>
> /* SPC system config interface registers */
> #define SYSCFG_WDATA 0x70
> @@ -69,7 +69,7 @@
> #define A7_PERFVAL_BASE 0xC30
>
> /* Config interface control bits */
> -#define SYSCFG_START (1 << 31)
> +#define SYSCFG_START BIT(31)
> #define SYSCFG_SCC (6 << 20)
> #define SYSCFG_STAT (14 << 20)
>
> @@ -90,8 +90,8 @@
> #define CA15_DVFS 0
> #define CA7_DVFS 1
> #define SPC_SYS_CFG 2
> -#define STAT_COMPLETE(type) ((1 << 0) << (type << 2))
> -#define STAT_ERR(type) ((1 << 1) << (type << 2))
> +#define STAT_COMPLETE(type) (BIT(0) << (type << 2))
> +#define STAT_ERR(type) (BIT(1) << (type << 2))
> #define RESPONSE_MASK(type) (STAT_COMPLETE(type) | STAT_ERR(type))
>
> struct ve_spc_opp {
> @@ -162,7 +162,7 @@ void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set)
> if (cluster >= MAX_CLUSTERS)
> return;
>
> - mask = 1 << cpu;
> + mask = BIT(cpu);
>
> if (!cluster_is_a15(cluster))
> mask <<= 4;
> --
> 2.11.0
>
>
--
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On Mon, Jun 24, 2019 at 08:51:04PM +0700, Phong Tran wrote:
> [arch/arm/net/bpf_jit_32.c:618]: (error) Shifting signed 32-bit value by
> 31 bits is undefined behaviour
>
> Signed-off-by: Phong Tran <[email protected]>
> ---
> arch/arm/net/bpf_jit_32.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
> index adff54c312bf..4e8ad26305ca 100644
> --- a/arch/arm/net/bpf_jit_32.c
> +++ b/arch/arm/net/bpf_jit_32.c
> @@ -612,7 +612,7 @@ static inline void emit_a32_mov_se_i64(const bool is64, const s8 dst[],
> const u32 val, struct jit_ctx *ctx) {
> u64 val64 = val;
>
> - if (is64 && (val & (1<<31)))
> + if (is64 && (val & (BIT(31))))
Extra parens are not necessary, please remove.
> val64 |= 0xffffffff00000000ULL;
> emit_a32_mov_i64(dst, val64, ctx);
> }
> --
> 2.11.0
>
>
--
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On Mon, Jun 24, 2019 at 08:50:50PM +0700, Phong Tran wrote:
> There are errors with cppcheck
>
> "Shifting signed 32-bit value by 31 bits is undefined behaviour errors"
>
> This is just a mirror changing.
"mirror" ?
Apart from that and the extra unnecessary parens (which ought to be
cleaned up) this looks fine to me.
When there's too many parens next to each other, it makes reading
the expression more difficult - and that is definitely bad, so please
avoid unecessary parens where possible.
Thanks.
>
> V2: Using BIT() macro instead of (1UL << nr)
>
> Phong Tran (15):
> arm: perf: cleanup cppcheck shifting error
> ARM: davinci: cleanup cppcheck shifting errors
> ARM: ep93xx: cleanup cppcheck shifting errors
> ARM: exynos: cleanup cppcheck shifting error
> ARM: footbridge: cleanup cppcheck shifting error
> ARM: imx: cleanup cppcheck shifting errors
> ARM: ks8695: cleanup cppcheck shifting error
> ARM: mmp: cleanup cppcheck shifting errors
> ARM: omap2: cleanup cppcheck shifting error
> ARM: orion5x: cleanup cppcheck shifting errors
> ARM: pxa: cleanup cppcheck shifting errors
> ARM: vexpress: cleanup cppcheck shifting error
> ARM: mm: cleanup cppcheck shifting errors
> ARM: bpf: cleanup cppcheck shifting error
> ARM: vfp: cleanup cppcheck shifting errors
>
> arch/arm/kernel/perf_event_v7.c | 6 +-
> arch/arm/mach-davinci/ddr2.h | 6 +-
> arch/arm/mach-ep93xx/soc.h | 132 ++++++++++++++++++-------------------
> arch/arm/mach-exynos/suspend.c | 2 +-
> arch/arm/mach-footbridge/dc21285.c | 2 +-
> arch/arm/mach-imx/iomux-mx3.h | 64 +++++++++---------
> arch/arm/mach-ks8695/regs-pci.h | 4 +-
> arch/arm/mach-mmp/pm-mmp2.h | 40 +++++------
> arch/arm/mach-mmp/pm-pxa910.h | 76 ++++++++++-----------
> arch/arm/mach-omap2/powerdomain.c | 2 +-
> arch/arm/mach-orion5x/pci.c | 8 +--
> arch/arm/mach-pxa/irq.c | 4 +-
> arch/arm/mach-vexpress/spc.c | 12 ++--
> arch/arm/mm/fault.h | 6 +-
> arch/arm/net/bpf_jit_32.c | 2 +-
> arch/arm/vfp/vfpinstr.h | 8 +--
> 16 files changed, 187 insertions(+), 187 deletions(-)
>
> --
> 2.11.0
>
>
--
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
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On Mon, Jun 24, 2019 at 08:50:50PM +0700, Phong Tran wrote:
> There are errors with cppcheck
>
> "Shifting signed 32-bit value by 31 bits is undefined behaviour errors"
As I've already told you; your checker is bad. That is not in face
undefined behaviour in the kernel.
That's not to say you shouldn't clean up the code, but don't give broken
checkout output as a reason.
On Mon, Jun 24, 2019 at 05:27:43PM +0200, Peter Zijlstra wrote:
> On Mon, Jun 24, 2019 at 08:50:50PM +0700, Phong Tran wrote:
> > There are errors with cppcheck
> >
> > "Shifting signed 32-bit value by 31 bits is undefined behaviour errors"
>
> As I've already told you; your checker is bad. That is not in face
Bah, fact, typing hard.
> undefined behaviour in the kernel.
>
> That's not to say you shouldn't clean up the code, but don't give broken
> checkout output as a reason.
Hi!
On 24/06/2019 15:50, Phong Tran wrote:
> [arch/arm/mach-ep93xx/clock.c:102]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
> [arch/arm/mach-ep93xx/clock.c:132]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
> [arch/arm/mach-ep93xx/clock.c:140]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
> [arch/arm/mach-ep93xx/core.c:1001]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
> [arch/arm/mach-ep93xx/core.c:1002]: (error) Shifting signed 32-bit value
> by 31 bits is undefined behaviour
Acked-by: Alexander Sverdlin <[email protected]>
> Signed-off-by: Phong Tran <[email protected]>
> ---
> arch/arm/mach-ep93xx/soc.h | 132 ++++++++++++++++++++++-----------------------
> 1 file changed, 66 insertions(+), 66 deletions(-)
>
> diff --git a/arch/arm/mach-ep93xx/soc.h b/arch/arm/mach-ep93xx/soc.h
> index f2dace1c9154..250c82f8b0a1 100644
> --- a/arch/arm/mach-ep93xx/soc.h
> +++ b/arch/arm/mach-ep93xx/soc.h
> @@ -109,89 +109,89 @@
> #define EP93XX_SYSCON_REG(x) (EP93XX_SYSCON_BASE + (x))
> #define EP93XX_SYSCON_POWER_STATE EP93XX_SYSCON_REG(0x00)
> #define EP93XX_SYSCON_PWRCNT EP93XX_SYSCON_REG(0x04)
> -#define EP93XX_SYSCON_PWRCNT_FIR_EN (1<<31)
> -#define EP93XX_SYSCON_PWRCNT_UARTBAUD (1<<29)
> -#define EP93XX_SYSCON_PWRCNT_USH_EN (1<<28)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 (1<<27)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 (1<<26)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 (1<<25)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 (1<<24)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 (1<<23)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 (1<<22)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 (1<<21)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 (1<<20)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 (1<<19)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 (1<<18)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 (1<<17)
> -#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 (1<<16)
> +#define EP93XX_SYSCON_PWRCNT_FIR_EN BIT(31)
> +#define EP93XX_SYSCON_PWRCNT_UARTBAUD BIT(29)
> +#define EP93XX_SYSCON_PWRCNT_USH_EN BIT(28)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2M1 BIT(27)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2M0 BIT(26)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P8 BIT(25)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P9 BIT(24)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P6 BIT(23)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P7 BIT(22)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P4 BIT(21)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P5 BIT(20)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P2 BIT(19)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P3 BIT(18)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P0 BIT(17)
> +#define EP93XX_SYSCON_PWRCNT_DMA_M2P1 BIT(16)
> #define EP93XX_SYSCON_HALT EP93XX_SYSCON_REG(0x08)
> #define EP93XX_SYSCON_STANDBY EP93XX_SYSCON_REG(0x0c)
> #define EP93XX_SYSCON_CLKSET1 EP93XX_SYSCON_REG(0x20)
> -#define EP93XX_SYSCON_CLKSET1_NBYP1 (1<<23)
> +#define EP93XX_SYSCON_CLKSET1_NBYP1 BIT(23)
> #define EP93XX_SYSCON_CLKSET2 EP93XX_SYSCON_REG(0x24)
> -#define EP93XX_SYSCON_CLKSET2_NBYP2 (1<<19)
> -#define EP93XX_SYSCON_CLKSET2_PLL2_EN (1<<18)
> +#define EP93XX_SYSCON_CLKSET2_NBYP2 BIT(19)
> +#define EP93XX_SYSCON_CLKSET2_PLL2_EN BIT(18)
> #define EP93XX_SYSCON_DEVCFG EP93XX_SYSCON_REG(0x80)
> -#define EP93XX_SYSCON_DEVCFG_SWRST (1<<31)
> -#define EP93XX_SYSCON_DEVCFG_D1ONG (1<<30)
> -#define EP93XX_SYSCON_DEVCFG_D0ONG (1<<29)
> -#define EP93XX_SYSCON_DEVCFG_IONU2 (1<<28)
> -#define EP93XX_SYSCON_DEVCFG_GONK (1<<27)
> -#define EP93XX_SYSCON_DEVCFG_TONG (1<<26)
> -#define EP93XX_SYSCON_DEVCFG_MONG (1<<25)
> -#define EP93XX_SYSCON_DEVCFG_U3EN (1<<24)
> -#define EP93XX_SYSCON_DEVCFG_CPENA (1<<23)
> -#define EP93XX_SYSCON_DEVCFG_A2ONG (1<<22)
> -#define EP93XX_SYSCON_DEVCFG_A1ONG (1<<21)
> -#define EP93XX_SYSCON_DEVCFG_U2EN (1<<20)
> -#define EP93XX_SYSCON_DEVCFG_EXVC (1<<19)
> -#define EP93XX_SYSCON_DEVCFG_U1EN (1<<18)
> -#define EP93XX_SYSCON_DEVCFG_TIN (1<<17)
> -#define EP93XX_SYSCON_DEVCFG_HC3IN (1<<15)
> -#define EP93XX_SYSCON_DEVCFG_HC3EN (1<<14)
> -#define EP93XX_SYSCON_DEVCFG_HC1IN (1<<13)
> -#define EP93XX_SYSCON_DEVCFG_HC1EN (1<<12)
> -#define EP93XX_SYSCON_DEVCFG_HONIDE (1<<11)
> -#define EP93XX_SYSCON_DEVCFG_GONIDE (1<<10)
> -#define EP93XX_SYSCON_DEVCFG_PONG (1<<9)
> -#define EP93XX_SYSCON_DEVCFG_EONIDE (1<<8)
> -#define EP93XX_SYSCON_DEVCFG_I2SONSSP (1<<7)
> -#define EP93XX_SYSCON_DEVCFG_I2SONAC97 (1<<6)
> -#define EP93XX_SYSCON_DEVCFG_RASONP3 (1<<4)
> -#define EP93XX_SYSCON_DEVCFG_RAS (1<<3)
> -#define EP93XX_SYSCON_DEVCFG_ADCPD (1<<2)
> -#define EP93XX_SYSCON_DEVCFG_KEYS (1<<1)
> -#define EP93XX_SYSCON_DEVCFG_SHENA (1<<0)
> +#define EP93XX_SYSCON_DEVCFG_SWRST BIT(31)
> +#define EP93XX_SYSCON_DEVCFG_D1ONG BIT(30)
> +#define EP93XX_SYSCON_DEVCFG_D0ONG BIT(29)
> +#define EP93XX_SYSCON_DEVCFG_IONU2 BIT(28)
> +#define EP93XX_SYSCON_DEVCFG_GONK BIT(27)
> +#define EP93XX_SYSCON_DEVCFG_TONG BIT(26)
> +#define EP93XX_SYSCON_DEVCFG_MONG BIT(25)
> +#define EP93XX_SYSCON_DEVCFG_U3EN BIT(24)
> +#define EP93XX_SYSCON_DEVCFG_CPENA BIT(23)
> +#define EP93XX_SYSCON_DEVCFG_A2ONG BIT(22)
> +#define EP93XX_SYSCON_DEVCFG_A1ONG BIT(21)
> +#define EP93XX_SYSCON_DEVCFG_U2EN BIT(20)
> +#define EP93XX_SYSCON_DEVCFG_EXVC BIT(19)
> +#define EP93XX_SYSCON_DEVCFG_U1EN BIT(18)
> +#define EP93XX_SYSCON_DEVCFG_TIN BIT(17)
> +#define EP93XX_SYSCON_DEVCFG_HC3IN BIT(15)
> +#define EP93XX_SYSCON_DEVCFG_HC3EN BIT(14)
> +#define EP93XX_SYSCON_DEVCFG_HC1IN BIT(13)
> +#define EP93XX_SYSCON_DEVCFG_HC1EN BIT(12)
> +#define EP93XX_SYSCON_DEVCFG_HONIDE BIT(11)
> +#define EP93XX_SYSCON_DEVCFG_GONIDE BIT(10)
> +#define EP93XX_SYSCON_DEVCFG_PONG BIT(9)
> +#define EP93XX_SYSCON_DEVCFG_EONIDE BIT(8)
> +#define EP93XX_SYSCON_DEVCFG_I2SONSSP BIT(7)
> +#define EP93XX_SYSCON_DEVCFG_I2SONAC97 BIT(6)
> +#define EP93XX_SYSCON_DEVCFG_RASONP3 BIT(4)
> +#define EP93XX_SYSCON_DEVCFG_RAS BIT(3)
> +#define EP93XX_SYSCON_DEVCFG_ADCPD BIT(2)
> +#define EP93XX_SYSCON_DEVCFG_KEYS BIT(1)
> +#define EP93XX_SYSCON_DEVCFG_SHENA BIT(0)
> #define EP93XX_SYSCON_VIDCLKDIV EP93XX_SYSCON_REG(0x84)
> -#define EP93XX_SYSCON_CLKDIV_ENABLE (1<<15)
> -#define EP93XX_SYSCON_CLKDIV_ESEL (1<<14)
> -#define EP93XX_SYSCON_CLKDIV_PSEL (1<<13)
> +#define EP93XX_SYSCON_CLKDIV_ENABLE BIT(15)
> +#define EP93XX_SYSCON_CLKDIV_ESEL BIT(14)
> +#define EP93XX_SYSCON_CLKDIV_PSEL BIT(13)
> #define EP93XX_SYSCON_CLKDIV_PDIV_SHIFT 8
> #define EP93XX_SYSCON_I2SCLKDIV EP93XX_SYSCON_REG(0x8c)
> -#define EP93XX_SYSCON_I2SCLKDIV_SENA (1<<31)
> -#define EP93XX_SYSCON_I2SCLKDIV_ORIDE (1<<29)
> -#define EP93XX_SYSCON_I2SCLKDIV_SPOL (1<<19)
> +#define EP93XX_SYSCON_I2SCLKDIV_SENA BIT(31)
> +#define EP93XX_SYSCON_I2SCLKDIV_ORIDE BIT(29)
> +#define EP93XX_SYSCON_I2SCLKDIV_SPOL BIT(19)
> #define EP93XX_I2SCLKDIV_SDIV (1 << 16)
> #define EP93XX_I2SCLKDIV_LRDIV32 (0 << 17)
> #define EP93XX_I2SCLKDIV_LRDIV64 (1 << 17)
> #define EP93XX_I2SCLKDIV_LRDIV128 (2 << 17)
> #define EP93XX_I2SCLKDIV_LRDIV_MASK (3 << 17)
> #define EP93XX_SYSCON_KEYTCHCLKDIV EP93XX_SYSCON_REG(0x90)
> -#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN (1<<31)
> -#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV (1<<16)
> -#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN (1<<15)
> -#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV (1<<0)
> +#define EP93XX_SYSCON_KEYTCHCLKDIV_TSEN BIT(31)
> +#define EP93XX_SYSCON_KEYTCHCLKDIV_ADIV BIT(16)
> +#define EP93XX_SYSCON_KEYTCHCLKDIV_KEN BIT(15)
> +#define EP93XX_SYSCON_KEYTCHCLKDIV_KDIV BIT(0)
> #define EP93XX_SYSCON_SYSCFG EP93XX_SYSCON_REG(0x9c)
> #define EP93XX_SYSCON_SYSCFG_REV_MASK (0xf0000000)
> #define EP93XX_SYSCON_SYSCFG_REV_SHIFT (28)
> -#define EP93XX_SYSCON_SYSCFG_SBOOT (1<<8)
> -#define EP93XX_SYSCON_SYSCFG_LCSN7 (1<<7)
> -#define EP93XX_SYSCON_SYSCFG_LCSN6 (1<<6)
> -#define EP93XX_SYSCON_SYSCFG_LASDO (1<<5)
> -#define EP93XX_SYSCON_SYSCFG_LEEDA (1<<4)
> -#define EP93XX_SYSCON_SYSCFG_LEECLK (1<<3)
> -#define EP93XX_SYSCON_SYSCFG_LCSN2 (1<<1)
> -#define EP93XX_SYSCON_SYSCFG_LCSN1 (1<<0)
> +#define EP93XX_SYSCON_SYSCFG_SBOOT BIT(8)
> +#define EP93XX_SYSCON_SYSCFG_LCSN7 BIT(7)
> +#define EP93XX_SYSCON_SYSCFG_LCSN6 BIT(6)
> +#define EP93XX_SYSCON_SYSCFG_LASDO BIT(5)
> +#define EP93XX_SYSCON_SYSCFG_LEEDA BIT(4)
> +#define EP93XX_SYSCON_SYSCFG_LEECLK BIT(3)
> +#define EP93XX_SYSCON_SYSCFG_LCSN2 BIT(1)
> +#define EP93XX_SYSCON_SYSCFG_LCSN1 BIT(0)
> #define EP93XX_SYSCON_SWLOCK EP93XX_SYSCON_REG(0xc0)
>
> /* EP93xx System Controller software locked register write */
This is also do as the suggestion of "Linux Kernel Mentorship Task List"
https://wiki.linuxfoundation.org/lkmp/lkmp_task_list#cleanup_cppcheck_errors
"Shifting signed 32-bit value by 31 bits is undefined behaviour errors"
Change Log:
V2: Using BIT() macro instead of (1UL << nr)
V3:
* Update the comments from Russell King.
* Update commit message and cover letter for clearly the reason as request
Peter Zijlstra
* For avoiding the broken only change (1<<nr) pattern to BIT(nr)
Phong Tran (15):
arm: perf: cleanup cppcheck shifting error
ARM: davinci: cleanup cppcheck shifting errors
ARM: ep93xx: cleanup cppcheck shifting errors
ARM: exynos: cleanup cppcheck shifting error
ARM: footbridge: cleanup cppcheck shifting error
ARM: imx: cleanup cppcheck shifting errors
ARM: ks8695: cleanup cppcheck shifting error
ARM: mmp: cleanup cppcheck shifting errors
ARM: omap2: cleanup cppcheck shifting error
ARM: orion5x: cleanup cppcheck shifting errors
ARM: pxa: cleanup cppcheck shifting errors
ARM: vexpress: cleanup cppcheck shifting error
ARM: mm: cleanup cppcheck shifting errors
ARM: bpf: cleanup cppcheck shifting error
ARM: vfp: cleanup cppcheck shifting errors
arch/arm/kernel/perf_event_v7.c | 6 +-
arch/arm/mach-davinci/ddr2.h | 6 +-
arch/arm/mach-ep93xx/soc.h | 134 ++++++++++++++++++-------------------
arch/arm/mach-exynos/suspend.c | 2 +-
arch/arm/mach-footbridge/dc21285.c | 2 +-
arch/arm/mach-imx/iomux-mx3.h | 64 +++++++++---------
arch/arm/mach-ks8695/regs-pci.h | 4 +-
arch/arm/mach-mmp/pm-mmp2.h | 40 +++++------
arch/arm/mach-mmp/pm-pxa910.h | 74 ++++++++++----------
arch/arm/mach-omap2/powerdomain.c | 2 +-
arch/arm/mach-orion5x/pci.c | 8 +--
arch/arm/mach-pxa/irq.c | 4 +-
arch/arm/mach-vexpress/spc.c | 4 +-
arch/arm/mm/fault.h | 6 +-
arch/arm/net/bpf_jit_32.c | 2 +-
arch/arm/vfp/vfpinstr.h | 8 +--
16 files changed, 183 insertions(+), 183 deletions(-)
--
2.11.0
There is error from cppcheck tool
"Shifting signed 32-bit value by 31 bits is undefined behaviour errors"
change to use BIT() marco for improvement.
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/kernel/perf_event_v7.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index a4fb0f8b8f84..2924d7910b10 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -697,9 +697,9 @@ static struct attribute_group armv7_pmuv2_events_attr_group = {
/*
* Event filters for PMUv2
*/
-#define ARMV7_EXCLUDE_PL1 (1 << 31)
-#define ARMV7_EXCLUDE_USER (1 << 30)
-#define ARMV7_INCLUDE_HYP (1 << 27)
+#define ARMV7_EXCLUDE_PL1 BIT(31)
+#define ARMV7_EXCLUDE_USER BIT(30)
+#define ARMV7_INCLUDE_HYP BIT(27)
/*
* Secure debug enable reg
--
2.11.0
There is error from cppcheck tool
"Shifting signed 32-bit value by 31 bits is undefined behaviour errors"
change to use BIT() marco for improvement.
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-exynos/suspend.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-exynos/suspend.c b/arch/arm/mach-exynos/suspend.c
index be122af0de8f..983d5f1d0c29 100644
--- a/arch/arm/mach-exynos/suspend.c
+++ b/arch/arm/mach-exynos/suspend.c
@@ -285,7 +285,7 @@ static void exynos_pm_set_wakeup_mask(void)
* Set wake-up mask registers
* EXYNOS_EINT_WAKEUP_MASK is set by pinctrl driver in late suspend.
*/
- pmu_raw_writel(exynos_irqwake_intmask & ~(1 << 31), S5P_WAKEUP_MASK);
+ pmu_raw_writel(exynos_irqwake_intmask & ~BIT(31), S5P_WAKEUP_MASK);
}
static void exynos_pm_enter_sleep_mode(void)
--
2.11.0
There is error from cppcheck tool
"Shifting signed 32-bit value by 31 bits is undefined behaviour errors"
change to use BIT() marco for improvement.
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-footbridge/dc21285.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-footbridge/dc21285.c b/arch/arm/mach-footbridge/dc21285.c
index 8b81a17f675d..edea41e0256f 100644
--- a/arch/arm/mach-footbridge/dc21285.c
+++ b/arch/arm/mach-footbridge/dc21285.c
@@ -230,7 +230,7 @@ static irqreturn_t dc21285_parity_irq(int irq, void *dev_id)
printk("\n");
cmd = *CSR_PCICMD & 0xffff;
- *CSR_PCICMD = cmd | 1 << 31;
+ *CSR_PCICMD = cmd | BIT(31);
/*
* back off this interrupt
--
2.11.0
There is error from cppcheck tool
"Shifting signed 32-bit value by 31 bits is undefined behaviour errors"
change to use BIT() marco for improvement.
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-ks8695/regs-pci.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-ks8695/regs-pci.h b/arch/arm/mach-ks8695/regs-pci.h
index 75a9db6edbd9..7d28a83bb574 100644
--- a/arch/arm/mach-ks8695/regs-pci.h
+++ b/arch/arm/mach-ks8695/regs-pci.h
@@ -45,9 +45,9 @@
-#define CFRV_GUEST (1 << 23)
+#define CFRV_GUEST BIT(23)
#define PBCA_TYPE1 (1)
-#define PBCA_ENABLE (1 << 31)
+#define PBCA_ENABLE BIT(31)
--
2.11.0
There is error from cppcheck tool
"Shifting signed 32-bit value by 31 bits is undefined behaviour errors"
change to use BIT() marco for improvement.
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-imx/iomux-mx3.h | 64 +++++++++++++++++++++----------------------
1 file changed, 32 insertions(+), 32 deletions(-)
diff --git a/arch/arm/mach-imx/iomux-mx3.h b/arch/arm/mach-imx/iomux-mx3.h
index 99270a183d47..028b683866c3 100644
--- a/arch/arm/mach-imx/iomux-mx3.h
+++ b/arch/arm/mach-imx/iomux-mx3.h
@@ -59,38 +59,38 @@ enum iomux_pad_config {
* various IOMUX general purpose functions
*/
enum iomux_gp_func {
- MUX_PGP_FIRI = 1 << 0,
- MUX_DDR_MODE = 1 << 1,
- MUX_PGP_CSPI_BB = 1 << 2,
- MUX_PGP_ATA_1 = 1 << 3,
- MUX_PGP_ATA_2 = 1 << 4,
- MUX_PGP_ATA_3 = 1 << 5,
- MUX_PGP_ATA_4 = 1 << 6,
- MUX_PGP_ATA_5 = 1 << 7,
- MUX_PGP_ATA_6 = 1 << 8,
- MUX_PGP_ATA_7 = 1 << 9,
- MUX_PGP_ATA_8 = 1 << 10,
- MUX_PGP_UH2 = 1 << 11,
- MUX_SDCTL_CSD0_SEL = 1 << 12,
- MUX_SDCTL_CSD1_SEL = 1 << 13,
- MUX_CSPI1_UART3 = 1 << 14,
- MUX_EXTDMAREQ2_MBX_SEL = 1 << 15,
- MUX_TAMPER_DETECT_EN = 1 << 16,
- MUX_PGP_USB_4WIRE = 1 << 17,
- MUX_PGP_USB_COMMON = 1 << 18,
- MUX_SDHC_MEMSTICK1 = 1 << 19,
- MUX_SDHC_MEMSTICK2 = 1 << 20,
- MUX_PGP_SPLL_BYP = 1 << 21,
- MUX_PGP_UPLL_BYP = 1 << 22,
- MUX_PGP_MSHC1_CLK_SEL = 1 << 23,
- MUX_PGP_MSHC2_CLK_SEL = 1 << 24,
- MUX_CSPI3_UART5_SEL = 1 << 25,
- MUX_PGP_ATA_9 = 1 << 26,
- MUX_PGP_USB_SUSPEND = 1 << 27,
- MUX_PGP_USB_OTG_LOOPBACK = 1 << 28,
- MUX_PGP_USB_HS1_LOOPBACK = 1 << 29,
- MUX_PGP_USB_HS2_LOOPBACK = 1 << 30,
- MUX_CLKO_DDR_MODE = 1 << 31,
+ MUX_PGP_FIRI = BIT(0),
+ MUX_DDR_MODE = BIT(1),
+ MUX_PGP_CSPI_BB = BIT(2),
+ MUX_PGP_ATA_1 = BIT(3),
+ MUX_PGP_ATA_2 = BIT(4),
+ MUX_PGP_ATA_3 = BIT(5),
+ MUX_PGP_ATA_4 = BIT(6),
+ MUX_PGP_ATA_5 = BIT(7),
+ MUX_PGP_ATA_6 = BIT(8),
+ MUX_PGP_ATA_7 = BIT(9),
+ MUX_PGP_ATA_8 = BIT(10),
+ MUX_PGP_UH2 = BIT(11),
+ MUX_SDCTL_CSD0_SEL = BIT(12),
+ MUX_SDCTL_CSD1_SEL = BIT(13),
+ MUX_CSPI1_UART3 = BIT(14),
+ MUX_EXTDMAREQ2_MBX_SEL = BIT(15),
+ MUX_TAMPER_DETECT_EN = BIT(16),
+ MUX_PGP_USB_4WIRE = BIT(17),
+ MUX_PGP_USB_COMMON = BIT(18),
+ MUX_SDHC_MEMSTICK1 = BIT(19),
+ MUX_SDHC_MEMSTICK2 = BIT(20),
+ MUX_PGP_SPLL_BYP = BIT(21),
+ MUX_PGP_UPLL_BYP = BIT(22),
+ MUX_PGP_MSHC1_CLK_SEL = BIT(23),
+ MUX_PGP_MSHC2_CLK_SEL = BIT(24),
+ MUX_CSPI3_UART5_SEL = BIT(25),
+ MUX_PGP_ATA_9 = BIT(26),
+ MUX_PGP_USB_SUSPEND = BIT(27),
+ MUX_PGP_USB_OTG_LOOPBACK = BIT(28),
+ MUX_PGP_USB_HS1_LOOPBACK = BIT(29),
+ MUX_PGP_USB_HS2_LOOPBACK = BIT(30),
+ MUX_CLKO_DDR_MODE = BIT(31),
};
/*
--
2.11.0
There is error from cppcheck tool
"Shifting signed 32-bit value by 31 bits is undefined behaviour errors"
change to use BIT() marco for improvement.
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-mmp/pm-mmp2.h | 40 +++++++++++------------
arch/arm/mach-mmp/pm-pxa910.h | 74 +++++++++++++++++++++----------------------
2 files changed, 57 insertions(+), 57 deletions(-)
diff --git a/arch/arm/mach-mmp/pm-mmp2.h b/arch/arm/mach-mmp/pm-mmp2.h
index 70299a9450d3..8b1d91543676 100644
--- a/arch/arm/mach-mmp/pm-mmp2.h
+++ b/arch/arm/mach-mmp/pm-mmp2.h
@@ -12,37 +12,37 @@
#include "addr-map.h"
#define APMU_PJ_IDLE_CFG APMU_REG(0x018)
-#define APMU_PJ_IDLE_CFG_PJ_IDLE (1 << 1)
-#define APMU_PJ_IDLE_CFG_PJ_PWRDWN (1 << 5)
+#define APMU_PJ_IDLE_CFG_PJ_IDLE BIT(1)
+#define APMU_PJ_IDLE_CFG_PJ_PWRDWN BIT(5)
#define APMU_PJ_IDLE_CFG_PWR_SW(x) ((x) << 16)
-#define APMU_PJ_IDLE_CFG_L2_PWR_SW (1 << 19)
+#define APMU_PJ_IDLE_CFG_L2_PWR_SW BIT(19)
#define APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK (3 << 28)
#define APMU_SRAM_PWR_DWN APMU_REG(0x08c)
#define MPMU_SCCR MPMU_REG(0x038)
#define MPMU_PCR_PJ MPMU_REG(0x1000)
-#define MPMU_PCR_PJ_AXISD (1 << 31)
-#define MPMU_PCR_PJ_SLPEN (1 << 29)
-#define MPMU_PCR_PJ_SPSD (1 << 28)
-#define MPMU_PCR_PJ_DDRCORSD (1 << 27)
-#define MPMU_PCR_PJ_APBSD (1 << 26)
-#define MPMU_PCR_PJ_INTCLR (1 << 24)
-#define MPMU_PCR_PJ_SLPWP0 (1 << 23)
-#define MPMU_PCR_PJ_SLPWP1 (1 << 22)
-#define MPMU_PCR_PJ_SLPWP2 (1 << 21)
-#define MPMU_PCR_PJ_SLPWP3 (1 << 20)
-#define MPMU_PCR_PJ_VCTCXOSD (1 << 19)
-#define MPMU_PCR_PJ_SLPWP4 (1 << 18)
-#define MPMU_PCR_PJ_SLPWP5 (1 << 17)
-#define MPMU_PCR_PJ_SLPWP6 (1 << 16)
-#define MPMU_PCR_PJ_SLPWP7 (1 << 15)
+#define MPMU_PCR_PJ_AXISD BIT(31)
+#define MPMU_PCR_PJ_SLPEN BIT(29)
+#define MPMU_PCR_PJ_SPSD BIT(28)
+#define MPMU_PCR_PJ_DDRCORSD BIT(27)
+#define MPMU_PCR_PJ_APBSD BIT(26)
+#define MPMU_PCR_PJ_INTCLR BIT(24)
+#define MPMU_PCR_PJ_SLPWP0 BIT(23)
+#define MPMU_PCR_PJ_SLPWP1 BIT(22)
+#define MPMU_PCR_PJ_SLPWP2 BIT(21)
+#define MPMU_PCR_PJ_SLPWP3 BIT(20)
+#define MPMU_PCR_PJ_VCTCXOSD BIT(19)
+#define MPMU_PCR_PJ_SLPWP4 BIT(18)
+#define MPMU_PCR_PJ_SLPWP5 BIT(17)
+#define MPMU_PCR_PJ_SLPWP6 BIT(16)
+#define MPMU_PCR_PJ_SLPWP7 BIT(15)
#define MPMU_PLL2_CTRL1 MPMU_REG(0x0414)
#define MPMU_CGR_PJ MPMU_REG(0x1024)
#define MPMU_WUCRM_PJ MPMU_REG(0x104c)
-#define MPMU_WUCRM_PJ_WAKEUP(x) (1 << (x))
-#define MPMU_WUCRM_PJ_RTC_ALARM (1 << 17)
+#define MPMU_WUCRM_PJ_WAKEUP(x) BIT(x)
+#define MPMU_WUCRM_PJ_RTC_ALARM BIT(17)
enum {
POWER_MODE_ACTIVE = 0,
diff --git a/arch/arm/mach-mmp/pm-pxa910.h b/arch/arm/mach-mmp/pm-pxa910.h
index 8e6344adaf51..fc2f9c4b9d94 100644
--- a/arch/arm/mach-mmp/pm-pxa910.h
+++ b/arch/arm/mach-mmp/pm-pxa910.h
@@ -10,53 +10,53 @@
#define __PXA910_PM_H__
#define APMU_MOH_IDLE_CFG APMU_REG(0x0018)
-#define APMU_MOH_IDLE_CFG_MOH_IDLE (1 << 1)
-#define APMU_MOH_IDLE_CFG_MOH_PWRDWN (1 << 5)
-#define APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN (1 << 6)
+#define APMU_MOH_IDLE_CFG_MOH_IDLE BIT(1)
+#define APMU_MOH_IDLE_CFG_MOH_PWRDWN BIT(5)
+#define APMU_MOH_IDLE_CFG_MOH_SRAM_PWRDWN BIT(6)
#define APMU_MOH_IDLE_CFG_MOH_PWR_SW(x) (((x) & 0x3) << 16)
#define APMU_MOH_IDLE_CFG_MOH_L2_PWR_SW(x) (((x) & 0x3) << 18)
-#define APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ (1 << 21)
-#define APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN (1 << 20)
+#define APMU_MOH_IDLE_CFG_MOH_DIS_MC_SW_REQ BIT(21)
+#define APMU_MOH_IDLE_CFG_MOH_MC_WAKE_EN BIT(20)
#define APMU_SQU_CLK_GATE_CTRL APMU_REG(0x001c)
#define APMU_MC_HW_SLP_TYPE APMU_REG(0x00b0)
#define MPMU_FCCR MPMU_REG(0x0008)
#define MPMU_APCR MPMU_REG(0x1000)
-#define MPMU_APCR_AXISD (1 << 31)
-#define MPMU_APCR_DSPSD (1 << 30)
-#define MPMU_APCR_SLPEN (1 << 29)
-#define MPMU_APCR_DTCMSD (1 << 28)
-#define MPMU_APCR_DDRCORSD (1 << 27)
-#define MPMU_APCR_APBSD (1 << 26)
-#define MPMU_APCR_BBSD (1 << 25)
-#define MPMU_APCR_SLPWP0 (1 << 23)
-#define MPMU_APCR_SLPWP1 (1 << 22)
-#define MPMU_APCR_SLPWP2 (1 << 21)
-#define MPMU_APCR_SLPWP3 (1 << 20)
-#define MPMU_APCR_VCTCXOSD (1 << 19)
-#define MPMU_APCR_SLPWP4 (1 << 18)
-#define MPMU_APCR_SLPWP5 (1 << 17)
-#define MPMU_APCR_SLPWP6 (1 << 16)
-#define MPMU_APCR_SLPWP7 (1 << 15)
-#define MPMU_APCR_MSASLPEN (1 << 14)
-#define MPMU_APCR_STBYEN (1 << 13)
+#define MPMU_APCR_AXISD BIT(31)
+#define MPMU_APCR_DSPSD BIT(30)
+#define MPMU_APCR_SLPEN BIT(29)
+#define MPMU_APCR_DTCMSD BIT(28)
+#define MPMU_APCR_DDRCORSD BIT(27)
+#define MPMU_APCR_APBSD BIT(26)
+#define MPMU_APCR_BBSD BIT(25)
+#define MPMU_APCR_SLPWP0 BIT(23)
+#define MPMU_APCR_SLPWP1 BIT(22)
+#define MPMU_APCR_SLPWP2 BIT(21)
+#define MPMU_APCR_SLPWP3 BIT(20)
+#define MPMU_APCR_VCTCXOSD BIT(19)
+#define MPMU_APCR_SLPWP4 BIT(18)
+#define MPMU_APCR_SLPWP5 BIT(17)
+#define MPMU_APCR_SLPWP6 BIT(16)
+#define MPMU_APCR_SLPWP7 BIT(15)
+#define MPMU_APCR_MSASLPEN BIT(14)
+#define MPMU_APCR_STBYEN BIT(13)
#define MPMU_AWUCRM MPMU_REG(0x104c)
-#define MPMU_AWUCRM_AP_ASYNC_INT (1 << 25)
-#define MPMU_AWUCRM_AP_FULL_IDLE (1 << 24)
-#define MPMU_AWUCRM_SDH1 (1 << 23)
-#define MPMU_AWUCRM_SDH2 (1 << 22)
-#define MPMU_AWUCRM_KEYPRESS (1 << 21)
-#define MPMU_AWUCRM_TRACKBALL (1 << 20)
-#define MPMU_AWUCRM_NEWROTARY (1 << 19)
-#define MPMU_AWUCRM_RTC_ALARM (1 << 17)
-#define MPMU_AWUCRM_AP2_TIMER_3 (1 << 13)
-#define MPMU_AWUCRM_AP2_TIMER_2 (1 << 12)
-#define MPMU_AWUCRM_AP2_TIMER_1 (1 << 11)
-#define MPMU_AWUCRM_AP1_TIMER_3 (1 << 10)
-#define MPMU_AWUCRM_AP1_TIMER_2 (1 << 9)
-#define MPMU_AWUCRM_AP1_TIMER_1 (1 << 8)
+#define MPMU_AWUCRM_AP_ASYNC_INT BIT(25)
+#define MPMU_AWUCRM_AP_FULL_IDLE BIT(24)
+#define MPMU_AWUCRM_SDH1 BIT(23)
+#define MPMU_AWUCRM_SDH2 BIT(22)
+#define MPMU_AWUCRM_KEYPRESS BIT(21)
+#define MPMU_AWUCRM_TRACKBALL BIT(20)
+#define MPMU_AWUCRM_NEWROTARY BIT(19)
+#define MPMU_AWUCRM_RTC_ALARM BIT(17)
+#define MPMU_AWUCRM_AP2_TIMER_3 BIT(13)
+#define MPMU_AWUCRM_AP2_TIMER_2 BIT(12)
+#define MPMU_AWUCRM_AP2_TIMER_1 BIT(11)
+#define MPMU_AWUCRM_AP1_TIMER_3 BIT(10)
+#define MPMU_AWUCRM_AP1_TIMER_2 BIT(9)
+#define MPMU_AWUCRM_AP1_TIMER_1 BIT(8)
#define MPMU_AWUCRM_WAKEUP(x) (1 << ((x) & 0x7))
enum {
--
2.11.0
There is error from cppcheck tool
"Shifting signed 32-bit value by 31 bits is undefined behaviour errors"
change to use BIT() marco for improvement.
Signed-off-by: Phong Tran <[email protected]>
Reviewed-by: Andrew Lunn <[email protected]>
---
arch/arm/mach-orion5x/pci.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 76951bfbacf5..f47668530d5e 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -200,13 +200,13 @@ static int __init pcie_setup(struct pci_sys_data *sys)
/*
* PCI_MODE bits
*/
-#define PCI_MODE_64BIT (1 << 2)
-#define PCI_MODE_PCIX ((1 << 4) | (1 << 5))
+#define PCI_MODE_64BIT BIT(2)
+#define PCI_MODE_PCIX (BIT(4) | BIT(5))
/*
* PCI_CMD bits
*/
-#define PCI_CMD_HOST_REORDER (1 << 29)
+#define PCI_CMD_HOST_REORDER BIT(29)
/*
* PCI_P2P_CONF bits
@@ -223,7 +223,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
#define PCI_CONF_FUNC(func) (((func) & 0x3) << 8)
#define PCI_CONF_DEV(dev) (((dev) & 0x1f) << 11)
#define PCI_CONF_BUS(bus) (((bus) & 0xff) << 16)
-#define PCI_CONF_ADDR_EN (1 << 31)
+#define PCI_CONF_ADDR_EN BIT(31)
/*
* Internal configuration space
--
2.11.0
There is error from cppcheck tool
"Shifting signed 32-bit value by 31 bits is undefined behaviour errors"
change to use BIT() marco for improvement.
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-omap2/powerdomain.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/powerdomain.c b/arch/arm/mach-omap2/powerdomain.c
index 1cbac76136d4..886961726380 100644
--- a/arch/arm/mach-omap2/powerdomain.c
+++ b/arch/arm/mach-omap2/powerdomain.c
@@ -35,7 +35,7 @@
#include "soc.h"
#include "pm.h"
-#define PWRDM_TRACE_STATES_FLAG (1<<31)
+#define PWRDM_TRACE_STATES_FLAG BIT(31)
void pwrdms_save_context(void);
void pwrdms_restore_context(void);
--
2.11.0
There is error from cppcheck tool
"Shifting signed 32-bit value by 31 bits is undefined behaviour errors"
change to use BIT() marco for improvement.
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-pxa/irq.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-pxa/irq.c b/arch/arm/mach-pxa/irq.c
index 74efc3ab595f..cbbb5cfecb60 100644
--- a/arch/arm/mach-pxa/irq.c
+++ b/arch/arm/mach-pxa/irq.c
@@ -35,9 +35,9 @@
#define IPR(i) (((i) < 32) ? (0x01c + ((i) << 2)) : \
((i) < 64) ? (0x0b0 + (((i) - 32) << 2)) : \
(0x144 + (((i) - 64) << 2)))
-#define ICHP_VAL_IRQ (1 << 31)
+#define ICHP_VAL_IRQ BIT(31)
#define ICHP_IRQ(i) (((i) >> 16) & 0x7fff)
-#define IPR_VALID (1 << 31)
+#define IPR_VALID BIT(31)
#define MAX_INTERNAL_IRQS 128
--
2.11.0
There is error from cppcheck tool
"Shifting signed 32-bit value by 31 bits is undefined behaviour errors"
change to use BIT() marco for improvement.
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mach-vexpress/spc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-vexpress/spc.c b/arch/arm/mach-vexpress/spc.c
index 0f5381d13494..354e0e7025ae 100644
--- a/arch/arm/mach-vexpress/spc.c
+++ b/arch/arm/mach-vexpress/spc.c
@@ -69,7 +69,7 @@
#define A7_PERFVAL_BASE 0xC30
/* Config interface control bits */
-#define SYSCFG_START (1 << 31)
+#define SYSCFG_START BIT(31)
#define SYSCFG_SCC (6 << 20)
#define SYSCFG_STAT (14 << 20)
@@ -162,7 +162,7 @@ void ve_spc_cpu_wakeup_irq(u32 cluster, u32 cpu, bool set)
if (cluster >= MAX_CLUSTERS)
return;
- mask = 1 << cpu;
+ mask = BIT(cpu);
if (!cluster_is_a15(cluster))
mask <<= 4;
--
2.11.0
There is error from cppcheck tool
"Shifting signed 32-bit value by 31 bits is undefined behaviour errors"
change to use BIT() marco for improvement.
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/mm/fault.h | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/mm/fault.h b/arch/arm/mm/fault.h
index c063708fa503..8a706cb7f21d 100644
--- a/arch/arm/mm/fault.h
+++ b/arch/arm/mm/fault.h
@@ -5,9 +5,9 @@
/*
* Fault status register encodings. We steal bit 31 for our own purposes.
*/
-#define FSR_LNX_PF (1 << 31)
-#define FSR_WRITE (1 << 11)
-#define FSR_FS4 (1 << 10)
+#define FSR_LNX_PF BIT(31)
+#define FSR_WRITE BIT(11)
+#define FSR_FS4 BIT(10)
#define FSR_FS3_0 (15)
#define FSR_FS5_0 (0x3f)
--
2.11.0
There is error from cppcheck tool
"Shifting signed 32-bit value by 31 bits is undefined behaviour errors"
change to use BIT() marco for improvement.
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/net/bpf_jit_32.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/net/bpf_jit_32.c b/arch/arm/net/bpf_jit_32.c
index adff54c312bf..8904d16a8754 100644
--- a/arch/arm/net/bpf_jit_32.c
+++ b/arch/arm/net/bpf_jit_32.c
@@ -612,7 +612,7 @@ static inline void emit_a32_mov_se_i64(const bool is64, const s8 dst[],
const u32 val, struct jit_ctx *ctx) {
u64 val64 = val;
- if (is64 && (val & (1<<31)))
+ if (is64 && (val & BIT(31)))
val64 |= 0xffffffff00000000ULL;
emit_a32_mov_i64(dst, val64, ctx);
}
--
2.11.0
There is error from cppcheck tool
"Shifting signed 32-bit value by 31 bits is undefined behaviour errors"
change to use BIT() marco for improvement.
Signed-off-by: Phong Tran <[email protected]>
---
arch/arm/vfp/vfpinstr.h | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/vfp/vfpinstr.h b/arch/arm/vfp/vfpinstr.h
index 38dc154e39ff..8951637c58ff 100644
--- a/arch/arm/vfp/vfpinstr.h
+++ b/arch/arm/vfp/vfpinstr.h
@@ -57,10 +57,10 @@
#define vfp_single(inst) (((inst) & 0x0000f00) == 0xa00)
-#define FPSCR_N (1 << 31)
-#define FPSCR_Z (1 << 30)
-#define FPSCR_C (1 << 29)
-#define FPSCR_V (1 << 28)
+#define FPSCR_N BIT(31)
+#define FPSCR_Z BIT(30)
+#define FPSCR_C BIT(29)
+#define FPSCR_V BIT(28)
/*
* Since we aren't building with -mfpu=vfp, we need to code
--
2.11.0
On Tue, Jun 25, 2019 at 11:03:42AM +0700, Phong Tran wrote:
> There is error from cppcheck tool
> "Shifting signed 32-bit value by 31 bits is undefined behaviour errors"
> change to use BIT() marco for improvement.
s/marco/macro/
As Peter pointed out, this "error" is also a false positive also for the
kernel.
> Signed-off-by: Phong Tran <[email protected]>
> ---
> arch/arm/kernel/perf_event_v7.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
> index a4fb0f8b8f84..2924d7910b10 100644
> --- a/arch/arm/kernel/perf_event_v7.c
> +++ b/arch/arm/kernel/perf_event_v7.c
> @@ -697,9 +697,9 @@ static struct attribute_group armv7_pmuv2_events_attr_group = {
> /*
> * Event filters for PMUv2
> */
> -#define ARMV7_EXCLUDE_PL1 (1 << 31)
> -#define ARMV7_EXCLUDE_USER (1 << 30)
> -#define ARMV7_INCLUDE_HYP (1 << 27)
> +#define ARMV7_EXCLUDE_PL1 BIT(31)
> +#define ARMV7_EXCLUDE_USER BIT(30)
> +#define ARMV7_INCLUDE_HYP BIT(27)
Acked-by: Will Deacon <[email protected]>
You can drop this into Russell's patch system[1].
Will
[1] https://www.arm.linux.org.uk/developer/patches/
On Tue, Jun 25, 2019 at 11:03:53AM +0700, Phong Tran wrote:
> There is error from cppcheck tool
> "Shifting signed 32-bit value by 31 bits is undefined behaviour errors"
> change to use BIT() marco for improvement.
>
What's your plan for merging this series ? I can take this for v5.4
If not,
Acked-by: Sudeep Holla <[email protected]>
--
Regards,
Sudeep
On Tue, Jun 25, 2019 at 11:03:45AM +0700, Phong Tran wrote:
> There is error from cppcheck tool
> "Shifting signed 32-bit value by 31 bits is undefined behaviour errors"
> change to use BIT() marco for improvement.
>
> Signed-off-by: Phong Tran <[email protected]>
> ---
> arch/arm/mach-exynos/suspend.c | 2 +-
Thanks, applied with slightly different commit message. As Peter
pointed, there is no error because of GCC. Usually we expect a reply to
comments on LKML... and also you could take his hints and use them to
improve the commit msg to properly describe what is the problem.
Best regards,
Krzysztof