by Maxime Ripard

On Sat, Jul 13, 2019 at 11:46:31AM +0800, Icenowy Zheng wrote:
> + [CLK_MMC1] = &mmc1_clk.common.hw,
> + [CLK_MMC1_SAMPLE] = &mmc1_sample_clk.common.hw,
> + [CLK_MMC1_OUTPUT] = &mmc1_output_clk.common.hw,
> + [CLK_MMC2] = &mmc1_clk.common.hw,
> + [CLK_MMC2_SAMPLE] = &mmc1_sample_clk.common.hw,
> + [CLK_MMC2_OUTPUT] = &mmc1_output_clk.common.hw,

And there's the same mistake here.

Maxime

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2019-07-20 18:41:34

by Icenowy Zheng

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Subject: Re: [PATCH v4 6/8] ARM: sunxi: dts: s3/s3l/v3: add DTSI files for S3/S3L/V3 SoCs

于 2019年7月20日 GMT+08:00 下午5:48:14, Maxime Ripard <[email protected]> 写到:
>On Sat, Jul 13, 2019 at 11:46:32AM +0800, Icenowy Zheng wrote:
>> The Allwinner S3/S3L/V3 SoCs all share the same die with the V3s SoC,
>> but with more GPIO wired out of the package.
>>
>> Add DTSI files for these SoCs. The DTSI file for V3 just replaces the
>> pinctrl compatible string, and the S3/S3L DTSI files just include the
>V3
>> DTSI file.
>>
>> Signed-off-by: Icenowy Zheng <[email protected]>
>> ---
>> No changes since v2.
>>
>> arch/arm/boot/dts/sun8i-s3.dtsi | 6 ++++++
>> arch/arm/boot/dts/sun8i-s3l.dtsi | 6 ++++++
>> arch/arm/boot/dts/sun8i-v3.dtsi | 14 ++++++++++++++
>> 3 files changed, 26 insertions(+)
>> create mode 100644 arch/arm/boot/dts/sun8i-s3.dtsi
>> create mode 100644 arch/arm/boot/dts/sun8i-s3l.dtsi
>> create mode 100644 arch/arm/boot/dts/sun8i-v3.dtsi
>>
>> diff --git a/arch/arm/boot/dts/sun8i-s3.dtsi
>b/arch/arm/boot/dts/sun8i-s3.dtsi
>> new file mode 100644
>> index 000000000000..0f41a25ecb30
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun8i-s3.dtsi
>> @@ -0,0 +1,6 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (C) 2019 Icenowy Zheng <[email protected]>
>> + */
>> +
>> +#include "sun8i-v3.dtsi"
>> diff --git a/arch/arm/boot/dts/sun8i-s3l.dtsi
>b/arch/arm/boot/dts/sun8i-s3l.dtsi
>> new file mode 100644
>> index 000000000000..0f41a25ecb30
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun8i-s3l.dtsi
>> @@ -0,0 +1,6 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (C) 2019 Icenowy Zheng <[email protected]>
>> + */
>> +
>> +#include "sun8i-v3.dtsi"
>> diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi
>b/arch/arm/boot/dts/sun8i-v3.dtsi
>> new file mode 100644
>> index 000000000000..6ae8645ade50
>> --- /dev/null
>> +++ b/arch/arm/boot/dts/sun8i-v3.dtsi
>> @@ -0,0 +1,14 @@
>> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
>> +/*
>> + * Copyright (C) 2019 Icenowy Zheng <[email protected]>
>> + */
>> +
>> +#include "sun8i-v3s.dtsi"
>> +
>> +&ccu {
>> + compatible = "allwinner,sun8i-v3-ccu";
>> +};
>> +
>> +&pio {
>> + compatible = "allwinner,sun8i-v3-pinctrl";
>> +};
>
>Is there any difference between the S3, S3L and V3?

DRAM. This might be useful when we introduce DRAM DVFS.

>
>If not, then we don't need all those DTSI, just add the v3

But I agree with this now.

>
>Maxime
>
>--
>Maxime Ripard, Bootlin
>Embedded Linux and Kernel engineering
>https://bootlin.com

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2019-07-20 18:41:44

by Maxime Ripard

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Subject: Re: [PATCH v4 7/8] dt-bindings: arm: sunxi: add binding for Lichee Zero Plus core board

On Sat, Jul 13, 2019 at 11:46:33AM +0800, Icenowy Zheng wrote:
> The Lichee Zero Plus is a core board made by Sipeed, with a microUSB
> connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI Flash.
> It has a gold finger connector for expansion, and UART is available from
> reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or
> Allwinner V3L SoCs.
>
> Add the device tree binding of the basic version of the core board --
> w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC.
>
> Signed-off-by: Icenowy Zheng <[email protected]>
> ---
> No changes since v3.
>
> Patch introduced in v2.
>
> Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml
> index 000a00d12d6a..48c126a7a848 100644
> --- a/Documentation/devicetree/bindings/arm/sunxi.yaml
> +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
> @@ -353,6 +353,11 @@ properties:
> - const: licheepi,licheepi-zero
> - const: allwinner,sun8i-v3s
>
> + - description: Lichee Zero Plus (with S3, without eMMC/SPI Flash)
> + items:
> + - const: sipeed,lichee-zero-plus
> + - const: allwinner,sun8i-s3

If the S3 is just a rebranded V3, then we should have the v3 compatile
in that list too.

Maxime

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2019-07-20 18:42:54

On Sat, Jul 13, 2019 at 11:46:32AM +0800, Icenowy Zheng wrote:
> The Allwinner S3/S3L/V3 SoCs all share the same die with the V3s SoC,
> but with more GPIO wired out of the package.
>
> Add DTSI files for these SoCs. The DTSI file for V3 just replaces the
> pinctrl compatible string, and the S3/S3L DTSI files just include the V3
> DTSI file.
>
> Signed-off-by: Icenowy Zheng <[email protected]>
> ---
> No changes since v2.
>
> arch/arm/boot/dts/sun8i-s3.dtsi | 6 ++++++
> arch/arm/boot/dts/sun8i-s3l.dtsi | 6 ++++++
> arch/arm/boot/dts/sun8i-v3.dtsi | 14 ++++++++++++++
> 3 files changed, 26 insertions(+)
> create mode 100644 arch/arm/boot/dts/sun8i-s3.dtsi
> create mode 100644 arch/arm/boot/dts/sun8i-s3l.dtsi
> create mode 100644 arch/arm/boot/dts/sun8i-v3.dtsi
>
> diff --git a/arch/arm/boot/dts/sun8i-s3.dtsi b/arch/arm/boot/dts/sun8i-s3.dtsi
> new file mode 100644
> index 000000000000..0f41a25ecb30
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-s3.dtsi
> @@ -0,0 +1,6 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Icenowy Zheng <[email protected]>
> + */
> +
> +#include "sun8i-v3.dtsi"
> diff --git a/arch/arm/boot/dts/sun8i-s3l.dtsi b/arch/arm/boot/dts/sun8i-s3l.dtsi
> new file mode 100644
> index 000000000000..0f41a25ecb30
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-s3l.dtsi
> @@ -0,0 +1,6 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Icenowy Zheng <[email protected]>
> + */
> +
> +#include "sun8i-v3.dtsi"
> diff --git a/arch/arm/boot/dts/sun8i-v3.dtsi b/arch/arm/boot/dts/sun8i-v3.dtsi
> new file mode 100644
> index 000000000000..6ae8645ade50
> --- /dev/null
> +++ b/arch/arm/boot/dts/sun8i-v3.dtsi
> @@ -0,0 +1,14 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (C) 2019 Icenowy Zheng <[email protected]>
> + */
> +
> +#include "sun8i-v3s.dtsi"
> +
> +&ccu {
> + compatible = "allwinner,sun8i-v3-ccu";
> +};
> +
> +&pio {
> + compatible = "allwinner,sun8i-v3-pinctrl";
> +};

Is there any difference between the S3, S3L and V3?

If not, then we don't need all those DTSI, just add the v3

Maxime

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2019-07-22 17:47:56

by Rob Herring (Arm)

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Subject: Re: [PATCH v4 5/8] clk: sunxi-ng: v3s: add Allwinner V3 support

On Sat, 13 Jul 2019 11:46:31 +0800, Icenowy Zheng wrote:
> Allwinner V3 has the same main die with V3s, but with more pins wired.
> There's a I2S bus on V3 that is not available on V3s.
>
> Add the V3-only peripheral's clocks and reset to the V3s CCU driver,
> bound to a new V3 compatible string. The driver name is not changed
> because it's part of the device tree binding (the header file name).
>
> Signed-off-by: Icenowy Zheng <[email protected]>
> ---
> Changes in v4:
> - Add the missing MMC2 clock slices.
>
> No changes in v3/v2.
>
> drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 228 +++++++++++++++++++++-
> drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 2 +-
> include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 +
> include/dt-bindings/reset/sun8i-v3s-ccu.h | 3 +
> 4 files changed, 234 insertions(+), 3 deletions(-)
>

Please add Acked-by/Reviewed-by tags when posting new versions. However,
there's no need to repost patches *only* to add the tags. The upstream
maintainer will do that for acks received on the version they apply.

If a tag was not added on purpose, please state why and what changed.

2019-07-23 02:39:28

On Wed, Jul 24, 2019 at 09:09:01PM +0800, Icenowy Zheng wrote:
> 在 2019-07-23 03:29，Maxime Ripard 写道：
> > On Sat, Jul 20, 2019 at 07:39:08PM +0800, Icenowy Zheng wrote:
> > >
> > >
> > > 于 2019年7月20日 GMT+08:00 下午6:13:18, Maxime Ripard
> > > <[email protected]> 写到:
> > > >On Sat, Jul 13, 2019 at 11:46:33AM +0800, Icenowy Zheng wrote:
> > > >> The Lichee Zero Plus is a core board made by Sipeed, with a microUSB
> > > >> connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI
> > > >Flash.
> > > >> It has a gold finger connector for expansion, and UART is available
> > > >from
> > > >> reserved pins w/ 2.54mm pitch. The board can use either SoChip S3 or
> > > >> Allwinner V3L SoCs.
> > > >>
> > > >> Add the device tree binding of the basic version of the core board --
> > > >> w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC.
> > > >>
> > > >> Signed-off-by: Icenowy Zheng <[email protected]>
> > > >> ---
> > > >> No changes since v3.
> > > >>
> > > >> Patch introduced in v2.
> > > >>
> > > >> Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++
> > > >> 1 file changed, 5 insertions(+)
> > > >>
> > > >> diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml
> > > >b/Documentation/devicetree/bindings/arm/sunxi.yaml
> > > >> index 000a00d12d6a..48c126a7a848 100644
> > > >> --- a/Documentation/devicetree/bindings/arm/sunxi.yaml
> > > >> +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml
> > > >> @@ -353,6 +353,11 @@ properties:
> > > >> - const: licheepi,licheepi-zero
> > > >> - const: allwinner,sun8i-v3s
> > > >>
> > > >> + - description: Lichee Zero Plus (with S3, without eMMC/SPI
> > > >Flash)
> > > >> + items:
> > > >> + - const: sipeed,lichee-zero-plus
> > > >> + - const: allwinner,sun8i-s3
> > > >
> > > >If the S3 is just a rebranded V3, then we should have the v3 compatile
> > > >in that list too.
> > >
> > > S3 is V3 with copackaged DDR3 DRAM.
> > >
> > > It's pin incompatible w/ V3.
> >
> > Does it matter though?
> >
> > If the only thing that changes is the package, we're not manipulating
> > that, and any software that deals with the v3 can deal with the
> > s3. Which is what the compatible is about.
>
> Okay. Should the S3 compatible be kept befoer the V3 one?

Yep, something like (in the DT)

compatible = "sipeed,lichee-zero-plus", "allwinner,sun8i-s3", "allwinner,sun8i-v3"

Maxime

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