i.MX8QXP boards feature an Hifi4 DSP from Tensilica. This patch series
adds the DT node.
Note that we switched to the new yaml format for bindings documentation.
The DSP will run SOF Firmware [1]. Patches adding support for Linux DSP
driver are already sent for review to SOF folks [2].
This patch series also contains a patch introducing DT related clocks.
The patch was already reviewed here:
https://lkml.org/lkml/2019/7/17/975
but I added it in this patch series because it wasn't yet picked by
Shawn so patches 2/3 will not compiled without patch 1.
[1] https://github.com/thesofproject/sof
[2] https://github.com/thesofproject/linux/pull/1048/commits
Daniel Baluta (3):
clk: imx8: Add DSP related clocks
arm64: dts: imx8qxp: Add DSP DT node
dt-bindings: dsp: fsl: Add DSP core binding support
.../devicetree/bindings/dsp/fsl,dsp.yaml | 87 +++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 4 +
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 32 +++++++
drivers/clk/imx/clk-imx8qxp-lpcg.c | 5 ++
include/dt-bindings/clock/imx8-clock.h | 6 +-
5 files changed, 133 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
--
2.17.1
This describes the DSP device tree node.
Signed-off-by: Daniel Baluta <[email protected]>
---
.../devicetree/bindings/dsp/fsl,dsp.yaml | 87 +++++++++++++++++++
1 file changed, 87 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
diff --git a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
new file mode 100644
index 000000000000..d112486eda0e
--- /dev/null
+++ b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
@@ -0,0 +1,87 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/freescale/fsl,dsp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8 DSP core
+
+maintainers:
+ - Daniel Baluta <[email protected]>
+
+description: |
+ Some boards from i.MX8 family contain a DSP core used for
+ advanced pre- and post- audio processing.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8qxp-dsp
+
+ reg:
+ description: Should contain register location and length
+
+ clocks:
+ items:
+ - description: ipg clock
+ - description: ocram clock
+ - description: core clock
+
+ clock-names:
+ items:
+ - const: ipg
+ - const: ocram
+ - const: core
+
+ power-domains:
+ description:
+ List of phandle and PM domain specifier as documented in
+ Documentation/devicetree/bindings/power/power_domain.txt
+
+ mboxes:
+ description:
+ List of <&phandle type channel> - 2 channels for TXDB, 2 channels for RXDB
+ (see mailbox/fsl,mu.txt)
+ maxItems: 4
+
+ mbox-names:
+ items:
+ - const: txdb0
+ - const: txdb1
+ - const: rxdb0
+ - const: rxdb1
+
+ memory-region:
+ description:
+ phandle to a node describing reserved memory (System RAM memory)
+ used by DSP (see bindings/reserved-memory/reserved-memory.txt)
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - power-domains
+ - mboxes
+ - mbox-names
+ - memory-region
+
+examples:
+ - |
+ #include <dt-bindings/firmware/imx/rsrc.h>
+ #include <dt-bindings/clock/imx8-clock.h>
+ dsp@596e8000 {
+ compatbile = "fsl,imx8qxp-dsp";
+ reg = <0x596e8000 0x88000>;
+ clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
+ <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
+ <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
+ clock-names = "ipg", "ocram", "core";
+ power-domains = <&pd IMX_SC_R_MU_13A>,
+ <&pd IMX_SC_R_MU_13B>,
+ <&pd IMX_SC_R_DSP>,
+ <&pd IMX_SC_R_DSP_RAM>;
+ mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1";
+ mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>;
+ };
--
2.17.1
i.MX8QXP contains Hifi4 DSP. There are four clocks
associated with DSP:
* dsp_lpcg_core_clk
* dsp_lpcg_ipg_clk
* dsp_lpcg_adb_aclk
* ocram_lpcg_ipg_clk
Signed-off-by: Daniel Baluta <[email protected]>
Reviewed-by: Dong Aisheng <[email protected]>
---
drivers/clk/imx/clk-imx8qxp-lpcg.c | 5 +++++
include/dt-bindings/clock/imx8-clock.h | 6 +++++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx8qxp-lpcg.c b/drivers/clk/imx/clk-imx8qxp-lpcg.c
index fb6edf1b8aa2..c0aff7ca6374 100644
--- a/drivers/clk/imx/clk-imx8qxp-lpcg.c
+++ b/drivers/clk/imx/clk-imx8qxp-lpcg.c
@@ -72,6 +72,11 @@ static const struct imx8qxp_lpcg_data imx8qxp_lpcg_adma[] = {
{ IMX_ADMA_LPCG_I2C2_CLK, "i2c2_lpcg_clk", "i2c2_clk", 0, ADMA_LPI2C_2_LPCG, 0, 0, },
{ IMX_ADMA_LPCG_I2C3_IPG_CLK, "i2c3_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_LPI2C_3_LPCG, 16, 0, },
{ IMX_ADMA_LPCG_I2C3_CLK, "i2c3_lpcg_clk", "i2c3_clk", 0, ADMA_LPI2C_3_LPCG, 0, 0, },
+
+ { IMX_ADMA_LPCG_DSP_CORE_CLK, "dsp_lpcg_core_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 28, 0, },
+ { IMX_ADMA_LPCG_DSP_IPG_CLK, "dsp_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 20, 0, },
+ { IMX_ADMA_LPCG_DSP_ADB_CLK, "dsp_lpcg_adb_clk", "dma_ipg_clk_root", 0, ADMA_HIFI_LPCG, 16, 0, },
+ { IMX_ADMA_LPCG_OCRAM_IPG_CLK, "ocram_lpcg_ipg_clk", "dma_ipg_clk_root", 0, ADMA_OCRAM_LPCG, 16, 0, },
};
static const struct imx8qxp_ss_lpcg imx8qxp_ss_adma = {
diff --git a/include/dt-bindings/clock/imx8-clock.h b/include/dt-bindings/clock/imx8-clock.h
index 4236818e3be5..673a8c662340 100644
--- a/include/dt-bindings/clock/imx8-clock.h
+++ b/include/dt-bindings/clock/imx8-clock.h
@@ -283,7 +283,11 @@
#define IMX_ADMA_LPCG_PWM_IPG_CLK 38
#define IMX_ADMA_LPCG_LCD_PIX_CLK 39
#define IMX_ADMA_LPCG_LCD_APB_CLK 40
+#define IMX_ADMA_LPCG_DSP_ADB_CLK 41
+#define IMX_ADMA_LPCG_DSP_IPG_CLK 42
+#define IMX_ADMA_LPCG_DSP_CORE_CLK 43
+#define IMX_ADMA_LPCG_OCRAM_IPG_CLK 44
-#define IMX_ADMA_LPCG_CLK_END 41
+#define IMX_ADMA_LPCG_CLK_END 45
#endif /* __DT_BINDINGS_CLOCK_IMX_H */
--
2.17.1
This includes DSP reserved memory, ADMA DSP device and DSP MU
communication channels description.
Signed-off-by: Daniel Baluta <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 4 +++
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 32 +++++++++++++++++++
2 files changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index bfdada2db176..19468058e6ae 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -230,3 +230,7 @@
>;
};
};
+
+&adma_dsp {
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
index 05fa0b7f36bb..6a4efb1f0fa2 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi
@@ -113,6 +113,17 @@
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ dsp_reserved: dsp@92400000 {
+ reg = <0 0x92400000 0 0x2000000>;
+ no-map;
+ };
+ };
+
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
@@ -204,6 +215,27 @@
#clock-cells = <1>;
};
+ adma_dsp: dsp@596e8000 {
+ compatible = "fsl,imx8qxp-dsp";
+ reg = <0x596e8000 0x88000>;
+ clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
+ <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
+ <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
+ clock-names = "ipg", "ocram", "core";
+ power-domains = <&pd IMX_SC_R_MU_13A>,
+ <&pd IMX_SC_R_MU_13B>,
+ <&pd IMX_SC_R_DSP>,
+ <&pd IMX_SC_R_DSP_RAM>;
+ mbox-names = "txdb0", "txdb1",
+ "rxdb0", "rxdb1";
+ mboxes = <&lsio_mu13 2 0>,
+ <&lsio_mu13 2 1>,
+ <&lsio_mu13 3 0>,
+ <&lsio_mu13 3 1>;
+ reserved-region = <&dsp_reserved>;
+ status = "disabled";
+ };
+
adma_lpuart0: serial@5a060000 {
compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart";
reg = <0x5a060000 0x1000>;
--
2.17.1
On Thu, Jul 18, 2019 at 9:13 AM Daniel Baluta <[email protected]> wrote:
>
> This describes the DSP device tree node.
>
> Signed-off-by: Daniel Baluta <[email protected]>
> ---
> .../devicetree/bindings/dsp/fsl,dsp.yaml | 87 +++++++++++++++++++
> 1 file changed, 87 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
>
> diff --git a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
> new file mode 100644
> index 000000000000..d112486eda0e
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
> @@ -0,0 +1,87 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/arm/freescale/fsl,dsp.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: NXP i.MX8 DSP core
> +
> +maintainers:
> + - Daniel Baluta <[email protected]>
> +
> +description: |
> + Some boards from i.MX8 family contain a DSP core used for
> + advanced pre- and post- audio processing.
> +
> +properties:
> + compatible:
> + enum:
> + - fsl,imx8qxp-dsp
> +
> + reg:
> + description: Should contain register location and length
> +
> + clocks:
> + items:
> + - description: ipg clock
> + - description: ocram clock
> + - description: core clock
> +
> + clock-names:
> + items:
> + - const: ipg
> + - const: ocram
> + - const: core
> +
> + power-domains:
> + description:
> + List of phandle and PM domain specifier as documented in
> + Documentation/devicetree/bindings/power/power_domain.txt
How many? 4?
> +
> + mboxes:
> + description:
> + List of <&phandle type channel> - 2 channels for TXDB, 2 channels for RXDB
> + (see mailbox/fsl,mu.txt)
> + maxItems: 4
> +
> + mbox-names:
> + items:
> + - const: txdb0
> + - const: txdb1
> + - const: rxdb0
> + - const: rxdb1
> +
> + memory-region:
> + description:
> + phandle to a node describing reserved memory (System RAM memory)
> + used by DSP (see bindings/reserved-memory/reserved-memory.txt)
> + maxItems: 1
> +
> +required:
> + - compatible
> + - reg
> + - clocks
> + - clock-names
> + - power-domains
> + - mboxes
> + - mbox-names
> + - memory-region
> +
> +examples:
> + - |
> + #include <dt-bindings/firmware/imx/rsrc.h>
> + #include <dt-bindings/clock/imx8-clock.h>
> + dsp@596e8000 {
> + compatbile = "fsl,imx8qxp-dsp";
> + reg = <0x596e8000 0x88000>;
> + clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
> + <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
> + <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
> + clock-names = "ipg", "ocram", "core";
> + power-domains = <&pd IMX_SC_R_MU_13A>,
> + <&pd IMX_SC_R_MU_13B>,
> + <&pd IMX_SC_R_DSP>,
> + <&pd IMX_SC_R_DSP_RAM>;
> + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1";
> + mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>;
> + };
> --
> 2.17.1
>
On Thu, Jul 18, 2019 at 7:41 PM Rob Herring <[email protected]> wrote:
>
> On Thu, Jul 18, 2019 at 9:13 AM Daniel Baluta <[email protected]> wrote:
> >
> > This describes the DSP device tree node.
> >
> > Signed-off-by: Daniel Baluta <[email protected]>
> > ---
> > .../devicetree/bindings/dsp/fsl,dsp.yaml | 87 +++++++++++++++++++
> > 1 file changed, 87 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
> > new file mode 100644
> > index 000000000000..d112486eda0e
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
> > @@ -0,0 +1,87 @@
> > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/arm/freescale/fsl,dsp.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: NXP i.MX8 DSP core
> > +
> > +maintainers:
> > + - Daniel Baluta <[email protected]>
> > +
> > +description: |
> > + Some boards from i.MX8 family contain a DSP core used for
> > + advanced pre- and post- audio processing.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - fsl,imx8qxp-dsp
> > +
> > + reg:
> > + description: Should contain register location and length
> > +
> > + clocks:
> > + items:
> > + - description: ipg clock
> > + - description: ocram clock
> > + - description: core clock
> > +
> > + clock-names:
> > + items:
> > + - const: ipg
> > + - const: ocram
> > + - const: core
> > +
> > + power-domains:
> > + description:
> > + List of phandle and PM domain specifier as documented in
> > + Documentation/devicetree/bindings/power/power_domain.txt
>
> How many? 4?
Yes, 4 for i.MX8QXP. Also, the same number is for i.MX8QM. Anyhow, I didn't
added added a limit here because I really don't know how many will be
in upcoming
i.MX platforms.
>
> > +
> > + mboxes:
> > + description:
> > + List of <&phandle type channel> - 2 channels for TXDB, 2 channels for RXDB
> > + (see mailbox/fsl,mu.txt)
> > + maxItems: 4
> > +
> > + mbox-names:
> > + items:
> > + - const: txdb0
> > + - const: txdb1
> > + - const: rxdb0
> > + - const: rxdb1
> > +
> > + memory-region:
> > + description:
> > + phandle to a node describing reserved memory (System RAM memory)
> > + used by DSP (see bindings/reserved-memory/reserved-memory.txt)
> > + maxItems: 1
> > +
> > +required:
> > + - compatible
> > + - reg
> > + - clocks
> > + - clock-names
> > + - power-domains
> > + - mboxes
> > + - mbox-names
> > + - memory-region
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/firmware/imx/rsrc.h>
> > + #include <dt-bindings/clock/imx8-clock.h>
> > + dsp@596e8000 {
> > + compatbile = "fsl,imx8qxp-dsp";
> > + reg = <0x596e8000 0x88000>;
> > + clocks = <&adma_lpcg IMX_ADMA_LPCG_DSP_IPG_CLK>,
> > + <&adma_lpcg IMX_ADMA_LPCG_OCRAM_IPG_CLK>,
> > + <&adma_lpcg IMX_ADMA_LPCG_DSP_CORE_CLK>;
> > + clock-names = "ipg", "ocram", "core";
> > + power-domains = <&pd IMX_SC_R_MU_13A>,
> > + <&pd IMX_SC_R_MU_13B>,
> > + <&pd IMX_SC_R_DSP>,
> > + <&pd IMX_SC_R_DSP_RAM>;
> > + mbox-names = "txdb0", "txdb1", "rxdb0", "rxdb1";
> > + mboxes = <&lsio_mu13 2 0>, <&lsio_mu13 2 1>, <&lsio_mu13 3 0>, <&lsio_mu13 3 1>;
> > + };
> > --
> > 2.17.1
> >
On 18.07.2019 21:24, Daniel Baluta wrote:
> On Thu, Jul 18, 2019 at 7:41 PM Rob Herring <[email protected]> wrote:
>>
>> On Thu, Jul 18, 2019 at 9:13 AM Daniel Baluta <[email protected]> wrote:
>>>
>>> This describes the DSP device tree node.
>>>
>>> Signed-off-by: Daniel Baluta <[email protected]>
>>> + power-domains:
>>> + description:
>>> + List of phandle and PM domain specifier as documented in
>>> + Documentation/devicetree/bindings/power/power_domain.txt
>>
>> How many? 4?
>
> Yes, 4 for i.MX8QXP. Also, the same number is for i.MX8QM. Anyhow, I didn't
> added added a limit here because I really don't know how many will be
> in upcoming i.MX platforms.
Which 4? It might help to use power-domain-names explicitly just like
it's done for clocks and mboxes.
This is very common for phandle lists.
--
Regards,
Leonard
On Thu, Jul 18, 2019 at 9:40 PM Leonard Crestez <[email protected]> wrote:
>
> On 18.07.2019 21:24, Daniel Baluta wrote:
> > On Thu, Jul 18, 2019 at 7:41 PM Rob Herring <[email protected]> wrote:
> >>
> >> On Thu, Jul 18, 2019 at 9:13 AM Daniel Baluta <[email protected]> wrote:
> >>>
> >>> This describes the DSP device tree node.
> >>>
> >>> Signed-off-by: Daniel Baluta <[email protected]>
>
> >>> + power-domains:
> >>> + description:
> >>> + List of phandle and PM domain specifier as documented in
> >>> + Documentation/devicetree/bindings/power/power_domain.txt
> >>
> >> How many? 4?
> >
> > Yes, 4 for i.MX8QXP. Also, the same number is for i.MX8QM. Anyhow, I didn't
> > added added a limit here because I really don't know how many will be
> > in upcoming i.MX platforms.
>
> Which 4? It might help to use power-domain-names explicitly just like
> it's done for clocks and mboxes.
>
> This is very common for phandle lists.
4 like in the example at the bottom of the patch:
+ power-domains = <&pd IMX_SC_R_MU_13A>,
+ <&pd IMX_SC_R_MU_13B>,
+ <&pd IMX_SC_R_DSP>,
+ <&pd IMX_SC_R_DSP_RAM>;
Not sure if it makes sense to use power-domain-names as the driver parses
directly the "power-domains" property.
Hi Daniel,
thanks for your patches :) but it's quite common to bundle the driver
related and the dt related patches. Can you add the firmware related
patch to this series in your v2?
Regards,
Marco
On 19-07-18 18:13, Daniel Baluta wrote:
> i.MX8QXP boards feature an Hifi4 DSP from Tensilica. This patch series
> adds the DT node.
>
> Note that we switched to the new yaml format for bindings documentation.
>
> The DSP will run SOF Firmware [1]. Patches adding support for Linux DSP
> driver are already sent for review to SOF folks [2].
>
> This patch series also contains a patch introducing DT related clocks.
>
> The patch was already reviewed here:
> https://lkml.org/lkml/2019/7/17/975
>
> but I added it in this patch series because it wasn't yet picked by
> Shawn so patches 2/3 will not compiled without patch 1.
>
> [1] https://github.com/thesofproject/sof
> [2] https://github.com/thesofproject/linux/pull/1048/commits
>
> Daniel Baluta (3):
> clk: imx8: Add DSP related clocks
> arm64: dts: imx8qxp: Add DSP DT node
> dt-bindings: dsp: fsl: Add DSP core binding support
>
> .../devicetree/bindings/dsp/fsl,dsp.yaml | 87 +++++++++++++++++++
> arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 4 +
> arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 32 +++++++
> drivers/clk/imx/clk-imx8qxp-lpcg.c | 5 ++
> include/dt-bindings/clock/imx8-clock.h | 6 +-
> 5 files changed, 133 insertions(+), 1 deletion(-)
> create mode 100644 Documentation/devicetree/bindings/dsp/fsl,dsp.yaml
>
> --
> 2.17.1
>
>
> _______________________________________________
> linux-arm-kernel mailing list
> [email protected]
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
>
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On Fri, Jul 19, 2019 at 10:00 AM Marco Felsch <[email protected]> wrote:
>
> Hi Daniel,
>
> thanks for your patches :) but it's quite common to bundle the driver
> related and the dt related patches. Can you add the firmware related
> patch to this series in your v2?
Sure. Will do that in v2.
On Thu, Jul 18, 2019 at 06:13:44PM +0300, Daniel Baluta wrote:
> i.MX8QXP contains Hifi4 DSP. There are four clocks
> associated with DSP:
> * dsp_lpcg_core_clk
> * dsp_lpcg_ipg_clk
> * dsp_lpcg_adb_aclk
> * ocram_lpcg_ipg_clk
>
> Signed-off-by: Daniel Baluta <[email protected]>
> Reviewed-by: Dong Aisheng <[email protected]>
I already picked this one up, so you do not need to include it in the
series any more.
Shawn