From: Shannon Zhao <[email protected]>
Like commit f2ddaf8(PCI: Apply Cavium ThunderX ACS quirk to more Root
Ports), it should apply ACS quirk to ThunderX 2 root port devices.
Signed-off-by: Shannon Zhao <[email protected]>
---
drivers/pci/quirks.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 28c64f8..ea7848b 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -4224,10 +4224,12 @@ static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
* family by 0xf800 mask (which represents 8 SoCs), while the lower
* bits of device ID are used to indicate which subdevice is used
* within the SoC.
+ * Effectively selects the ThunderX 2 root ports whose device ID
+ * is 0xaf84.
*/
return (pci_is_pcie(dev) &&
(pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) &&
- ((dev->device & 0xf800) == 0xa000));
+ ((dev->device & 0xf800) == 0xa000 || dev->device == 0xaf84));
}
static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
--
1.8.3.1
See
https://lkml.kernel.org/r/[email protected]
for incidental hints (subject, commit log, commit reference). Your
patch basically extends that commit, so the subject should be very
similar.
On Fri, Jul 19, 2019 at 09:10:35PM +0800, Shannon Zhao wrote:
> From: Shannon Zhao <[email protected]>
>
> Like commit f2ddaf8(PCI: Apply Cavium ThunderX ACS quirk to more Root
> Ports), it should apply ACS quirk to ThunderX 2 root port devices.
s/root port/Root Port/ to be consistent
> Signed-off-by: Shannon Zhao <[email protected]>
I suppose this should have the same stable tag as f2ddaf8dfd4a ("PCI:
Apply Cavium ThunderX ACS quirk to more Root Ports") itself?
> ---
> drivers/pci/quirks.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> index 28c64f8..ea7848b 100644
> --- a/drivers/pci/quirks.c
> +++ b/drivers/pci/quirks.c
> @@ -4224,10 +4224,12 @@ static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
> * family by 0xf800 mask (which represents 8 SoCs), while the lower
> * bits of device ID are used to indicate which subdevice is used
> * within the SoC.
> + * Effectively selects the ThunderX 2 root ports whose device ID
> + * is 0xaf84.
> */
> return (pci_is_pcie(dev) &&
> (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) &&
> - ((dev->device & 0xf800) == 0xa000));
> + ((dev->device & 0xf800) == 0xa000 || dev->device == 0xaf84));
I'm somewhat doubtful about this because previously we at least
selected a whole class of ThunderX 1 devices:
((dev->device & 0xf800) == 0xa000)
while you're adding only a *single* ThunderX device.
I don't want a constant trickle of adding new devices. Can somebody
from Cavium or Marvell provide a corresponding mask for ThunderX 2, or
confirm that 0xaf84 is really the single device we expect to need
here?
> }
>
> static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
> --
> 1.8.3.1
>
On Wed, Jul 24, 2019 at 01:55:35PM -0500, Bjorn Helgaas wrote:
> See
> https://lkml.kernel.org/r/[email protected]
> for incidental hints (subject, commit log, commit reference). Your
> patch basically extends that commit, so the subject should be very
> similar.
>
> On Fri, Jul 19, 2019 at 09:10:35PM +0800, Shannon Zhao wrote:
> > From: Shannon Zhao <[email protected]>
> >
> > Like commit f2ddaf8(PCI: Apply Cavium ThunderX ACS quirk to more Root
> > Ports), it should apply ACS quirk to ThunderX 2 root port devices.
>
> s/root port/Root Port/ to be consistent
>
> > Signed-off-by: Shannon Zhao <[email protected]>
>
> I suppose this should have the same stable tag as f2ddaf8dfd4a ("PCI:
> Apply Cavium ThunderX ACS quirk to more Root Ports") itself?
> > ---
> > drivers/pci/quirks.c | 4 +++-
> > 1 file changed, 3 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
> > index 28c64f8..ea7848b 100644
> > --- a/drivers/pci/quirks.c
> > +++ b/drivers/pci/quirks.c
> > @@ -4224,10 +4224,12 @@ static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
> > * family by 0xf800 mask (which represents 8 SoCs), while the lower
> > * bits of device ID are used to indicate which subdevice is used
> > * within the SoC.
> > + * Effectively selects the ThunderX 2 root ports whose device ID
> > + * is 0xaf84.
> > */
> > return (pci_is_pcie(dev) &&
> > (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) &&
> > - ((dev->device & 0xf800) == 0xa000));
> > + ((dev->device & 0xf800) == 0xa000 || dev->device == 0xaf84));
>
> I'm somewhat doubtful about this because previously we at least
> selected a whole class of ThunderX 1 devices:
>
> ((dev->device & 0xf800) == 0xa000)
>
> while you're adding only a *single* ThunderX device.
>
> I don't want a constant trickle of adding new devices. Can somebody
> from Cavium or Marvell provide a corresponding mask for ThunderX 2, or
> confirm that 0xaf84 is really the single device we expect to need
> here?
We are working on a patch to fix this quirk to handle more Marvell
(Cavium) PCI IDs. Ideally we should be handling ThunderX1, ThunderX2
and the Octeon-TX families here.
Adding the folks working on this reduce the churn here, hopefully
we can get all of it sorted in one patch.
JC
On 2019/7/26 0:35, Jayachandran Chandrasekharan Nair wrote:
> On Wed, Jul 24, 2019 at 01:55:35PM -0500, Bjorn Helgaas wrote:
>> See
>> https://lkml.kernel.org/r/[email protected]
>> for incidental hints (subject, commit log, commit reference). Your
>> patch basically extends that commit, so the subject should be very
>> similar.
>>
>> On Fri, Jul 19, 2019 at 09:10:35PM +0800, Shannon Zhao wrote:
>>> From: Shannon Zhao <[email protected]>
>>>
>>> Like commit f2ddaf8(PCI: Apply Cavium ThunderX ACS quirk to more Root
>>> Ports), it should apply ACS quirk to ThunderX 2 root port devices.
>>
>> s/root port/Root Port/ to be consistent
>>
>>> Signed-off-by: Shannon Zhao <[email protected]>
>>
>> I suppose this should have the same stable tag as f2ddaf8dfd4a ("PCI:
>> Apply Cavium ThunderX ACS quirk to more Root Ports") itself?
>>> ---
>>> drivers/pci/quirks.c | 4 +++-
>>> 1 file changed, 3 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
>>> index 28c64f8..ea7848b 100644
>>> --- a/drivers/pci/quirks.c
>>> +++ b/drivers/pci/quirks.c
>>> @@ -4224,10 +4224,12 @@ static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
>>> * family by 0xf800 mask (which represents 8 SoCs), while the lower
>>> * bits of device ID are used to indicate which subdevice is used
>>> * within the SoC.
>>> + * Effectively selects the ThunderX 2 root ports whose device ID
>>> + * is 0xaf84.
>>> */
>>> return (pci_is_pcie(dev) &&
>>> (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) &&
>>> - ((dev->device & 0xf800) == 0xa000));
>>> + ((dev->device & 0xf800) == 0xa000 || dev->device == 0xaf84));
>>
>> I'm somewhat doubtful about this because previously we at least
>> selected a whole class of ThunderX 1 devices:
>>
>> ((dev->device & 0xf800) == 0xa000)
>>
>> while you're adding only a *single* ThunderX device.
>>
>> I don't want a constant trickle of adding new devices. Can somebody
>> from Cavium or Marvell provide a corresponding mask for ThunderX 2, or
>> confirm that 0xaf84 is really the single device we expect to need
>> here?
>
> We are working on a patch to fix this quirk to handle more Marvell
> (Cavium) PCI IDs. Ideally we should be handling ThunderX1, ThunderX2
> and the Octeon-TX families here.
>
> Adding the folks working on this reduce the churn here, hopefully
> we can get all of it sorted in one patch.
>
That would be better. Please CC me when you send the patch out.
Thanks,
Shannon