This set mainly added DeviceTree based CPU probe support and reworked
topology handling for MIPS. In order to prepare for pure DeviceTree
boot for Loongson64. It can also convinient Yanjie's Inegnic jz4780/X2000
SMP/SMT support.
I've done build test for bmips, nlm, ip27 and boot test for malta with
34Kf, I6400 in QEMU, Loongson64 on a Loongson-3B1500 real machine.
Thanks.
Jiaxun Yang (12):
MIPS: setup: Drop prefill_possible_map
MIPS: prom: Add helper to parse CPU node in dt
arch_topology: Make it avilable for MIPS
arch_topology: Reset all cpus in reset_cpu_topology
MIPS: Switch to arch_topology
MIPS: Kernel: Switch to new topology interface
MIPS: CPS & MT: Switch to new topology interface
irqchip: mips-cpu: Switch to new topology interface
MIPS: bmips: Switch to new topology interface
MIPS: nlm: Switch to new topology interface
MIPS: Loongson64: Switch to new topology interface
MIPS: ip27: Fix includes
arch/mips/Kconfig | 1 +
arch/mips/include/asm/cpu-info.h | 49 -------
arch/mips/include/asm/mach-ip27/mmzone.h | 2 +
arch/mips/include/asm/mach-ip27/topology.h | 2 +
.../include/asm/mach-loongson64/topology.h | 2 +
arch/mips/include/asm/mips-cm.h | 9 +-
arch/mips/include/asm/mips-cps.h | 2 +
arch/mips/include/asm/prom.h | 2 +
arch/mips/include/asm/smp-ops.h | 2 -
arch/mips/include/asm/smp.h | 2 -
arch/mips/include/asm/sn/addrs.h | 1 +
arch/mips/include/asm/topology.h | 48 ++++++-
arch/mips/kernel/cacheinfo.c | 5 +-
arch/mips/kernel/cpu-probe.c | 43 ------
arch/mips/kernel/mips-cm.c | 4 +-
arch/mips/kernel/mips-cpc.c | 4 +-
arch/mips/kernel/perf_event_mipsxx.c | 4 +-
arch/mips/kernel/pm-cps.c | 12 +-
arch/mips/kernel/proc.c | 8 +-
arch/mips/kernel/prom.c | 96 ++++++++++++++
arch/mips/kernel/setup.c | 22 +---
arch/mips/kernel/smp-bmips.c | 3 +-
arch/mips/kernel/smp-cmp.c | 5 +-
arch/mips/kernel/smp-cps.c | 41 +++---
arch/mips/kernel/smp-mt.c | 3 +-
arch/mips/kernel/smp.c | 55 +-------
arch/mips/kernel/topology.c | 42 ++++++
arch/mips/loongson64/smp.c | 20 +--
arch/mips/mm/c-r4k.c | 4 +-
arch/mips/mm/context.c | 4 +-
arch/mips/netlogic/common/smp.c | 4 +-
arch/mips/oprofile/op_model_mipsxx.c | 4 +-
drivers/base/arch_topology.c | 123 ++++++++++--------
drivers/irqchip/irq-mips-cpu.c | 2 +-
34 files changed, 337 insertions(+), 293 deletions(-)
--
2.26.0.rc2
For MIPS platform, when topology isn't probed by DeviceTree,
possible_cpu might be empty when calling init_cpu_topology,
that may result cpu_topology not fully reseted for all CPUs.
So here we can reset all cpus instead of possible cpus.
Signed-off-by: Jiaxun Yang <[email protected]>
---
drivers/base/arch_topology.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c
index 9c2405d08dae..3398b7ac7dfb 100644
--- a/drivers/base/arch_topology.c
+++ b/drivers/base/arch_topology.c
@@ -542,7 +542,7 @@ void __init reset_cpu_topology(void)
{
unsigned int cpu;
- for_each_possible_cpu(cpu) {
+ for (cpu = 0; cpu < NR_CPUS; cpu++) {
struct cpu_topology *cpu_topo = &cpu_topology[cpu];
cpu_topo->thread_id = -1;
--
2.26.0.rc2
Previously, MIPS is using self-defined "globalnumber" in struct
mips_cpuinfo to store topology information. However, it's not friendly
to DeviceTree based systems and lack of cpu_capacity related feature
which can take advantage of multi-cluster system.
Here, we enabled arch_topology for MIPS and adapted some functions
to fit arch_topology structure.
Also, we implmented smp_store_cpu_info to probe CPU's topology information
by "globalnumber" registers in VP ASE or Ebase.CPUNum for legacy systems.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/Kconfig | 1 +
arch/mips/include/asm/cpu-info.h | 49 ----------------------------
arch/mips/include/asm/smp.h | 2 --
arch/mips/include/asm/topology.h | 48 +++++++++++++++++++++++++---
arch/mips/kernel/cpu-probe.c | 43 -------------------------
arch/mips/kernel/setup.c | 1 +
arch/mips/kernel/smp.c | 55 ++++----------------------------
arch/mips/kernel/topology.c | 42 ++++++++++++++++++++++++
8 files changed, 93 insertions(+), 148 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 690718b3701a..66b57e9f2b4d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -20,6 +20,7 @@ config MIPS
select CLONE_BACKWARDS
select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
select CPU_PM if CPU_IDLE
+ select GENERIC_ARCH_TOPOLOGY if SMP
select GENERIC_ATOMIC64 if !64BIT
select GENERIC_CLOCKEVENTS
select GENERIC_CMOS_UPDATE
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index ed7ffe4e63a3..7140a3e61ce3 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -78,8 +78,6 @@ struct cpuinfo_mips {
struct cache_desc scache; /* Secondary cache */
struct cache_desc tcache; /* Tertiary/split secondary cache */
int srsets; /* Shadow register sets */
- int package;/* physical package number */
- unsigned int globalnumber;
#ifdef CONFIG_64BIT
int vmbits; /* Virtual memory size in bits */
#endif
@@ -139,53 +137,6 @@ struct proc_cpuinfo_notifier_args {
unsigned long n;
};
-static inline unsigned int cpu_cluster(struct cpuinfo_mips *cpuinfo)
-{
- /* Optimisation for systems where multiple clusters aren't used */
- if (!IS_ENABLED(CONFIG_CPU_MIPSR6))
- return 0;
-
- return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_CLUSTER) >>
- MIPS_GLOBALNUMBER_CLUSTER_SHF;
-}
-
-static inline unsigned int cpu_core(struct cpuinfo_mips *cpuinfo)
-{
- return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_CORE) >>
- MIPS_GLOBALNUMBER_CORE_SHF;
-}
-
-static inline unsigned int cpu_vpe_id(struct cpuinfo_mips *cpuinfo)
-{
- /* Optimisation for systems where VP(E)s aren't used */
- if (!IS_ENABLED(CONFIG_MIPS_MT_SMP) && !IS_ENABLED(CONFIG_CPU_MIPSR6))
- return 0;
-
- return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_VP) >>
- MIPS_GLOBALNUMBER_VP_SHF;
-}
-
-extern void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster);
-extern void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core);
-extern void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe);
-
-static inline bool cpus_are_siblings(int cpua, int cpub)
-{
- struct cpuinfo_mips *infoa = &cpu_data[cpua];
- struct cpuinfo_mips *infob = &cpu_data[cpub];
- unsigned int gnuma, gnumb;
-
- if (infoa->package != infob->package)
- return false;
-
- gnuma = infoa->globalnumber & ~MIPS_GLOBALNUMBER_VP;
- gnumb = infob->globalnumber & ~MIPS_GLOBALNUMBER_VP;
- if (gnuma != gnumb)
- return false;
-
- return true;
-}
-
static inline unsigned long cpu_asid_inc(void)
{
return 1 << CONFIG_MIPS_ASID_SHIFT;
diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
index 7990c1c70471..538e73f6bab0 100644
--- a/arch/mips/include/asm/smp.h
+++ b/arch/mips/include/asm/smp.h
@@ -21,8 +21,6 @@
#include <asm/smp-ops.h>
extern int smp_num_siblings;
-extern cpumask_t cpu_sibling_map[];
-extern cpumask_t cpu_core_map[];
extern cpumask_t cpu_foreign_map[];
static inline int raw_smp_processor_id(void)
diff --git a/arch/mips/include/asm/topology.h b/arch/mips/include/asm/topology.h
index 0673d2d0f2e6..e2044bbde53d 100644
--- a/arch/mips/include/asm/topology.h
+++ b/arch/mips/include/asm/topology.h
@@ -9,13 +9,51 @@
#define __ASM_TOPOLOGY_H
#include <topology.h>
+#include <linux/arch_topology.h>
#include <linux/smp.h>
-#ifdef CONFIG_SMP
-#define topology_physical_package_id(cpu) (cpu_data[cpu].package)
-#define topology_core_id(cpu) (cpu_core(&cpu_data[cpu]))
-#define topology_core_cpumask(cpu) (&cpu_core_map[cpu])
-#define topology_sibling_cpumask(cpu) (&cpu_sibling_map[cpu])
+#if defined(CONFIG_SMP)
+static inline bool cpus_are_siblings(int cpua, int cpub)
+{
+ return cpumask_test_cpu(cpua, topology_sibling_cpumask(cpub));
+}
+
+static inline unsigned int cpu_cluster(int cpu)
+{
+ return cpu_topology[cpu].package_id;
+}
+
+static inline unsigned int cpu_core(int cpu)
+{
+ return cpu_topology[cpu].core_id;
+}
+
+static inline unsigned int cpu_vpe_id(int cpu)
+{
+ int id = cpu_topology[cpu].thread_id;
+
+ /* Uniprocessor system may get -1, but for hardware it's 0 */
+ if (id == -1)
+ return 0;
+
+ return id;
+}
+
+static inline void cpu_set_cluster(int cpu, unsigned int cluster)
+{
+ cpu_topology[cpu].package_id = cluster;
+}
+
+static inline void cpu_set_core(int cpu, unsigned int core)
+{
+ cpu_topology[cpu].core_id = core;
+}
+
+static inline void cpu_set_vpe_id(int cpu, unsigned int vpe)
+{
+ cpu_topology[cpu].thread_id = vpe;
+}
+
#endif
#endif /* __ASM_TOPOLOGY_H */
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index f21a2304401f..eead35e5dbfd 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1042,17 +1042,6 @@ static void decode_configs(struct cpuinfo_mips *c)
set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
mips_probe_watch_registers(c);
-
-#ifndef CONFIG_MIPS_CPS
- if (cpu_has_mips_r2_r6) {
- unsigned int core;
-
- core = get_ebase_cpunum();
- if (cpu_has_mipsmt)
- core >>= fls(core_nvpes()) - 1;
- cpu_set_core(c, core);
- }
-#endif
}
/*
@@ -2303,35 +2292,3 @@ void cpu_report(void)
if (cpu_has_msa)
pr_info("MSA revision is: %08x\n", c->msa_id);
}
-
-void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster)
-{
- /* Ensure the core number fits in the field */
- WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >>
- MIPS_GLOBALNUMBER_CLUSTER_SHF));
-
- cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER;
- cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF;
-}
-
-void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core)
-{
- /* Ensure the core number fits in the field */
- WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF));
-
- cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE;
- cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF;
-}
-
-void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe)
-{
- /* Ensure the VP(E) ID fits in the field */
- WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF));
-
- /* Ensure we're not using VP(E)s without support */
- WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) &&
- !IS_ENABLED(CONFIG_CPU_MIPSR6));
-
- cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP;
- cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF;
-}
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 8a418783a6bb..b9fefc5dc702 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -784,6 +784,7 @@ void __init setup_arch(char **cmdline_p)
dmi_setup();
resource_init();
+ init_cpu_topology();
plat_smp_setup();
cpu_cache_init();
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 48d84d5fcc36..4896d6ecc719 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -34,6 +34,7 @@
#include <asm/mips-cps.h>
#include <asm/mmu_context.h>
#include <asm/time.h>
+#include <asm/topology.h>
#include <asm/setup.h>
#include <asm/maar.h>
@@ -47,10 +48,6 @@ EXPORT_SYMBOL(__cpu_logical_map);
int smp_num_siblings = 1;
EXPORT_SYMBOL(smp_num_siblings);
-/* representing the TCs (or siblings in Intel speak) of each logical CPU */
-cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
-EXPORT_SYMBOL(cpu_sibling_map);
-
/* representing the core map of multi-core chips of each logical CPU */
cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
EXPORT_SYMBOL(cpu_core_map);
@@ -65,12 +62,6 @@ static DECLARE_COMPLETION(cpu_running);
cpumask_t cpu_foreign_map[NR_CPUS] __read_mostly;
EXPORT_SYMBOL(cpu_foreign_map);
-/* representing cpus for which sibling maps can be computed */
-static cpumask_t cpu_sibling_setup_map;
-
-/* representing cpus for which core maps can be computed */
-static cpumask_t cpu_core_setup_map;
-
cpumask_t cpu_coherent_mask;
#ifdef CONFIG_GENERIC_IRQ_IPI
@@ -78,37 +69,6 @@ static struct irq_desc *call_desc;
static struct irq_desc *sched_desc;
#endif
-static inline void set_cpu_sibling_map(int cpu)
-{
- int i;
-
- cpumask_set_cpu(cpu, &cpu_sibling_setup_map);
-
- if (smp_num_siblings > 1) {
- for_each_cpu(i, &cpu_sibling_setup_map) {
- if (cpus_are_siblings(cpu, i)) {
- cpumask_set_cpu(i, &cpu_sibling_map[cpu]);
- cpumask_set_cpu(cpu, &cpu_sibling_map[i]);
- }
- }
- } else
- cpumask_set_cpu(cpu, &cpu_sibling_map[cpu]);
-}
-
-static inline void set_cpu_core_map(int cpu)
-{
- int i;
-
- cpumask_set_cpu(cpu, &cpu_core_setup_map);
-
- for_each_cpu(i, &cpu_core_setup_map) {
- if (cpu_data[cpu].package == cpu_data[i].package) {
- cpumask_set_cpu(i, &cpu_core_map[cpu]);
- cpumask_set_cpu(cpu, &cpu_core_map[i]);
- }
- }
-}
-
/*
* Calculate a new cpu_foreign_map mask whenever a
* new cpu appears or disappears.
@@ -131,7 +91,7 @@ void calculate_cpu_foreign_map(void)
for_each_online_cpu(i)
cpumask_andnot(&cpu_foreign_map[i],
- &temp_foreign_map, &cpu_sibling_map[i]);
+ &temp_foreign_map, topology_sibling_cpumask(i));
}
const struct plat_smp_ops *mp_ops;
@@ -177,7 +137,7 @@ void mips_smp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
if (cpus_are_siblings(cpu, smp_processor_id()))
continue;
- core = cpu_core(&cpu_data[cpu]);
+ core = cpu_core(cpu);
while (!cpumask_test_cpu(cpu, &cpu_coherent_mask)) {
mips_cm_lock_other_cpu(cpu, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
@@ -340,6 +300,8 @@ asmlinkage void start_secondary(void)
mips_clockevent_init();
mp_ops->init_secondary();
cpu_report();
+ cpu = smp_processor_id();
+ store_cpu_topology(cpu);
maar_init();
/*
@@ -349,7 +311,6 @@ asmlinkage void start_secondary(void)
calibrate_delay();
preempt_disable();
- cpu = smp_processor_id();
cpu_data[cpu].udelay_val = loops_per_jiffy;
cpumask_set_cpu(cpu, &cpu_coherent_mask);
@@ -363,9 +324,6 @@ asmlinkage void start_secondary(void)
/* The CPU is running and counters synchronised, now mark it online */
set_cpu_online(cpu, true);
- set_cpu_sibling_map(cpu);
- set_cpu_core_map(cpu);
-
calculate_cpu_foreign_map();
/*
@@ -411,8 +369,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
init_new_context(current, &init_mm);
current_thread_info()->cpu = 0;
mp_ops->prepare_cpus(max_cpus);
- set_cpu_sibling_map(0);
- set_cpu_core_map(0);
+ store_cpu_topology(0);
calculate_cpu_foreign_map();
#ifndef CONFIG_HOTPLUG_CPU
init_cpu_present(cpu_possible_mask);
diff --git a/arch/mips/kernel/topology.c b/arch/mips/kernel/topology.c
index cd3e1f82e1a5..112482de8187 100644
--- a/arch/mips/kernel/topology.c
+++ b/arch/mips/kernel/topology.c
@@ -31,3 +31,45 @@ static int __init topology_init(void)
}
subsys_initcall(topology_init);
+
+#if defined(CONFIG_SMP)
+void store_cpu_topology(unsigned int cpuid)
+{
+ struct cpu_topology *cpuid_topo = &cpu_topology[cpuid];
+
+ if (cpuid_topo->package_id != -1)
+ goto topology_populated;
+
+ if (cpu_has_vp) {
+ u32 gn = read_c0_globalnumber();
+
+ cpuid_topo->thread_id = (gn & MIPS_GLOBALNUMBER_VP) >>
+ MIPS_GLOBALNUMBER_VP_SHF;
+ cpuid_topo->core_id = (gn & MIPS_GLOBALNUMBER_CORE) >>
+ MIPS_GLOBALNUMBER_CORE_SHF;
+ cpuid_topo->package_id = (gn & MIPS_GLOBALNUMBER_CLUSTER) >>
+ MIPS_GLOBALNUMBER_CLUSTER_SHF;
+ } else {
+ int hwid;
+
+ if (cpu_has_mips_r2_r6)
+ hwid = get_ebase_cpunum();
+ else
+ hwid = cpuid; /* Assume hwid = cpuid */
+
+ if (smp_num_siblings == 1)
+ cpuid_topo->thread_id = -1;
+ else
+ cpuid_topo->thread_id = hwid % smp_num_siblings;
+
+ cpuid_topo->core_id = hwid / smp_num_siblings;
+ /* Platform code will handle multi-cluster case */
+ cpuid_topo->package_id = 0;
+ }
+
+topology_populated:
+ update_siblings_masks(cpuid);
+ pr_info("Topology: CPU %d: cluster: %d, core: %d, vpe: %d\n", cpuid,
+ cpu_cluster(cpuid), cpu_core(cpuid), cpu_vpe_id(cpuid));
+}
+#endif
--
2.26.0.rc2
All the plat_smp_setup are setting up possible cpus in their
platform code. So prefill_possible_map is actually overwriting
platform's setup, which seems unreasonable.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/kernel/setup.c | 20 --------------------
1 file changed, 20 deletions(-)
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 10bef8f78e7c..8a418783a6bb 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -761,25 +761,6 @@ static void __init resource_init(void)
}
}
-#ifdef CONFIG_SMP
-static void __init prefill_possible_map(void)
-{
- int i, possible = num_possible_cpus();
-
- if (possible > nr_cpu_ids)
- possible = nr_cpu_ids;
-
- for (i = 0; i < possible; i++)
- set_cpu_possible(i, true);
- for (; i < NR_CPUS; i++)
- set_cpu_possible(i, false);
-
- nr_cpu_ids = possible;
-}
-#else
-static inline void prefill_possible_map(void) {}
-#endif
-
void __init setup_arch(char **cmdline_p)
{
cpu_probe();
@@ -804,7 +785,6 @@ void __init setup_arch(char **cmdline_p)
resource_init();
plat_smp_setup();
- prefill_possible_map();
cpu_cache_init();
paging_init();
--
2.26.0.rc2
Mostly identical with arm one. The only difference is that we allow
to mark a CPU Node as status = "disabled" in dt, which means the core
is physicaly present, but not possible for the kernel. It will occupy
a bit in cpumask as well.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/include/asm/prom.h | 2 +
arch/mips/kernel/prom.c | 96 ++++++++++++++++++++++++++++++++++++
2 files changed, 98 insertions(+)
diff --git a/arch/mips/include/asm/prom.h b/arch/mips/include/asm/prom.h
index c42e07671934..1ec46e09dc8b 100644
--- a/arch/mips/include/asm/prom.h
+++ b/arch/mips/include/asm/prom.h
@@ -19,9 +19,11 @@ struct boot_param_header;
extern void __dt_setup_arch(void *bph);
extern int __dt_register_buses(const char *bus0, const char *bus1);
+extern void mips_dt_init_cpu_maps(void);
#else /* CONFIG_OF */
static inline void device_tree_init(void) { }
+static inline void mips_dt_init_cpu_maps(void) { }
#endif /* CONFIG_OF */
extern char *mips_get_machine_name(void);
diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c
index 9e50dc8df2f6..ebeb22ffa76a 100644
--- a/arch/mips/kernel/prom.c
+++ b/arch/mips/kernel/prom.c
@@ -89,4 +89,100 @@ int __init __dt_register_buses(const char *bus0, const char *bus1)
return 0;
}
+void __init mips_dt_init_cpu_maps(void)
+{
+ struct device_node *cpu, *cpus;
+ u32 i, j, cpuidx = 1;
+ u32 cpunum;
+ u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = U32_MAX };
+ bool cpu_possible[NR_CPUS] = { [0 ... NR_CPUS-1] = false };
+ bool bootcpu_valid = false;
+
+ cpus = of_find_node_by_path("/cpus");
+ if (!cpus)
+ return;
+
+ if (cpu_has_mips_r2_r6)
+ cpunum = get_ebase_cpunum();
+ else
+ cpunum = 0; /* For legacy system we assume boot from CPU 0 */
+
+ for_each_of_cpu_node(cpu) {
+ u32 hwid;
+
+ pr_debug(" * %pOF...\n", cpu);
+ /*
+ * A device tree containing CPU nodes with missing "reg"
+ * properties is considered invalid to build the
+ * cpu_logical_map.
+ */
+
+ if (of_property_read_u32(cpu, "reg", &hwid)) {
+ pr_debug(" * %pOF missing reg property\n", cpu);
+ of_node_put(cpu);
+ return;
+ }
+
+ /*
+ * Duplicate hwid are a recipe for disaster.
+ * Scan all initialized entries and check for
+ * duplicates. If any is found just bail out.
+ */
+ for (j = 0; j < cpuidx; j++)
+ if (WARN(tmp_map[j] == hwid,
+ "Duplicate /cpu reg properties in the DT\n")) {
+ of_node_put(cpu);
+ return;
+ }
+
+ /*
+ * Build a stashed array of hwid values. Numbering scheme
+ * requires that if detected the boot CPU must be assigned
+ * logical id 0. Other CPUs get sequential indexes starting
+ * from 1. If a CPU node with a reg property matching the
+ * boot CPU hwid is detected, this is recorded so that the
+ * logical map built from DT is validated.
+ */
+ if (hwid == cpunum) {
+ i = 0;
+ if (of_device_is_available(cpu))
+ bootcpu_valid = true;
+ } else {
+ i = cpuidx++;
+ }
+
+ if (WARN(cpuidx > nr_cpu_ids, "DT /cpu %u nodes greater than "
+ "max cores %u, capping them\n",
+ cpuidx, nr_cpu_ids)) {
+ cpuidx = nr_cpu_ids;
+ of_node_put(cpu);
+ break;
+ }
+
+ tmp_map[i] = hwid;
+
+ if (of_device_is_available(cpu))
+ cpu_possible[i] = true;
+ }
+
+ if (!bootcpu_valid) {
+ pr_warn("DT missing boot CPU, fall back to default cpu_logical_map\n");
+ return;
+ }
+
+ init_cpu_possible(cpu_none_mask);
+ init_cpu_present(cpu_none_mask);
+
+ for (i = 0; i < cpuidx; i++) {
+ set_cpu_possible(i, cpu_possible[i]);
+ cpu_logical_map(i) = tmp_map[i];
+ pr_debug("cpu logical map 0x%x\n", cpu_logical_map(i));
+ }
+}
+
+bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
+{
+ return phys_id == cpu_logical_map(cpu);
+}
+
#endif
--
2.26.0.rc2
Simply drop unnecessary archtecture limitions and add dummy
function for platforms without OF/COMMON_CLK support.
Also exclude functions for arm that existed in platform code.
Signed-off-by: Jiaxun Yang <[email protected]>
---
drivers/base/arch_topology.c | 121 +++++++++++++++++++----------------
1 file changed, 66 insertions(+), 55 deletions(-)
diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c
index 4d0a0038b476..9c2405d08dae 100644
--- a/drivers/base/arch_topology.c
+++ b/drivers/base/arch_topology.c
@@ -143,57 +143,6 @@ void topology_normalize_cpu_scale(void)
}
}
-bool __init topology_parse_cpu_capacity(struct device_node *cpu_node, int cpu)
-{
- struct clk *cpu_clk;
- static bool cap_parsing_failed;
- int ret;
- u32 cpu_capacity;
-
- if (cap_parsing_failed)
- return false;
-
- ret = of_property_read_u32(cpu_node, "capacity-dmips-mhz",
- &cpu_capacity);
- if (!ret) {
- if (!raw_capacity) {
- raw_capacity = kcalloc(num_possible_cpus(),
- sizeof(*raw_capacity),
- GFP_KERNEL);
- if (!raw_capacity) {
- cap_parsing_failed = true;
- return false;
- }
- }
- raw_capacity[cpu] = cpu_capacity;
- pr_debug("cpu_capacity: %pOF cpu_capacity=%u (raw)\n",
- cpu_node, raw_capacity[cpu]);
-
- /*
- * Update freq_factor for calculating early boot cpu capacities.
- * For non-clk CPU DVFS mechanism, there's no way to get the
- * frequency value now, assuming they are running at the same
- * frequency (by keeping the initial freq_factor value).
- */
- cpu_clk = of_clk_get(cpu_node, 0);
- if (!PTR_ERR_OR_ZERO(cpu_clk)) {
- per_cpu(freq_factor, cpu) =
- clk_get_rate(cpu_clk) / 1000;
- clk_put(cpu_clk);
- }
- } else {
- if (raw_capacity) {
- pr_err("cpu_capacity: missing %pOF raw capacity\n",
- cpu_node);
- pr_err("cpu_capacity: partial information: fallback to 1024 for all CPUs\n");
- }
- cap_parsing_failed = true;
- free_raw_capacity();
- }
-
- return !ret;
-}
-
#ifdef CONFIG_CPU_FREQ
static cpumask_var_t cpus_to_visit;
static void parsing_done_workfn(struct work_struct *work);
@@ -275,7 +224,64 @@ static void parsing_done_workfn(struct work_struct *work)
core_initcall(free_raw_capacity);
#endif
-#if defined(CONFIG_ARM64) || defined(CONFIG_RISCV)
+#if defined(CONFIG_OF) && !defined(CONFIG_ARM)
+#if defined(CONFIG_COMMON_CLK)
+bool __init topology_parse_cpu_capacity(struct device_node *cpu_node, int cpu)
+{
+ struct clk *cpu_clk;
+ static bool cap_parsing_failed;
+ int ret;
+ u32 cpu_capacity;
+
+ if (cap_parsing_failed)
+ return false;
+
+ ret = of_property_read_u32(cpu_node, "capacity-dmips-mhz",
+ &cpu_capacity);
+ if (!ret) {
+ if (!raw_capacity) {
+ raw_capacity = kcalloc(num_possible_cpus(),
+ sizeof(*raw_capacity),
+ GFP_KERNEL);
+ if (!raw_capacity) {
+ cap_parsing_failed = true;
+ return false;
+ }
+ }
+ raw_capacity[cpu] = cpu_capacity;
+ pr_debug("cpu_capacity: %pOF cpu_capacity=%u (raw)\n",
+ cpu_node, raw_capacity[cpu]);
+
+ /*
+ * Update freq_factor for calculating early boot cpu capacities.
+ * For non-clk CPU DVFS mechanism, there's no way to get the
+ * frequency value now, assuming they are running at the same
+ * frequency (by keeping the initial freq_factor value).
+ */
+ cpu_clk = of_clk_get(cpu_node, 0);
+ if (!PTR_ERR_OR_ZERO(cpu_clk)) {
+ per_cpu(freq_factor, cpu) =
+ clk_get_rate(cpu_clk) / 1000;
+ clk_put(cpu_clk);
+ }
+ } else {
+ if (raw_capacity) {
+ pr_err("cpu_capacity: missing %pOF raw capacity\n",
+ cpu_node);
+ pr_err("cpu_capacity: partial information: fallback to 1024 for all CPUs\n");
+ }
+ cap_parsing_failed = true;
+ free_raw_capacity();
+ }
+
+ return !ret;
+}
+#else
+bool __init topology_parse_cpu_capacity(struct device_node *cpu_node, int cpu)
+{
+ return false;
+}
+#endif /* CONFIG_COMMON_CLK */
/*
* This function returns the logic cpu number of the node.
* There are basically three kinds of return values:
@@ -461,7 +467,12 @@ static int __init parse_dt_topology(void)
of_node_put(cn);
return ret;
}
-#endif
+#else
+static int __init parse_dt_topology(void)
+{
+ return 0;
+}
+#endif /* CONFIG_OF & !CONFIG_ARM */
/*
* cpu topology table
@@ -562,7 +573,7 @@ __weak int __init parse_acpi_topology(void)
return 0;
}
-#if defined(CONFIG_ARM64) || defined(CONFIG_RISCV)
+#if !defined(CONFIG_ARM)
void __init init_cpu_topology(void)
{
reset_cpu_topology();
@@ -576,4 +587,4 @@ void __init init_cpu_topology(void)
else if (of_have_populated_dt() && parse_dt_topology())
reset_cpu_topology();
}
-#endif
+#endif /* !CONFIG_ARM */
--
2.26.0.rc2
Change the parameter of cpu_vpe_id from cpu_data to cpuid.
Signed-off-by: Jiaxun Yang <[email protected]>
---
drivers/irqchip/irq-mips-cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c
index 95d4fd8f7a96..eed3edf8480b 100644
--- a/drivers/irqchip/irq-mips-cpu.c
+++ b/drivers/irqchip/irq-mips-cpu.c
@@ -100,7 +100,7 @@ static void mips_mt_send_ipi(struct irq_data *d, unsigned int cpu)
WARN_ON(!cpus_are_siblings(smp_processor_id(), cpu));
vpflags = dvpe();
- settc(cpu_vpe_id(&cpu_data[cpu]));
+ settc(cpu_vpe_id(cpu));
write_vpe_c0_cause(read_vpe_c0_cause() | (C_SW0 << hwirq));
evpe(vpflags);
--
2.26.0.rc2
Use new functions to set core_id & cluster_id.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/netlogic/common/smp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c
index 39a300bd6cc2..14bfa8a099cc 100644
--- a/arch/mips/netlogic/common/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -122,8 +122,8 @@ static void nlm_init_secondary(void)
int hwtid;
hwtid = hard_smp_processor_id();
- cpu_set_core(¤t_cpu_data, hwtid / NLM_THREADS_PER_CORE);
- current_cpu_data.package = nlm_nodeid();
+ cpu_set_core(smp_processor_id(), hwtid / NLM_THREADS_PER_CORE);
+ cpu_set_cluster(smp_processor_id(), nlm_nodeid());
nlm_percpu_init(hwtid);
nlm_smp_irq_init(hwtid);
}
--
2.26.0.rc2
Use the new interface to setup topology information.
Signed-off-by: Jiaxun Yang <[email protected]>
---
.../include/asm/mach-loongson64/topology.h | 2 ++
arch/mips/loongson64/smp.c | 20 +++++++++----------
2 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/arch/mips/include/asm/mach-loongson64/topology.h b/arch/mips/include/asm/mach-loongson64/topology.h
index 3414a1fd1783..999464ed0c20 100644
--- a/arch/mips/include/asm/mach-loongson64/topology.h
+++ b/arch/mips/include/asm/mach-loongson64/topology.h
@@ -2,6 +2,8 @@
#ifndef _ASM_MACH_TOPOLOGY_H
#define _ASM_MACH_TOPOLOGY_H
+#include <linux/numa.h>
+
#ifdef CONFIG_NUMA
#define cpu_to_node(cpu) (cpu_logical_map(cpu) >> 2)
diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
index e1fe8bbb377d..bb37d0a7e79c 100644
--- a/arch/mips/loongson64/smp.c
+++ b/arch/mips/loongson64/smp.c
@@ -353,10 +353,10 @@ static void loongson3_init_secondary(void)
loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(i)]);
per_cpu(cpu_state, cpu) = CPU_ONLINE;
- cpu_set_core(&cpu_data[cpu],
+ cpu_set_core(cpu,
cpu_logical_map(cpu) % loongson_sysconf.cores_per_package);
- cpu_data[cpu].package =
- cpu_logical_map(cpu) / loongson_sysconf.cores_per_package;
+ cpu_set_cluster(cpu,
+ cpu_logical_map(cpu) / loongson_sysconf.cores_per_package);
i = 0;
core0_c0count[cpu] = 0;
@@ -368,7 +368,7 @@ static void loongson3_init_secondary(void)
if (i > MAX_LOOPS)
i = MAX_LOOPS;
- if (cpu_data[cpu].package)
+ if (cpu_cluster(cpu))
initcount = core0_c0count[cpu] + i;
else /* Local access is faster for loops */
initcount = core0_c0count[cpu] + i/2;
@@ -421,9 +421,9 @@ static void __init loongson3_smp_setup(void)
ipi_status0_regs_init();
ipi_en0_regs_init();
ipi_mailbox_buf_init();
- cpu_set_core(&cpu_data[0],
+ cpu_set_core(0,
cpu_logical_map(0) % loongson_sysconf.cores_per_package);
- cpu_data[0].package = cpu_logical_map(0) / loongson_sysconf.cores_per_package;
+ cpu_set_cluster(0, cpu_logical_map(0) / loongson_sysconf.cores_per_package);
}
static void __init loongson3_prepare_cpus(unsigned int max_cpus)
@@ -752,8 +752,8 @@ void play_dead(void)
static int loongson3_disable_clock(unsigned int cpu)
{
- uint64_t core_id = cpu_core(&cpu_data[cpu]);
- uint64_t package_id = cpu_data[cpu].package;
+ uint64_t core_id = cpu_core(cpu);
+ uint64_t package_id = cpu_cluster(cpu);
if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) {
LOONGSON_CHIPCFG(package_id) &= ~(1 << (12 + core_id));
@@ -766,8 +766,8 @@ static int loongson3_disable_clock(unsigned int cpu)
static int loongson3_enable_clock(unsigned int cpu)
{
- uint64_t core_id = cpu_core(&cpu_data[cpu]);
- uint64_t package_id = cpu_data[cpu].package;
+ uint64_t core_id = cpu_core(cpu);
+ uint64_t package_id = cpu_cluster(cpu);
if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) {
LOONGSON_CHIPCFG(package_id) |= 1 << (12 + core_id);
--
2.26.0.rc2
Somehow changes in topology messed up headers.
So just add necessary headers to make it compile again.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/include/asm/mach-ip27/mmzone.h | 2 ++
arch/mips/include/asm/mach-ip27/topology.h | 2 ++
arch/mips/include/asm/sn/addrs.h | 1 +
3 files changed, 5 insertions(+)
diff --git a/arch/mips/include/asm/mach-ip27/mmzone.h b/arch/mips/include/asm/mach-ip27/mmzone.h
index 08c36e50a860..e0a53b97b4a8 100644
--- a/arch/mips/include/asm/mach-ip27/mmzone.h
+++ b/arch/mips/include/asm/mach-ip27/mmzone.h
@@ -2,6 +2,8 @@
#ifndef _ASM_MACH_MMZONE_H
#define _ASM_MACH_MMZONE_H
+#include <linux/mmzone.h>
+
#include <asm/sn/addrs.h>
#include <asm/sn/arch.h>
#include <asm/sn/agent.h>
diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h
index d66cc53feab8..601e350908f7 100644
--- a/arch/mips/include/asm/mach-ip27/topology.h
+++ b/arch/mips/include/asm/mach-ip27/topology.h
@@ -2,6 +2,8 @@
#ifndef _ASM_MACH_TOPOLOGY_H
#define _ASM_MACH_TOPOLOGY_H 1
+#include <linux/numa.h>
+
#include <asm/sn/types.h>
#include <asm/mmzone.h>
diff --git a/arch/mips/include/asm/sn/addrs.h b/arch/mips/include/asm/sn/addrs.h
index 837d23e24976..1d3945ef2ca4 100644
--- a/arch/mips/include/asm/sn/addrs.h
+++ b/arch/mips/include/asm/sn/addrs.h
@@ -13,6 +13,7 @@
#ifndef __ASSEMBLY__
#include <linux/smp.h>
#include <linux/types.h>
+#include <asm/io.h>
#endif /* !__ASSEMBLY__ */
#include <asm/addrspace.h>
--
2.26.0.rc2
Adapt topology functions to new interface in various of kernel
parts like perf, proc.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/kernel/cacheinfo.c | 5 +++--
arch/mips/kernel/perf_event_mipsxx.c | 4 ++--
arch/mips/kernel/proc.c | 8 ++++----
arch/mips/mm/c-r4k.c | 4 ++--
arch/mips/mm/context.c | 4 ++--
arch/mips/oprofile/op_model_mipsxx.c | 4 ++--
6 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/arch/mips/kernel/cacheinfo.c b/arch/mips/kernel/cacheinfo.c
index 47312c529410..582c866b294f 100644
--- a/arch/mips/kernel/cacheinfo.c
+++ b/arch/mips/kernel/cacheinfo.c
@@ -3,6 +3,7 @@
* MIPS cacheinfo support
*/
#include <linux/cacheinfo.h>
+#include <asm/topology.h>
/* Populates leaf and increments to next leaf */
#define populate_cache(cache, leaf, c_level, c_type) \
@@ -62,10 +63,10 @@ static void fill_cpumask_siblings(int cpu, cpumask_t *cpu_map)
static void fill_cpumask_cluster(int cpu, cpumask_t *cpu_map)
{
int cpu1;
- int cluster = cpu_cluster(&cpu_data[cpu]);
+ int cluster = cpu_topology[cpu].package_id;
for_each_possible_cpu(cpu1)
- if (cpu_cluster(&cpu_data[cpu1]) == cluster)
+ if (cpu_topology[cpu1].package_id == cluster)
cpumask_set_cpu(cpu1, cpu_map);
}
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 128fc9999c56..e9ed3526bad0 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -127,7 +127,7 @@ static DEFINE_RWLOCK(pmuint_rwlock);
0 : (smp_processor_id() & MIPS_CPUID_TO_COUNTER_MASK))
#else
#define vpe_id() (cpu_has_mipsmt_pertccounters ? \
- 0 : cpu_vpe_id(¤t_cpu_data))
+ 0 : cpu_vpe_id(smp_processor_id()))
#endif
/* Copied from op_model_mipsxx.c */
@@ -343,7 +343,7 @@ static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
*/
cpu = (event->cpu >= 0) ? event->cpu : smp_processor_id();
- ctrl = M_PERFCTL_VPEID(cpu_vpe_id(&cpu_data[cpu]));
+ ctrl = M_PERFCTL_VPEID(cpu_vpe_id(smp_processor_id()));
ctrl |= M_TC_EN_VPE;
cpuc->saved_ctrl[idx] |= ctrl;
pr_debug("Enabling perf counter for CPU%d\n", cpu);
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index f8d36710cd58..e8795b262ca2 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -138,14 +138,14 @@ static int show_cpuinfo(struct seq_file *m, void *v)
cpu_data[n].srsets);
seq_printf(m, "kscratch registers\t: %d\n",
hweight8(cpu_data[n].kscratch_mask));
- seq_printf(m, "package\t\t\t: %d\n", cpu_data[n].package);
- seq_printf(m, "core\t\t\t: %d\n", cpu_core(&cpu_data[n]));
+ seq_printf(m, "package\t\t\t: %d\n", cpu_cluster(n));
+ seq_printf(m, "core\t\t\t: %d\n", cpu_core(n));
#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6)
if (cpu_has_mipsmt)
- seq_printf(m, "VPE\t\t\t: %d\n", cpu_vpe_id(&cpu_data[n]));
+ seq_printf(m, "VPE\t\t\t: %d\n", cpu_vpe_id(n));
else if (cpu_has_vp)
- seq_printf(m, "VP\t\t\t: %d\n", cpu_vpe_id(&cpu_data[n]));
+ seq_printf(m, "VP\t\t\t: %d\n", cpu_vpe_id(n));
#endif
sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 36a311348739..851559ef0bc3 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -547,7 +547,7 @@ static inline int has_valid_asid(const struct mm_struct *mm, unsigned int type)
if (cpu_has_mmid)
return cpu_context(0, mm) != 0;
- /* cpu_sibling_map[] undeclared when !CONFIG_SMP */
+ /* topology_sibling_cpumask undeclared when !CONFIG_SMP */
#ifdef CONFIG_SMP
/*
* If r4k_on_each_cpu does SMP calls, it does them to a single VPE in
@@ -555,7 +555,7 @@ static inline int has_valid_asid(const struct mm_struct *mm, unsigned int type)
* Otherwise we need to worry about all present CPUs.
*/
if (r4k_op_needs_ipi(type))
- mask = &cpu_sibling_map[smp_processor_id()];
+ mask = topology_sibling_cpumask(smp_processor_id());
#endif
for_each_cpu(i, mask)
if (cpu_context(i, mm))
diff --git a/arch/mips/mm/context.c b/arch/mips/mm/context.c
index b25564090939..ad2d8b7f464b 100644
--- a/arch/mips/mm/context.c
+++ b/arch/mips/mm/context.c
@@ -241,12 +241,12 @@ void check_switch_mmu_context(struct mm_struct *mm)
* increase then we need to invalidate any TLB entries for our MMID
* that we might otherwise pick up from a sibling.
*
- * We ifdef on CONFIG_SMP because cpu_sibling_map isn't defined in
+ * We ifdef on CONFIG_SMP because topology_sibling_cpumask isn't defined in
* CONFIG_SMP=n kernels.
*/
#ifdef CONFIG_SMP
if (cpu_has_shared_ftlb_entries &&
- cpumask_intersects(&tlb_flush_pending, &cpu_sibling_map[cpu])) {
+ cpumask_intersects(&tlb_flush_pending, topology_sibling_cpumask(cpu))) {
/* Ensure we operate on the new MMID */
mtc0_tlbw_hazard();
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index a537bf98912c..0129dfcf5d55 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -37,9 +37,9 @@ static int perfcount_irq;
#ifdef CONFIG_MIPS_MT_SMP
#define WHAT (MIPS_PERFCTRL_MT_EN_VPE | \
- M_PERFCTL_VPEID(cpu_vpe_id(¤t_cpu_data)))
+ M_PERFCTL_VPEID(cpu_vpe_id(smp_processor_id())))
#define vpe_id() (cpu_has_mipsmt_pertccounters ? \
- 0 : cpu_vpe_id(¤t_cpu_data))
+ 0 : cpu_vpe_id(smp_processor_id()))
/*
* The number of bits to shift to convert between counters per core and
--
2.26.0.rc2
Change the parameter of get/set topology ID functions from cpudata
to cpuid.
Also adjust include relationship to prevent conflictions.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/include/asm/mips-cm.h | 9 ++++---
arch/mips/include/asm/mips-cps.h | 2 ++
arch/mips/include/asm/smp-ops.h | 2 --
arch/mips/kernel/mips-cm.c | 4 ++--
arch/mips/kernel/mips-cpc.c | 4 ++--
arch/mips/kernel/pm-cps.c | 12 +++++-----
arch/mips/kernel/setup.c | 1 +
arch/mips/kernel/smp-cmp.c | 5 ++--
arch/mips/kernel/smp-cps.c | 41 ++++++++++++++++----------------
arch/mips/kernel/smp-mt.c | 3 ++-
10 files changed, 42 insertions(+), 41 deletions(-)
diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
index aeae2effa123..6bab8f485bcd 100644
--- a/arch/mips/include/asm/mips-cm.h
+++ b/arch/mips/include/asm/mips-cm.h
@@ -395,8 +395,8 @@ static inline unsigned int mips_cm_max_vp_width(void)
*/
static inline unsigned int mips_cm_vp_id(unsigned int cpu)
{
- unsigned int core = cpu_core(&cpu_data[cpu]);
- unsigned int vp = cpu_vpe_id(&cpu_data[cpu]);
+ unsigned int core = cpu_core(cpu);
+ unsigned int vp = cpu_vpe_id(cpu);
return (core * mips_cm_max_vp_width()) + vp;
}
@@ -451,9 +451,8 @@ static inline void mips_cm_unlock_other(void) { }
*/
static inline void mips_cm_lock_other_cpu(unsigned int cpu, unsigned int block)
{
- struct cpuinfo_mips *d = &cpu_data[cpu];
-
- mips_cm_lock_other(cpu_cluster(d), cpu_core(d), cpu_vpe_id(d), block);
+ mips_cm_lock_other(cpu_cluster(cpu), cpu_core(cpu),
+ cpu_vpe_id(cpu), block);
}
#endif /* __MIPS_ASM_MIPS_CM_H__ */
diff --git a/arch/mips/include/asm/mips-cps.h b/arch/mips/include/asm/mips-cps.h
index fd43d876892e..340e367fcf07 100644
--- a/arch/mips/include/asm/mips-cps.h
+++ b/arch/mips/include/asm/mips-cps.h
@@ -9,6 +9,8 @@
#include <linux/io.h>
#include <linux/types.h>
+#include <linux/smp.h>
+#include <asm/topology.h>
extern unsigned long __cps_access_bad_size(void)
__compiletime_error("Bad size for CPS accessor");
diff --git a/arch/mips/include/asm/smp-ops.h b/arch/mips/include/asm/smp-ops.h
index 65618ff1280c..a58f5b019eb7 100644
--- a/arch/mips/include/asm/smp-ops.h
+++ b/arch/mips/include/asm/smp-ops.h
@@ -13,8 +13,6 @@
#include <linux/errno.h>
-#include <asm/mips-cps.h>
-
#ifdef CONFIG_SMP
#include <linux/cpumask.h>
diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c
index cdb93ed91cde..7dd3b6fd9c1c 100644
--- a/arch/mips/kernel/mips-cm.c
+++ b/arch/mips/kernel/mips-cm.c
@@ -295,7 +295,7 @@ void mips_cm_lock_other(unsigned int cluster, unsigned int core,
* CM 2.5 & older, so have to ensure other VP(E)s don't
* race with us.
*/
- curr_core = cpu_core(¤t_cpu_data);
+ curr_core = cpu_core(smp_processor_id());
spin_lock_irqsave(&per_cpu(cm_core_lock, curr_core),
per_cpu(cm_core_lock_flags, curr_core));
@@ -316,7 +316,7 @@ void mips_cm_unlock_other(void)
unsigned int curr_core;
if (mips_cm_revision() < CM_REV_CM3) {
- curr_core = cpu_core(¤t_cpu_data);
+ curr_core = cpu_core(smp_processor_id());
spin_unlock_irqrestore(&per_cpu(cm_core_lock, curr_core),
per_cpu(cm_core_lock_flags, curr_core));
} else {
diff --git a/arch/mips/kernel/mips-cpc.c b/arch/mips/kernel/mips-cpc.c
index 8d2535123f11..13f6f813e82a 100644
--- a/arch/mips/kernel/mips-cpc.c
+++ b/arch/mips/kernel/mips-cpc.c
@@ -94,7 +94,7 @@ void mips_cpc_lock_other(unsigned int core)
return;
preempt_disable();
- curr_core = cpu_core(¤t_cpu_data);
+ curr_core = cpu_core(smp_processor_id());
spin_lock_irqsave(&per_cpu(cpc_core_lock, curr_core),
per_cpu(cpc_core_lock_flags, curr_core));
write_cpc_cl_other(core << __ffs(CPC_Cx_OTHER_CORENUM));
@@ -114,7 +114,7 @@ void mips_cpc_unlock_other(void)
/* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */
return;
- curr_core = cpu_core(¤t_cpu_data);
+ curr_core = cpu_core(smp_processor_id());
spin_unlock_irqrestore(&per_cpu(cpc_core_lock, curr_core),
per_cpu(cpc_core_lock_flags, curr_core));
preempt_enable();
diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c
index 9bf60d7d44d3..cd4401bc79d2 100644
--- a/arch/mips/kernel/pm-cps.c
+++ b/arch/mips/kernel/pm-cps.c
@@ -110,7 +110,7 @@ static void coupled_barrier(atomic_t *a, unsigned online)
int cps_pm_enter_state(enum cps_pm_state state)
{
unsigned cpu = smp_processor_id();
- unsigned core = cpu_core(¤t_cpu_data);
+ unsigned int core = cpu_core(cpu);
unsigned online, left;
cpumask_t *coupled_mask = this_cpu_ptr(&online_coupled);
u32 *core_ready_count, *nc_core_ready_count;
@@ -128,7 +128,7 @@ int cps_pm_enter_state(enum cps_pm_state state)
#if defined(CONFIG_MIPS_MT) || defined(CONFIG_CPU_MIPSR6)
if (cpu_online(cpu)) {
cpumask_and(coupled_mask, cpu_online_mask,
- &cpu_sibling_map[cpu]);
+ topology_sibling_cpumask(cpu));
online = cpumask_weight(coupled_mask);
cpumask_clear_cpu(cpu, coupled_mask);
} else
@@ -145,7 +145,7 @@ int cps_pm_enter_state(enum cps_pm_state state)
return -EINVAL;
core_cfg = &mips_cps_core_bootcfg[core];
- vpe_cfg = &core_cfg->vpe_config[cpu_vpe_id(¤t_cpu_data)];
+ vpe_cfg = &core_cfg->vpe_config[cpu_vpe_id(smp_processor_id())];
vpe_cfg->pc = (unsigned long)mips_cps_pm_restore;
vpe_cfg->gp = (unsigned long)current_thread_info();
vpe_cfg->sp = 0;
@@ -444,7 +444,7 @@ static void *cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
/* Halt the VP via the CPC VP_STOP register */
unsigned int vpe_id;
- vpe_id = cpu_vpe_id(&cpu_data[cpu]);
+ vpe_id = cpu_vpe_id(cpu);
uasm_i_addiu(&p, t0, zero, 1 << vpe_id);
UASM_i_LA(&p, t1, (long)addr_cpc_cl_vp_stop());
uasm_i_sw(&p, t0, 0, t1);
@@ -482,7 +482,7 @@ static void *cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
* defined by the interAptiv & proAptiv SUMs as ensuring that the
* operation resulting from the preceding store is complete.
*/
- uasm_i_addiu(&p, t0, zero, 1 << cpu_core(&cpu_data[cpu]));
+ uasm_i_addiu(&p, t0, zero, 1 << cpu_core(cpu));
uasm_i_sw(&p, t0, 0, r_pcohctl);
uasm_i_lw(&p, t0, 0, r_pcohctl);
@@ -636,7 +636,7 @@ static void *cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
static int cps_pm_online_cpu(unsigned int cpu)
{
enum cps_pm_state state;
- unsigned core = cpu_core(&cpu_data[cpu]);
+ unsigned int core = cpu_core(cpu);
void *entry_fn, *core_rc;
for (state = CPS_PM_NC_WAIT; state < CPS_PM_STATE_COUNT; state++) {
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index b9fefc5dc702..92739120cb09 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -38,6 +38,7 @@
#include <asm/cpu.h>
#include <asm/debug.h>
#include <asm/dma-coherence.h>
+#include <asm/mips-cps.h>
#include <asm/sections.h>
#include <asm/setup.h>
#include <asm/smp-ops.h>
diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c
index 76f5824cdb00..9f775195fe0d 100644
--- a/arch/mips/kernel/smp-cmp.c
+++ b/arch/mips/kernel/smp-cmp.c
@@ -21,6 +21,7 @@
#include <asm/hardirq.h>
#include <asm/mmu_context.h>
#include <asm/smp.h>
+#include <asm/mips-cps.h>
#include <asm/time.h>
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
@@ -29,8 +30,6 @@
static void cmp_init_secondary(void)
{
- struct cpuinfo_mips *c __maybe_unused = ¤t_cpu_data;
-
/* Assume GIC is present */
change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 |
STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7);
@@ -39,7 +38,7 @@ static void cmp_init_secondary(void)
#ifdef CONFIG_MIPS_MT_SMP
if (cpu_has_mipsmt)
- cpu_set_vpe_id(c, (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
+ cpu_set_vpe_id(smp_processor_id(), (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
TCBIND_CURVPE);
#endif
}
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index dbb3f1fc71ab..cf5875487d71 100644
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -71,9 +71,10 @@ static void __init cps_smp_setup(void)
smp_num_siblings = core_vpes;
for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
- cpu_set_cluster(&cpu_data[nvpes + v], cl);
- cpu_set_core(&cpu_data[nvpes + v], c);
- cpu_set_vpe_id(&cpu_data[nvpes + v], v);
+ cpu_set_cluster(nvpes + v, cl);
+ cpu_set_core(nvpes + v, c);
+ cpu_set_vpe_id(nvpes + v, v);
+ update_siblings_masks(nvpes + v);
}
nvpes += core_vpes;
@@ -85,8 +86,8 @@ static void __init cps_smp_setup(void)
/* Indicate present CPUs (CPU being synonymous with VPE) */
for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
- set_cpu_possible(v, cpu_cluster(&cpu_data[v]) == 0);
- set_cpu_present(v, cpu_cluster(&cpu_data[v]) == 0);
+ set_cpu_possible(v, cpu_cluster(v) == 0);
+ set_cpu_present(v, cpu_cluster(v) == 0);
__cpu_number_map[v] = v;
__cpu_logical_map[v] = v;
}
@@ -190,8 +191,8 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
}
/* Mark this CPU as booted */
- atomic_set(&mips_cps_core_bootcfg[cpu_core(¤t_cpu_data)].vpe_mask,
- 1 << cpu_vpe_id(¤t_cpu_data));
+ atomic_set(&mips_cps_core_bootcfg[cpu_core(smp_processor_id())].vpe_mask,
+ 1 << cpu_vpe_id(smp_processor_id()));
return;
err_out:
@@ -285,16 +286,16 @@ static void boot_core(unsigned int core, unsigned int vpe_id)
static void remote_vpe_boot(void *dummy)
{
- unsigned core = cpu_core(¤t_cpu_data);
+ unsigned int core = cpu_core(smp_processor_id());
struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
- mips_cps_boot_vpes(core_cfg, cpu_vpe_id(¤t_cpu_data));
+ mips_cps_boot_vpes(core_cfg, cpu_vpe_id(smp_processor_id()));
}
static int cps_boot_secondary(int cpu, struct task_struct *idle)
{
- unsigned core = cpu_core(&cpu_data[cpu]);
- unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
+ unsigned int core = cpu_core(cpu);
+ unsigned int vpe_id = cpu_vpe_id(cpu);
struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
unsigned long core_entry;
@@ -302,14 +303,14 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle)
int err;
/* We don't yet support booting CPUs in other clusters */
- if (cpu_cluster(&cpu_data[cpu]) != cpu_cluster(&raw_current_cpu_data))
+ if (cpu_cluster(cpu) != cpu_cluster(smp_processor_id()))
return -ENOSYS;
vpe_cfg->pc = (unsigned long)&smp_bootstrap;
vpe_cfg->sp = __KSTK_TOS(idle);
vpe_cfg->gp = (unsigned long)task_thread_info(idle);
- atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);
+ atomic_or(1 << cpu_vpe_id(cpu), &core_cfg->vpe_mask);
preempt_disable();
@@ -406,10 +407,10 @@ static void cps_shutdown_this_cpu(enum cpu_death death)
unsigned int cpu, core, vpe_id;
cpu = smp_processor_id();
- core = cpu_core(&cpu_data[cpu]);
+ core = cpu_core(cpu);
if (death == CPU_DEATH_HALT) {
- vpe_id = cpu_vpe_id(&cpu_data[cpu]);
+ vpe_id = cpu_vpe_id(cpu);
pr_debug("Halting core %d VP%d\n", core, vpe_id);
if (cpu_has_mipsmt) {
@@ -456,8 +457,8 @@ static int cps_cpu_disable(void)
if (!cps_pm_support_state(CPS_PM_POWER_GATED))
return -EINVAL;
- core_cfg = &mips_cps_core_bootcfg[cpu_core(¤t_cpu_data)];
- atomic_sub(1 << cpu_vpe_id(¤t_cpu_data), &core_cfg->vpe_mask);
+ core_cfg = &mips_cps_core_bootcfg[cpu_core(smp_processor_id())];
+ atomic_sub(1 << cpu_vpe_id(smp_processor_id()), &core_cfg->vpe_mask);
smp_mb__after_atomic();
set_cpu_online(cpu, false);
calculate_cpu_foreign_map();
@@ -506,7 +507,7 @@ void play_dead(void)
static void wait_for_sibling_halt(void *ptr_cpu)
{
unsigned cpu = (unsigned long)ptr_cpu;
- unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
+ unsigned int vpe_id = cpu_vpe_id(cpu);
unsigned halted;
unsigned long flags;
@@ -520,8 +521,8 @@ static void wait_for_sibling_halt(void *ptr_cpu)
static void cps_cpu_die(unsigned int cpu)
{
- unsigned core = cpu_core(&cpu_data[cpu]);
- unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]);
+ unsigned int core = cpu_core(cpu);
+ unsigned int vpe_id = cpu_vpe_id(cpu);
ktime_t fail_time;
unsigned stat;
int err;
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 5f04a0141068..5eb31b8c8ea0 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -21,6 +21,7 @@
#include <asm/hardirq.h>
#include <asm/mmu_context.h>
#include <asm/time.h>
+#include <asm/topology.h>
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/mips_mt.h>
@@ -72,7 +73,7 @@ static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0,
if (tc != 0)
smvp_copy_vpe_config();
- cpu_set_vpe_id(&cpu_data[ncpu], tc);
+ cpu_set_vpe_id(ncpu, tc);
return ncpu;
}
--
2.26.0.rc2
Change the parameter of cpu_set_core from cpudata to cpuid.
Also set cluster id for bmips as it have different method to probe
actual hwid of CPU, and smp_store_cpuinfo is using cluster id to
determine if we should probe topology info again.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/kernel/smp-bmips.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index 9058e9dcf080..c40bb37eab38 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -247,7 +247,8 @@ static void bmips_init_secondary(void)
break;
case CPU_BMIPS5000:
write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
- cpu_set_core(¤t_cpu_data, (read_c0_brcm_config() >> 25) & 3);
+ cpu_set_core(smp_processor_id(), (read_c0_brcm_config() >> 25) & 3);
+ cpu_set_cluster(smp_processor_id(), 0);
break;
}
}
--
2.26.0.rc2
On 08/04/20 12:34, Jiaxun Yang wrote:
> For MIPS platform, when topology isn't probed by DeviceTree,
> possible_cpu might be empty when calling init_cpu_topology,
> that may result cpu_topology not fully reseted for all CPUs.
> So here we can reset all cpus instead of possible cpus.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> ---
> drivers/base/arch_topology.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c
> index 9c2405d08dae..3398b7ac7dfb 100644
> --- a/drivers/base/arch_topology.c
> +++ b/drivers/base/arch_topology.c
> @@ -542,7 +542,7 @@ void __init reset_cpu_topology(void)
> {
> unsigned int cpu;
>
> - for_each_possible_cpu(cpu) {
> + for (cpu = 0; cpu < NR_CPUS; cpu++) {
Hmph, kind of a shame but if you really have to do it then perhaps you
should go with ARRAY_SIZE(cpu_topology) instead.
> struct cpu_topology *cpu_topo = &cpu_topology[cpu];
>
> cpu_topo->thread_id = -1;
(+ Dietmar)
On 08/04/20 12:34, Jiaxun Yang wrote:
> @@ -275,7 +224,64 @@ static void parsing_done_workfn(struct work_struct *work)
> core_initcall(free_raw_capacity);
> #endif
>
> -#if defined(CONFIG_ARM64) || defined(CONFIG_RISCV)
> +#if defined(CONFIG_OF) && !defined(CONFIG_ARM)
> +#if defined(CONFIG_COMMON_CLK)
> +bool __init topology_parse_cpu_capacity(struct device_node *cpu_node, int cpu)
We actually use this for arm:
arch/arm/kernel/topology.o: In function `init_cpu_topology':
topology.c:(.init.text+0xc8): undefined reference to `topology_parse_cpu_capacity'
So that doesn't work. TBH I'd be quite happy to see the ifdef(ARCH) go away
entirely; it's shame that arm is using some of those names already. I think
some of that is due to the CPU efficiency faff, if we can't get rid of it /
align those then perhaps the next best thing is to make some of those
definitions __weak.
> +{
> + struct clk *cpu_clk;
> + static bool cap_parsing_failed;
> + int ret;
> + u32 cpu_capacity;
> +
> + if (cap_parsing_failed)
> + return false;
> +
> + ret = of_property_read_u32(cpu_node, "capacity-dmips-mhz",
> + &cpu_capacity);
> + if (!ret) {
> + if (!raw_capacity) {
> + raw_capacity = kcalloc(num_possible_cpus(),
> + sizeof(*raw_capacity),
> + GFP_KERNEL);
> + if (!raw_capacity) {
> + cap_parsing_failed = true;
> + return false;
> + }
> + }
> + raw_capacity[cpu] = cpu_capacity;
> + pr_debug("cpu_capacity: %pOF cpu_capacity=%u (raw)\n",
> + cpu_node, raw_capacity[cpu]);
> +
> + /*
> + * Update freq_factor for calculating early boot cpu capacities.
> + * For non-clk CPU DVFS mechanism, there's no way to get the
> + * frequency value now, assuming they are running at the same
> + * frequency (by keeping the initial freq_factor value).
> + */
> + cpu_clk = of_clk_get(cpu_node, 0);
> + if (!PTR_ERR_OR_ZERO(cpu_clk)) {
> + per_cpu(freq_factor, cpu) =
> + clk_get_rate(cpu_clk) / 1000;
> + clk_put(cpu_clk);
> + }
> + } else {
> + if (raw_capacity) {
> + pr_err("cpu_capacity: missing %pOF raw capacity\n",
> + cpu_node);
> + pr_err("cpu_capacity: partial information: fallback to 1024 for all CPUs\n");
> + }
> + cap_parsing_failed = true;
> + free_raw_capacity();
> + }
> +
> + return !ret;
> +}
> +#else
> +bool __init topology_parse_cpu_capacity(struct device_node *cpu_node, int cpu)
> +{
> + return false;
> +}
> +#endif /* CONFIG_COMMON_CLK */
> /*
> * This function returns the logic cpu number of the node.
> * There are basically three kinds of return values:
On Wed, Apr 08, 2020 at 08:59:54PM +0800, Jiaxun Yang wrote:
> Somehow changes in topology messed up headers.
> So just add necessary headers to make it compile again.
Please avoid aftermath build fixes because it breaks bisection.
Each commit should be buildable, so this changes should go into the patches
that actually require them.
> Signed-off-by: Jiaxun Yang <[email protected]>
> ---
> arch/mips/include/asm/mach-ip27/mmzone.h | 2 ++
> arch/mips/include/asm/mach-ip27/topology.h | 2 ++
> arch/mips/include/asm/sn/addrs.h | 1 +
> 3 files changed, 5 insertions(+)
>
> diff --git a/arch/mips/include/asm/mach-ip27/mmzone.h b/arch/mips/include/asm/mach-ip27/mmzone.h
> index 08c36e50a860..e0a53b97b4a8 100644
> --- a/arch/mips/include/asm/mach-ip27/mmzone.h
> +++ b/arch/mips/include/asm/mach-ip27/mmzone.h
> @@ -2,6 +2,8 @@
> #ifndef _ASM_MACH_MMZONE_H
> #define _ASM_MACH_MMZONE_H
>
> +#include <linux/mmzone.h>
> +
> #include <asm/sn/addrs.h>
> #include <asm/sn/arch.h>
> #include <asm/sn/agent.h>
> diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h
> index d66cc53feab8..601e350908f7 100644
> --- a/arch/mips/include/asm/mach-ip27/topology.h
> +++ b/arch/mips/include/asm/mach-ip27/topology.h
> @@ -2,6 +2,8 @@
> #ifndef _ASM_MACH_TOPOLOGY_H
> #define _ASM_MACH_TOPOLOGY_H 1
>
> +#include <linux/numa.h>
> +
> #include <asm/sn/types.h>
> #include <asm/mmzone.h>
>
> diff --git a/arch/mips/include/asm/sn/addrs.h b/arch/mips/include/asm/sn/addrs.h
> index 837d23e24976..1d3945ef2ca4 100644
> --- a/arch/mips/include/asm/sn/addrs.h
> +++ b/arch/mips/include/asm/sn/addrs.h
> @@ -13,6 +13,7 @@
> #ifndef __ASSEMBLY__
> #include <linux/smp.h>
> #include <linux/types.h>
> +#include <asm/io.h>
> #endif /* !__ASSEMBLY__ */
>
> #include <asm/addrspace.h>
> --
> 2.26.0.rc2
>
>
--
Sincerely yours,
Mike.
On Thu, 9 Apr 2020 12:19:22 +0300
Mike Rapoport <[email protected]> wrote:
> On Wed, Apr 08, 2020 at 08:59:54PM +0800, Jiaxun Yang wrote:
> > Somehow changes in topology messed up headers.
> > So just add necessary headers to make it compile again.
>
> Please avoid aftermath build fixes because it breaks bisection.
> Each commit should be buildable, so this changes should go into the
> patches that actually require them.
I'd love to but for that I'll have to squash patch #5~#12 into a single
patch. T thought it's to big and touching too many files.
Is that acceptable?
Thanks.
>
> > Signed-off-by: Jiaxun Yang <[email protected]>
> > ---
--
Jiaxun Yang
On Thu, Apr 09, 2020 at 05:38:35PM +0800, Jiaxun Yang wrote:
> On Thu, 9 Apr 2020 12:19:22 +0300
> Mike Rapoport <[email protected]> wrote:
>
> > On Wed, Apr 08, 2020 at 08:59:54PM +0800, Jiaxun Yang wrote:
> > > Somehow changes in topology messed up headers.
> > > So just add necessary headers to make it compile again.
> >
> > Please avoid aftermath build fixes because it breaks bisection.
> > Each commit should be buildable, so this changes should go into the
> > patches that actually require them.
>
> I'd love to but for that I'll have to squash patch #5~#12 into a single
> patch. T thought it's to big and touching too many files.
>
> Is that acceptable?
If I understand correctly, the patches #5-#12 replace custom MIPS
implementation of CPU topology with a generic one, so making them a single
patch could be Ok as it is single logical change.
But I'm not sure it is required. Judging by diffstat, my guess would be
that patch #5 breaks ip27 builds. If that's true, only patch #5 should be
redacted
> Thanks.
> >
> > > Signed-off-by: Jiaxun Yang <[email protected]>
> > > ---
> --
> Jiaxun Yang
>
>
--
Sincerely yours,
Mike.
On Wed, Apr 08, 2020 at 07:34:13PM +0800, Jiaxun Yang wrote:
> Simply drop unnecessary archtecture limitions and add dummy
> function for platforms without OF/COMMON_CLK support.
> Also exclude functions for arm that existed in platform code.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> ---
> drivers/base/arch_topology.c | 121 +++++++++++++++++++----------------
> 1 file changed, 66 insertions(+), 55 deletions(-)
>
> diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c
> index 4d0a0038b476..9c2405d08dae 100644
> --- a/drivers/base/arch_topology.c
> +++ b/drivers/base/arch_topology.c
> @@ -143,57 +143,6 @@ void topology_normalize_cpu_scale(void)
> }
> }
>
[...]
> #ifdef CONFIG_CPU_FREQ
> static cpumask_var_t cpus_to_visit;
> static void parsing_done_workfn(struct work_struct *work);
> @@ -275,7 +224,64 @@ static void parsing_done_workfn(struct work_struct *work)
> core_initcall(free_raw_capacity);
> #endif
>
> -#if defined(CONFIG_ARM64) || defined(CONFIG_RISCV)
> +#if defined(CONFIG_OF) && !defined(CONFIG_ARM)
topology_parse_cpu_capacity is used even on ARM, so you can't do the above.
> +#if defined(CONFIG_COMMON_CLK)
Not required, it will either fail in of_clk_get or clk_get_rate if the
platform doesn't support.
[...]
> -#if defined(CONFIG_ARM64) || defined(CONFIG_RISCV)
> +#if !defined(CONFIG_ARM)
I think we need to see if we can merge ARM support too or rename these
functions in ARM. Since we wanted to keep changes minimum when we moved
ARM64 and RISCV to common, we skipped ARM. May be worth giving it a shot ?
--
Regards,
Sudeep
On Wed, Apr 08, 2020 at 07:34:14PM +0800, Jiaxun Yang wrote:
> For MIPS platform, when topology isn't probed by DeviceTree,
> possible_cpu might be empty when calling init_cpu_topology,
> that may result cpu_topology not fully reseted for all CPUs.
> So here we can reset all cpus instead of possible cpus.
>
Why not set all CPUs upto NR_CPUS in possible cpus_mask as
default to begin with ?
--
Regards,
Sudeep
On Wed, Apr 08, 2020 at 07:34:15PM +0800, Jiaxun Yang wrote:
> Previously, MIPS is using self-defined "globalnumber" in struct
> mips_cpuinfo to store topology information. However, it's not friendly
> to DeviceTree based systems and lack of cpu_capacity related feature
> which can take advantage of multi-cluster system.
>
> Here, we enabled arch_topology for MIPS and adapted some functions
> to fit arch_topology structure.
> Also, we implmented smp_store_cpu_info to probe CPU's topology information
> by "globalnumber" registers in VP ASE or Ebase.CPUNum for legacy systems.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> ---
> arch/mips/Kconfig | 1 +
> arch/mips/include/asm/cpu-info.h | 49 ----------------------------
> arch/mips/include/asm/smp.h | 2 --
> arch/mips/include/asm/topology.h | 48 +++++++++++++++++++++++++---
> arch/mips/kernel/cpu-probe.c | 43 -------------------------
> arch/mips/kernel/setup.c | 1 +
> arch/mips/kernel/smp.c | 55 ++++----------------------------
> arch/mips/kernel/topology.c | 42 ++++++++++++++++++++++++
> 8 files changed, 93 insertions(+), 148 deletions(-)
>
[...]
> diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
> index 8a418783a6bb..b9fefc5dc702 100644
> --- a/arch/mips/kernel/setup.c
> +++ b/arch/mips/kernel/setup.c
> @@ -784,6 +784,7 @@ void __init setup_arch(char **cmdline_p)
> dmi_setup();
>
> resource_init();
> + init_cpu_topology();
> plat_smp_setup();
>
Continuing my reply on previous patch, I see possible_cpu_mask being
set up in plat_smp_setup. Why not reverse the order above. Further I see
that the logical->physical CPU mapping is done in plat_smp_setup which
is required to store/save any topology information.
--
Regards,
Sudeep
This set mainly added DeviceTree based CPU probe support and reworked
topology handling for MIPS. In order to prepare for pure DeviceTree
boot for Loongson64. It can also convinient Yanjie's Inegnic jz4780/X2000
SMP/SMT support.
I've done build test for bmips, nlm, ip27 and boot test for malta with
34Kf, I6400 in QEMU, Loongson64 on a Loongson-3B1500 real machine.
Thanks.
v2:
- Fixes
Jiaxun Yang (11):
MIPS: setup: Drop prefill_possible_map
MIPS: prom: Add helper to parse CPU node in dt
arch_topology: Make it avilable for MIPS
arch_topology: Reset all cpus in reset_cpu_topology
MIPS: Switch to arch_topology
MIPS: Kernel: Switch to new topology interface
MIPS: CPS & MT: Switch to new topology interface
irqchip: mips-cpu: Switch to new topology interface
MIPS: bmips: Switch to new topology interface
MIPS: nlm: Switch to new topology interface
MIPS: Loongson64: Switch to new topology interface
arch/mips/Kconfig | 1 +
arch/mips/include/asm/cpu-info.h | 49 --------
arch/mips/include/asm/mach-ip27/mmzone.h | 2 +
arch/mips/include/asm/mach-ip27/topology.h | 2 +
.../include/asm/mach-loongson64/topology.h | 2 +
arch/mips/include/asm/mips-cm.h | 9 +-
arch/mips/include/asm/mips-cps.h | 2 +
arch/mips/include/asm/prom.h | 6 +
arch/mips/include/asm/smp-ops.h | 2 -
arch/mips/include/asm/smp.h | 2 -
arch/mips/include/asm/sn/addrs.h | 1 +
arch/mips/include/asm/topology.h | 68 +++++++++-
arch/mips/kernel/cacheinfo.c | 19 +--
arch/mips/kernel/cpu-probe.c | 43 -------
arch/mips/kernel/mips-cm.c | 4 +-
arch/mips/kernel/mips-cpc.c | 4 +-
arch/mips/kernel/perf_event_mipsxx.c | 4 +-
arch/mips/kernel/pm-cps.c | 12 +-
arch/mips/kernel/proc.c | 8 +-
arch/mips/kernel/prom.c | 97 ++++++++++++++
arch/mips/kernel/setup.c | 22 +---
arch/mips/kernel/smp-bmips.c | 3 +-
arch/mips/kernel/smp-cmp.c | 5 +-
arch/mips/kernel/smp-cps.c | 41 +++---
arch/mips/kernel/smp-mt.c | 3 +-
arch/mips/kernel/smp.c | 55 +-------
arch/mips/kernel/topology.c | 42 +++++++
arch/mips/loongson64/smp.c | 20 +--
arch/mips/mm/c-r4k.c | 4 +-
arch/mips/mm/context.c | 4 +-
arch/mips/netlogic/common/smp.c | 4 +-
arch/mips/oprofile/op_model_mipsxx.c | 4 +-
drivers/base/arch_topology.c | 118 +++++++++---------
drivers/cpuidle/cpuidle-cps.c | 3 +-
drivers/irqchip/irq-mips-cpu.c | 2 +-
35 files changed, 361 insertions(+), 306 deletions(-)
--
2.26.0.rc2
Mostly identical with arm one. The only difference is that we allow
to mark a CPU Node as status = "disabled" in dt, which means the core
is physicaly present, but not possible for the kernel. It will occupy
a bit in cpumask as well.
Signed-off-by: Jiaxun Yang <[email protected]>
--
v2: Exclude non-SMP config.
---
arch/mips/include/asm/prom.h | 6 +++
arch/mips/kernel/prom.c | 97 ++++++++++++++++++++++++++++++++++++
2 files changed, 103 insertions(+)
diff --git a/arch/mips/include/asm/prom.h b/arch/mips/include/asm/prom.h
index c42e07671934..84802c70e426 100644
--- a/arch/mips/include/asm/prom.h
+++ b/arch/mips/include/asm/prom.h
@@ -24,6 +24,12 @@ extern int __dt_register_buses(const char *bus0, const char *bus1);
static inline void device_tree_init(void) { }
#endif /* CONFIG_OF */
+#if defined(CONFIG_OF) && defined(CONFIG_SMP)
+extern void mips_dt_init_cpu_maps(void);
+#else
+static inline void mips_dt_init_cpu_maps(void) { }
+#endif
+
extern char *mips_get_machine_name(void);
extern void mips_set_machine_name(const char *name);
diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c
index 9e50dc8df2f6..deb5cc0a0eb5 100644
--- a/arch/mips/kernel/prom.c
+++ b/arch/mips/kernel/prom.c
@@ -89,4 +89,101 @@ int __init __dt_register_buses(const char *bus0, const char *bus1)
return 0;
}
+#ifdef CONFIG_SMP
+void __init mips_dt_init_cpu_maps(void)
+{
+ struct device_node *cpu, *cpus;
+ u32 i, j, cpuidx = 1;
+ u32 cpunum;
+ u32 tmp_map[NR_CPUS] = { [0 ... NR_CPUS-1] = U32_MAX };
+ bool cpu_possible[NR_CPUS] = { [0 ... NR_CPUS-1] = false };
+ bool bootcpu_valid = false;
+
+ cpus = of_find_node_by_path("/cpus");
+ if (!cpus)
+ return;
+
+ if (cpu_has_mips_r2_r6)
+ cpunum = get_ebase_cpunum();
+ else
+ cpunum = 0; /* For legacy system we assume boot from CPU 0 */
+
+ for_each_of_cpu_node(cpu) {
+ u32 hwid;
+
+ pr_debug(" * %pOF...\n", cpu);
+ /*
+ * A device tree containing CPU nodes with missing "reg"
+ * properties is considered invalid to build the
+ * cpu_logical_map.
+ */
+
+ if (of_property_read_u32(cpu, "reg", &hwid)) {
+ pr_debug(" * %pOF missing reg property\n", cpu);
+ of_node_put(cpu);
+ return;
+ }
+
+ /*
+ * Duplicate hwid are a recipe for disaster.
+ * Scan all initialized entries and check for
+ * duplicates. If any is found just bail out.
+ */
+ for (j = 0; j < cpuidx; j++)
+ if (WARN(tmp_map[j] == hwid,
+ "Duplicate /cpu reg properties in the DT\n")) {
+ of_node_put(cpu);
+ return;
+ }
+
+ /*
+ * Build a stashed array of hwid values. Numbering scheme
+ * requires that if detected the boot CPU must be assigned
+ * logical id 0. Other CPUs get sequential indexes starting
+ * from 1. If a CPU node with a reg property matching the
+ * boot CPU hwid is detected, this is recorded so that the
+ * logical map built from DT is validated.
+ */
+ if (hwid == cpunum) {
+ i = 0;
+ if (of_device_is_available(cpu))
+ bootcpu_valid = true;
+ } else {
+ i = cpuidx++;
+ }
+
+ if (WARN(cpuidx > nr_cpu_ids, "DT /cpu %u nodes greater than "
+ "max cores %u, capping them\n",
+ cpuidx, nr_cpu_ids)) {
+ cpuidx = nr_cpu_ids;
+ of_node_put(cpu);
+ break;
+ }
+
+ tmp_map[i] = hwid;
+
+ if (of_device_is_available(cpu))
+ cpu_possible[i] = true;
+ }
+
+ if (!bootcpu_valid) {
+ pr_warn("DT missing boot CPU, fall back to default cpu_logical_map\n");
+ return;
+ }
+
+ init_cpu_possible(cpu_none_mask);
+ init_cpu_present(cpu_none_mask);
+
+ for (i = 0; i < cpuidx; i++) {
+ set_cpu_possible(i, cpu_possible[i]);
+ cpu_logical_map(i) = tmp_map[i];
+ pr_debug("cpu logical map 0x%x\n", cpu_logical_map(i));
+ }
+}
+
+bool arch_match_cpu_phys_id(int cpu, u64 phys_id)
+{
+ return phys_id == cpu_logical_map(cpu);
+}
+#endif /* CONFIG_SMP */
#endif
--
2.26.0.rc2
All the plat_smp_setup are setting up possible cpus in their
platform code. So prefill_possible_map is actually overwriting
platform's setup, which seems unreasonable.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/kernel/setup.c | 20 --------------------
1 file changed, 20 deletions(-)
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 10bef8f78e7c..8a418783a6bb 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -761,25 +761,6 @@ static void __init resource_init(void)
}
}
-#ifdef CONFIG_SMP
-static void __init prefill_possible_map(void)
-{
- int i, possible = num_possible_cpus();
-
- if (possible > nr_cpu_ids)
- possible = nr_cpu_ids;
-
- for (i = 0; i < possible; i++)
- set_cpu_possible(i, true);
- for (; i < NR_CPUS; i++)
- set_cpu_possible(i, false);
-
- nr_cpu_ids = possible;
-}
-#else
-static inline void prefill_possible_map(void) {}
-#endif
-
void __init setup_arch(char **cmdline_p)
{
cpu_probe();
@@ -804,7 +785,6 @@ void __init setup_arch(char **cmdline_p)
resource_init();
plat_smp_setup();
- prefill_possible_map();
cpu_cache_init();
paging_init();
--
2.26.0.rc2
For MIPS platform, when topology isn't probed by DeviceTree,
possible_cpu might be empty when calling init_cpu_topology,
that may result cpu_topology not fully reseted for all CPUs.
So here we can reset all cpus instead of possible cpus.
Signed-off-by: Jiaxun Yang <[email protected]>
--
v2: Use ARRAY_SIZE instead of NR_CPUS.
---
drivers/base/arch_topology.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c
index 13dc4fbf043f..e7912d0a875e 100644
--- a/drivers/base/arch_topology.c
+++ b/drivers/base/arch_topology.c
@@ -536,7 +536,7 @@ void __init reset_cpu_topology(void)
{
unsigned int cpu;
- for_each_possible_cpu(cpu) {
+ for (cpu = 0; cpu < ARRAY_SIZE(cpu_topology); cpu++) {
struct cpu_topology *cpu_topo = &cpu_topology[cpu];
cpu_topo->thread_id = -1;
--
2.26.0.rc2
Simply drop unnecessary archtecture limitions and add dummy
function for platforms without OF support.
As some of the functions are conflicting with Arm's platform
implementations, we mark them as weak.
Signed-off-by: Jiaxun Yang <[email protected]>
--
v2: Use weak instead of ifdef to exclude functions for Arm.
---
drivers/base/arch_topology.c | 116 ++++++++++++++++++-----------------
1 file changed, 60 insertions(+), 56 deletions(-)
diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c
index 4d0a0038b476..13dc4fbf043f 100644
--- a/drivers/base/arch_topology.c
+++ b/drivers/base/arch_topology.c
@@ -143,57 +143,6 @@ void topology_normalize_cpu_scale(void)
}
}
-bool __init topology_parse_cpu_capacity(struct device_node *cpu_node, int cpu)
-{
- struct clk *cpu_clk;
- static bool cap_parsing_failed;
- int ret;
- u32 cpu_capacity;
-
- if (cap_parsing_failed)
- return false;
-
- ret = of_property_read_u32(cpu_node, "capacity-dmips-mhz",
- &cpu_capacity);
- if (!ret) {
- if (!raw_capacity) {
- raw_capacity = kcalloc(num_possible_cpus(),
- sizeof(*raw_capacity),
- GFP_KERNEL);
- if (!raw_capacity) {
- cap_parsing_failed = true;
- return false;
- }
- }
- raw_capacity[cpu] = cpu_capacity;
- pr_debug("cpu_capacity: %pOF cpu_capacity=%u (raw)\n",
- cpu_node, raw_capacity[cpu]);
-
- /*
- * Update freq_factor for calculating early boot cpu capacities.
- * For non-clk CPU DVFS mechanism, there's no way to get the
- * frequency value now, assuming they are running at the same
- * frequency (by keeping the initial freq_factor value).
- */
- cpu_clk = of_clk_get(cpu_node, 0);
- if (!PTR_ERR_OR_ZERO(cpu_clk)) {
- per_cpu(freq_factor, cpu) =
- clk_get_rate(cpu_clk) / 1000;
- clk_put(cpu_clk);
- }
- } else {
- if (raw_capacity) {
- pr_err("cpu_capacity: missing %pOF raw capacity\n",
- cpu_node);
- pr_err("cpu_capacity: partial information: fallback to 1024 for all CPUs\n");
- }
- cap_parsing_failed = true;
- free_raw_capacity();
- }
-
- return !ret;
-}
-
#ifdef CONFIG_CPU_FREQ
static cpumask_var_t cpus_to_visit;
static void parsing_done_workfn(struct work_struct *work);
@@ -275,7 +224,58 @@ static void parsing_done_workfn(struct work_struct *work)
core_initcall(free_raw_capacity);
#endif
-#if defined(CONFIG_ARM64) || defined(CONFIG_RISCV)
+#if defined(CONFIG_OF)
+bool __init topology_parse_cpu_capacity(struct device_node *cpu_node, int cpu)
+{
+ struct clk *cpu_clk;
+ static bool cap_parsing_failed;
+ int ret;
+ u32 cpu_capacity;
+
+ if (cap_parsing_failed)
+ return false;
+
+ ret = of_property_read_u32(cpu_node, "capacity-dmips-mhz",
+ &cpu_capacity);
+ if (!ret) {
+ if (!raw_capacity) {
+ raw_capacity = kcalloc(num_possible_cpus(),
+ sizeof(*raw_capacity),
+ GFP_KERNEL);
+ if (!raw_capacity) {
+ cap_parsing_failed = true;
+ return false;
+ }
+ }
+ raw_capacity[cpu] = cpu_capacity;
+ pr_debug("cpu_capacity: %pOF cpu_capacity=%u (raw)\n",
+ cpu_node, raw_capacity[cpu]);
+
+ /*
+ * Update freq_factor for calculating early boot cpu capacities.
+ * For non-clk CPU DVFS mechanism, there's no way to get the
+ * frequency value now, assuming they are running at the same
+ * frequency (by keeping the initial freq_factor value).
+ */
+ cpu_clk = of_clk_get(cpu_node, 0);
+ if (!PTR_ERR_OR_ZERO(cpu_clk)) {
+ per_cpu(freq_factor, cpu) =
+ clk_get_rate(cpu_clk) / 1000;
+ clk_put(cpu_clk);
+ }
+ } else {
+ if (raw_capacity) {
+ pr_err("cpu_capacity: missing %pOF raw capacity\n",
+ cpu_node);
+ pr_err("cpu_capacity: partial information: fallback to 1024 for all CPUs\n");
+ }
+ cap_parsing_failed = true;
+ free_raw_capacity();
+ }
+
+ return !ret;
+}
+
/*
* This function returns the logic cpu number of the node.
* There are basically three kinds of return values:
@@ -461,7 +461,12 @@ static int __init parse_dt_topology(void)
of_node_put(cn);
return ret;
}
-#endif
+#else
+static int __init parse_dt_topology(void)
+{
+ return 0;
+}
+#endif /* CONFIG_OF */
/*
* cpu topology table
@@ -562,8 +567,8 @@ __weak int __init parse_acpi_topology(void)
return 0;
}
-#if defined(CONFIG_ARM64) || defined(CONFIG_RISCV)
-void __init init_cpu_topology(void)
+
+__weak void __init init_cpu_topology(void)
{
reset_cpu_topology();
@@ -576,4 +581,3 @@ void __init init_cpu_topology(void)
else if (of_have_populated_dt() && parse_dt_topology())
reset_cpu_topology();
}
-#endif
--
2.26.0.rc2
Previously, MIPS is using self-defined "globalnumber" in struct
mips_cpuinfo to store topology information. However, it's not friendly
to DeviceTree based systems and lack of cpu_capacity related feature
which can take advantage of multi-cluster system.
Here, we enabled arch_topology for MIPS and adapted some functions
to fit arch_topology structure.
Also, we implmented smp_store_cpu_info to probe CPU's topology information
by "globalnumber" registers in VP ASE or Ebase.CPUNum for legacy systems.
Signed-off-by: Jiaxun Yang <[email protected]>
--
v2:
- Squash header fix into this commit.
- Provide dummy functions for no-SMP config, CM code requires them.
(Thanks to 0-day CI for discover this)
---
arch/mips/Kconfig | 1 +
arch/mips/include/asm/cpu-info.h | 49 ----------------
arch/mips/include/asm/mach-ip27/mmzone.h | 2 +
arch/mips/include/asm/mach-ip27/topology.h | 2 +
arch/mips/include/asm/smp.h | 2 -
arch/mips/include/asm/sn/addrs.h | 1 +
arch/mips/include/asm/topology.h | 68 ++++++++++++++++++++--
arch/mips/kernel/cpu-probe.c | 43 --------------
arch/mips/kernel/setup.c | 1 +
arch/mips/kernel/smp.c | 55 ++---------------
arch/mips/kernel/topology.c | 42 +++++++++++++
11 files changed, 118 insertions(+), 148 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 690718b3701a..66b57e9f2b4d 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -20,6 +20,7 @@ config MIPS
select CLONE_BACKWARDS
select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
select CPU_PM if CPU_IDLE
+ select GENERIC_ARCH_TOPOLOGY if SMP
select GENERIC_ATOMIC64 if !64BIT
select GENERIC_CLOCKEVENTS
select GENERIC_CMOS_UPDATE
diff --git a/arch/mips/include/asm/cpu-info.h b/arch/mips/include/asm/cpu-info.h
index ed7ffe4e63a3..7140a3e61ce3 100644
--- a/arch/mips/include/asm/cpu-info.h
+++ b/arch/mips/include/asm/cpu-info.h
@@ -78,8 +78,6 @@ struct cpuinfo_mips {
struct cache_desc scache; /* Secondary cache */
struct cache_desc tcache; /* Tertiary/split secondary cache */
int srsets; /* Shadow register sets */
- int package;/* physical package number */
- unsigned int globalnumber;
#ifdef CONFIG_64BIT
int vmbits; /* Virtual memory size in bits */
#endif
@@ -139,53 +137,6 @@ struct proc_cpuinfo_notifier_args {
unsigned long n;
};
-static inline unsigned int cpu_cluster(struct cpuinfo_mips *cpuinfo)
-{
- /* Optimisation for systems where multiple clusters aren't used */
- if (!IS_ENABLED(CONFIG_CPU_MIPSR6))
- return 0;
-
- return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_CLUSTER) >>
- MIPS_GLOBALNUMBER_CLUSTER_SHF;
-}
-
-static inline unsigned int cpu_core(struct cpuinfo_mips *cpuinfo)
-{
- return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_CORE) >>
- MIPS_GLOBALNUMBER_CORE_SHF;
-}
-
-static inline unsigned int cpu_vpe_id(struct cpuinfo_mips *cpuinfo)
-{
- /* Optimisation for systems where VP(E)s aren't used */
- if (!IS_ENABLED(CONFIG_MIPS_MT_SMP) && !IS_ENABLED(CONFIG_CPU_MIPSR6))
- return 0;
-
- return (cpuinfo->globalnumber & MIPS_GLOBALNUMBER_VP) >>
- MIPS_GLOBALNUMBER_VP_SHF;
-}
-
-extern void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster);
-extern void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core);
-extern void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe);
-
-static inline bool cpus_are_siblings(int cpua, int cpub)
-{
- struct cpuinfo_mips *infoa = &cpu_data[cpua];
- struct cpuinfo_mips *infob = &cpu_data[cpub];
- unsigned int gnuma, gnumb;
-
- if (infoa->package != infob->package)
- return false;
-
- gnuma = infoa->globalnumber & ~MIPS_GLOBALNUMBER_VP;
- gnumb = infob->globalnumber & ~MIPS_GLOBALNUMBER_VP;
- if (gnuma != gnumb)
- return false;
-
- return true;
-}
-
static inline unsigned long cpu_asid_inc(void)
{
return 1 << CONFIG_MIPS_ASID_SHIFT;
diff --git a/arch/mips/include/asm/mach-ip27/mmzone.h b/arch/mips/include/asm/mach-ip27/mmzone.h
index 08c36e50a860..e0a53b97b4a8 100644
--- a/arch/mips/include/asm/mach-ip27/mmzone.h
+++ b/arch/mips/include/asm/mach-ip27/mmzone.h
@@ -2,6 +2,8 @@
#ifndef _ASM_MACH_MMZONE_H
#define _ASM_MACH_MMZONE_H
+#include <linux/mmzone.h>
+
#include <asm/sn/addrs.h>
#include <asm/sn/arch.h>
#include <asm/sn/agent.h>
diff --git a/arch/mips/include/asm/mach-ip27/topology.h b/arch/mips/include/asm/mach-ip27/topology.h
index d66cc53feab8..601e350908f7 100644
--- a/arch/mips/include/asm/mach-ip27/topology.h
+++ b/arch/mips/include/asm/mach-ip27/topology.h
@@ -2,6 +2,8 @@
#ifndef _ASM_MACH_TOPOLOGY_H
#define _ASM_MACH_TOPOLOGY_H 1
+#include <linux/numa.h>
+
#include <asm/sn/types.h>
#include <asm/mmzone.h>
diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
index 7990c1c70471..538e73f6bab0 100644
--- a/arch/mips/include/asm/smp.h
+++ b/arch/mips/include/asm/smp.h
@@ -21,8 +21,6 @@
#include <asm/smp-ops.h>
extern int smp_num_siblings;
-extern cpumask_t cpu_sibling_map[];
-extern cpumask_t cpu_core_map[];
extern cpumask_t cpu_foreign_map[];
static inline int raw_smp_processor_id(void)
diff --git a/arch/mips/include/asm/sn/addrs.h b/arch/mips/include/asm/sn/addrs.h
index 837d23e24976..1d3945ef2ca4 100644
--- a/arch/mips/include/asm/sn/addrs.h
+++ b/arch/mips/include/asm/sn/addrs.h
@@ -13,6 +13,7 @@
#ifndef __ASSEMBLY__
#include <linux/smp.h>
#include <linux/types.h>
+#include <asm/io.h>
#endif /* !__ASSEMBLY__ */
#include <asm/addrspace.h>
diff --git a/arch/mips/include/asm/topology.h b/arch/mips/include/asm/topology.h
index 0673d2d0f2e6..0f27a00df56d 100644
--- a/arch/mips/include/asm/topology.h
+++ b/arch/mips/include/asm/topology.h
@@ -9,13 +9,71 @@
#define __ASM_TOPOLOGY_H
#include <topology.h>
+#include <linux/arch_topology.h>
#include <linux/smp.h>
-#ifdef CONFIG_SMP
-#define topology_physical_package_id(cpu) (cpu_data[cpu].package)
-#define topology_core_id(cpu) (cpu_core(&cpu_data[cpu]))
-#define topology_core_cpumask(cpu) (&cpu_core_map[cpu])
-#define topology_sibling_cpumask(cpu) (&cpu_sibling_map[cpu])
+#if defined(CONFIG_SMP)
+static inline bool cpus_are_siblings(int cpua, int cpub)
+{
+ return cpumask_test_cpu(cpua, topology_sibling_cpumask(cpub));
+}
+
+static inline unsigned int cpu_cluster(int cpu)
+{
+ return cpu_topology[cpu].package_id;
+}
+
+static inline unsigned int cpu_core(int cpu)
+{
+ return cpu_topology[cpu].core_id;
+}
+
+static inline unsigned int cpu_vpe_id(int cpu)
+{
+ int id = cpu_topology[cpu].thread_id;
+
+ /* Uniprocessor system may get -1, but for hardware it's 0 */
+ if (id == -1)
+ return 0;
+
+ return id;
+}
+
+static inline void cpu_set_cluster(int cpu, unsigned int cluster)
+{
+ cpu_topology[cpu].package_id = cluster;
+}
+
+static inline void cpu_set_core(int cpu, unsigned int core)
+{
+ cpu_topology[cpu].core_id = core;
+}
+
+static inline void cpu_set_vpe_id(int cpu, unsigned int vpe)
+{
+ cpu_topology[cpu].thread_id = vpe;
+}
+#else
+static inline void init_cpu_topology(void) { }
+static inline bool cpus_are_siblings(int cpua, int cpub)
+{
+ return false;
+}
+
+static inline unsigned int cpu_cluster(int cpu)
+{
+ return 0;
+}
+
+static inline unsigned int cpu_core(int cpu)
+{
+ return 0;
+}
+
+static inline unsigned int cpu_vpe_id(int cpu)
+{
+ return 0;
+}
#endif
#endif /* __ASM_TOPOLOGY_H */
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index f21a2304401f..eead35e5dbfd 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1042,17 +1042,6 @@ static void decode_configs(struct cpuinfo_mips *c)
set_ftlb_enable(c, (mips_ftlb_disabled ? 0 : FTLB_EN) | FTLB_SET_PROB);
mips_probe_watch_registers(c);
-
-#ifndef CONFIG_MIPS_CPS
- if (cpu_has_mips_r2_r6) {
- unsigned int core;
-
- core = get_ebase_cpunum();
- if (cpu_has_mipsmt)
- core >>= fls(core_nvpes()) - 1;
- cpu_set_core(c, core);
- }
-#endif
}
/*
@@ -2303,35 +2292,3 @@ void cpu_report(void)
if (cpu_has_msa)
pr_info("MSA revision is: %08x\n", c->msa_id);
}
-
-void cpu_set_cluster(struct cpuinfo_mips *cpuinfo, unsigned int cluster)
-{
- /* Ensure the core number fits in the field */
- WARN_ON(cluster > (MIPS_GLOBALNUMBER_CLUSTER >>
- MIPS_GLOBALNUMBER_CLUSTER_SHF));
-
- cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CLUSTER;
- cpuinfo->globalnumber |= cluster << MIPS_GLOBALNUMBER_CLUSTER_SHF;
-}
-
-void cpu_set_core(struct cpuinfo_mips *cpuinfo, unsigned int core)
-{
- /* Ensure the core number fits in the field */
- WARN_ON(core > (MIPS_GLOBALNUMBER_CORE >> MIPS_GLOBALNUMBER_CORE_SHF));
-
- cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_CORE;
- cpuinfo->globalnumber |= core << MIPS_GLOBALNUMBER_CORE_SHF;
-}
-
-void cpu_set_vpe_id(struct cpuinfo_mips *cpuinfo, unsigned int vpe)
-{
- /* Ensure the VP(E) ID fits in the field */
- WARN_ON(vpe > (MIPS_GLOBALNUMBER_VP >> MIPS_GLOBALNUMBER_VP_SHF));
-
- /* Ensure we're not using VP(E)s without support */
- WARN_ON(vpe && !IS_ENABLED(CONFIG_MIPS_MT_SMP) &&
- !IS_ENABLED(CONFIG_CPU_MIPSR6));
-
- cpuinfo->globalnumber &= ~MIPS_GLOBALNUMBER_VP;
- cpuinfo->globalnumber |= vpe << MIPS_GLOBALNUMBER_VP_SHF;
-}
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 8a418783a6bb..b9fefc5dc702 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -784,6 +784,7 @@ void __init setup_arch(char **cmdline_p)
dmi_setup();
resource_init();
+ init_cpu_topology();
plat_smp_setup();
cpu_cache_init();
diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c
index 48d84d5fcc36..4896d6ecc719 100644
--- a/arch/mips/kernel/smp.c
+++ b/arch/mips/kernel/smp.c
@@ -34,6 +34,7 @@
#include <asm/mips-cps.h>
#include <asm/mmu_context.h>
#include <asm/time.h>
+#include <asm/topology.h>
#include <asm/setup.h>
#include <asm/maar.h>
@@ -47,10 +48,6 @@ EXPORT_SYMBOL(__cpu_logical_map);
int smp_num_siblings = 1;
EXPORT_SYMBOL(smp_num_siblings);
-/* representing the TCs (or siblings in Intel speak) of each logical CPU */
-cpumask_t cpu_sibling_map[NR_CPUS] __read_mostly;
-EXPORT_SYMBOL(cpu_sibling_map);
-
/* representing the core map of multi-core chips of each logical CPU */
cpumask_t cpu_core_map[NR_CPUS] __read_mostly;
EXPORT_SYMBOL(cpu_core_map);
@@ -65,12 +62,6 @@ static DECLARE_COMPLETION(cpu_running);
cpumask_t cpu_foreign_map[NR_CPUS] __read_mostly;
EXPORT_SYMBOL(cpu_foreign_map);
-/* representing cpus for which sibling maps can be computed */
-static cpumask_t cpu_sibling_setup_map;
-
-/* representing cpus for which core maps can be computed */
-static cpumask_t cpu_core_setup_map;
-
cpumask_t cpu_coherent_mask;
#ifdef CONFIG_GENERIC_IRQ_IPI
@@ -78,37 +69,6 @@ static struct irq_desc *call_desc;
static struct irq_desc *sched_desc;
#endif
-static inline void set_cpu_sibling_map(int cpu)
-{
- int i;
-
- cpumask_set_cpu(cpu, &cpu_sibling_setup_map);
-
- if (smp_num_siblings > 1) {
- for_each_cpu(i, &cpu_sibling_setup_map) {
- if (cpus_are_siblings(cpu, i)) {
- cpumask_set_cpu(i, &cpu_sibling_map[cpu]);
- cpumask_set_cpu(cpu, &cpu_sibling_map[i]);
- }
- }
- } else
- cpumask_set_cpu(cpu, &cpu_sibling_map[cpu]);
-}
-
-static inline void set_cpu_core_map(int cpu)
-{
- int i;
-
- cpumask_set_cpu(cpu, &cpu_core_setup_map);
-
- for_each_cpu(i, &cpu_core_setup_map) {
- if (cpu_data[cpu].package == cpu_data[i].package) {
- cpumask_set_cpu(i, &cpu_core_map[cpu]);
- cpumask_set_cpu(cpu, &cpu_core_map[i]);
- }
- }
-}
-
/*
* Calculate a new cpu_foreign_map mask whenever a
* new cpu appears or disappears.
@@ -131,7 +91,7 @@ void calculate_cpu_foreign_map(void)
for_each_online_cpu(i)
cpumask_andnot(&cpu_foreign_map[i],
- &temp_foreign_map, &cpu_sibling_map[i]);
+ &temp_foreign_map, topology_sibling_cpumask(i));
}
const struct plat_smp_ops *mp_ops;
@@ -177,7 +137,7 @@ void mips_smp_send_ipi_mask(const struct cpumask *mask, unsigned int action)
if (cpus_are_siblings(cpu, smp_processor_id()))
continue;
- core = cpu_core(&cpu_data[cpu]);
+ core = cpu_core(cpu);
while (!cpumask_test_cpu(cpu, &cpu_coherent_mask)) {
mips_cm_lock_other_cpu(cpu, CM_GCR_Cx_OTHER_BLOCK_LOCAL);
@@ -340,6 +300,8 @@ asmlinkage void start_secondary(void)
mips_clockevent_init();
mp_ops->init_secondary();
cpu_report();
+ cpu = smp_processor_id();
+ store_cpu_topology(cpu);
maar_init();
/*
@@ -349,7 +311,6 @@ asmlinkage void start_secondary(void)
calibrate_delay();
preempt_disable();
- cpu = smp_processor_id();
cpu_data[cpu].udelay_val = loops_per_jiffy;
cpumask_set_cpu(cpu, &cpu_coherent_mask);
@@ -363,9 +324,6 @@ asmlinkage void start_secondary(void)
/* The CPU is running and counters synchronised, now mark it online */
set_cpu_online(cpu, true);
- set_cpu_sibling_map(cpu);
- set_cpu_core_map(cpu);
-
calculate_cpu_foreign_map();
/*
@@ -411,8 +369,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus)
init_new_context(current, &init_mm);
current_thread_info()->cpu = 0;
mp_ops->prepare_cpus(max_cpus);
- set_cpu_sibling_map(0);
- set_cpu_core_map(0);
+ store_cpu_topology(0);
calculate_cpu_foreign_map();
#ifndef CONFIG_HOTPLUG_CPU
init_cpu_present(cpu_possible_mask);
diff --git a/arch/mips/kernel/topology.c b/arch/mips/kernel/topology.c
index cd3e1f82e1a5..112482de8187 100644
--- a/arch/mips/kernel/topology.c
+++ b/arch/mips/kernel/topology.c
@@ -31,3 +31,45 @@ static int __init topology_init(void)
}
subsys_initcall(topology_init);
+
+#if defined(CONFIG_SMP)
+void store_cpu_topology(unsigned int cpuid)
+{
+ struct cpu_topology *cpuid_topo = &cpu_topology[cpuid];
+
+ if (cpuid_topo->package_id != -1)
+ goto topology_populated;
+
+ if (cpu_has_vp) {
+ u32 gn = read_c0_globalnumber();
+
+ cpuid_topo->thread_id = (gn & MIPS_GLOBALNUMBER_VP) >>
+ MIPS_GLOBALNUMBER_VP_SHF;
+ cpuid_topo->core_id = (gn & MIPS_GLOBALNUMBER_CORE) >>
+ MIPS_GLOBALNUMBER_CORE_SHF;
+ cpuid_topo->package_id = (gn & MIPS_GLOBALNUMBER_CLUSTER) >>
+ MIPS_GLOBALNUMBER_CLUSTER_SHF;
+ } else {
+ int hwid;
+
+ if (cpu_has_mips_r2_r6)
+ hwid = get_ebase_cpunum();
+ else
+ hwid = cpuid; /* Assume hwid = cpuid */
+
+ if (smp_num_siblings == 1)
+ cpuid_topo->thread_id = -1;
+ else
+ cpuid_topo->thread_id = hwid % smp_num_siblings;
+
+ cpuid_topo->core_id = hwid / smp_num_siblings;
+ /* Platform code will handle multi-cluster case */
+ cpuid_topo->package_id = 0;
+ }
+
+topology_populated:
+ update_siblings_masks(cpuid);
+ pr_info("Topology: CPU %d: cluster: %d, core: %d, vpe: %d\n", cpuid,
+ cpu_cluster(cpuid), cpu_core(cpuid), cpu_vpe_id(cpuid));
+}
+#endif
--
2.26.0.rc2
Change the parameter of get/set topology ID functions from cpudata
to cpuid.
Also adjust include relationship to prevent conflictions.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/include/asm/mips-cm.h | 9 ++++---
arch/mips/include/asm/mips-cps.h | 2 ++
arch/mips/include/asm/smp-ops.h | 2 --
arch/mips/kernel/mips-cm.c | 4 ++--
arch/mips/kernel/mips-cpc.c | 4 ++--
arch/mips/kernel/pm-cps.c | 12 +++++-----
arch/mips/kernel/setup.c | 1 +
arch/mips/kernel/smp-cmp.c | 5 ++--
arch/mips/kernel/smp-cps.c | 41 ++++++++++++++++----------------
arch/mips/kernel/smp-mt.c | 3 ++-
drivers/cpuidle/cpuidle-cps.c | 3 ++-
11 files changed, 44 insertions(+), 42 deletions(-)
diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h
index aeae2effa123..6bab8f485bcd 100644
--- a/arch/mips/include/asm/mips-cm.h
+++ b/arch/mips/include/asm/mips-cm.h
@@ -395,8 +395,8 @@ static inline unsigned int mips_cm_max_vp_width(void)
*/
static inline unsigned int mips_cm_vp_id(unsigned int cpu)
{
- unsigned int core = cpu_core(&cpu_data[cpu]);
- unsigned int vp = cpu_vpe_id(&cpu_data[cpu]);
+ unsigned int core = cpu_core(cpu);
+ unsigned int vp = cpu_vpe_id(cpu);
return (core * mips_cm_max_vp_width()) + vp;
}
@@ -451,9 +451,8 @@ static inline void mips_cm_unlock_other(void) { }
*/
static inline void mips_cm_lock_other_cpu(unsigned int cpu, unsigned int block)
{
- struct cpuinfo_mips *d = &cpu_data[cpu];
-
- mips_cm_lock_other(cpu_cluster(d), cpu_core(d), cpu_vpe_id(d), block);
+ mips_cm_lock_other(cpu_cluster(cpu), cpu_core(cpu),
+ cpu_vpe_id(cpu), block);
}
#endif /* __MIPS_ASM_MIPS_CM_H__ */
diff --git a/arch/mips/include/asm/mips-cps.h b/arch/mips/include/asm/mips-cps.h
index fd43d876892e..340e367fcf07 100644
--- a/arch/mips/include/asm/mips-cps.h
+++ b/arch/mips/include/asm/mips-cps.h
@@ -9,6 +9,8 @@
#include <linux/io.h>
#include <linux/types.h>
+#include <linux/smp.h>
+#include <asm/topology.h>
extern unsigned long __cps_access_bad_size(void)
__compiletime_error("Bad size for CPS accessor");
diff --git a/arch/mips/include/asm/smp-ops.h b/arch/mips/include/asm/smp-ops.h
index 65618ff1280c..a58f5b019eb7 100644
--- a/arch/mips/include/asm/smp-ops.h
+++ b/arch/mips/include/asm/smp-ops.h
@@ -13,8 +13,6 @@
#include <linux/errno.h>
-#include <asm/mips-cps.h>
-
#ifdef CONFIG_SMP
#include <linux/cpumask.h>
diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c
index cdb93ed91cde..7dd3b6fd9c1c 100644
--- a/arch/mips/kernel/mips-cm.c
+++ b/arch/mips/kernel/mips-cm.c
@@ -295,7 +295,7 @@ void mips_cm_lock_other(unsigned int cluster, unsigned int core,
* CM 2.5 & older, so have to ensure other VP(E)s don't
* race with us.
*/
- curr_core = cpu_core(¤t_cpu_data);
+ curr_core = cpu_core(smp_processor_id());
spin_lock_irqsave(&per_cpu(cm_core_lock, curr_core),
per_cpu(cm_core_lock_flags, curr_core));
@@ -316,7 +316,7 @@ void mips_cm_unlock_other(void)
unsigned int curr_core;
if (mips_cm_revision() < CM_REV_CM3) {
- curr_core = cpu_core(¤t_cpu_data);
+ curr_core = cpu_core(smp_processor_id());
spin_unlock_irqrestore(&per_cpu(cm_core_lock, curr_core),
per_cpu(cm_core_lock_flags, curr_core));
} else {
diff --git a/arch/mips/kernel/mips-cpc.c b/arch/mips/kernel/mips-cpc.c
index 8d2535123f11..13f6f813e82a 100644
--- a/arch/mips/kernel/mips-cpc.c
+++ b/arch/mips/kernel/mips-cpc.c
@@ -94,7 +94,7 @@ void mips_cpc_lock_other(unsigned int core)
return;
preempt_disable();
- curr_core = cpu_core(¤t_cpu_data);
+ curr_core = cpu_core(smp_processor_id());
spin_lock_irqsave(&per_cpu(cpc_core_lock, curr_core),
per_cpu(cpc_core_lock_flags, curr_core));
write_cpc_cl_other(core << __ffs(CPC_Cx_OTHER_CORENUM));
@@ -114,7 +114,7 @@ void mips_cpc_unlock_other(void)
/* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */
return;
- curr_core = cpu_core(¤t_cpu_data);
+ curr_core = cpu_core(smp_processor_id());
spin_unlock_irqrestore(&per_cpu(cpc_core_lock, curr_core),
per_cpu(cpc_core_lock_flags, curr_core));
preempt_enable();
diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c
index 9bf60d7d44d3..cd4401bc79d2 100644
--- a/arch/mips/kernel/pm-cps.c
+++ b/arch/mips/kernel/pm-cps.c
@@ -110,7 +110,7 @@ static void coupled_barrier(atomic_t *a, unsigned online)
int cps_pm_enter_state(enum cps_pm_state state)
{
unsigned cpu = smp_processor_id();
- unsigned core = cpu_core(¤t_cpu_data);
+ unsigned int core = cpu_core(cpu);
unsigned online, left;
cpumask_t *coupled_mask = this_cpu_ptr(&online_coupled);
u32 *core_ready_count, *nc_core_ready_count;
@@ -128,7 +128,7 @@ int cps_pm_enter_state(enum cps_pm_state state)
#if defined(CONFIG_MIPS_MT) || defined(CONFIG_CPU_MIPSR6)
if (cpu_online(cpu)) {
cpumask_and(coupled_mask, cpu_online_mask,
- &cpu_sibling_map[cpu]);
+ topology_sibling_cpumask(cpu));
online = cpumask_weight(coupled_mask);
cpumask_clear_cpu(cpu, coupled_mask);
} else
@@ -145,7 +145,7 @@ int cps_pm_enter_state(enum cps_pm_state state)
return -EINVAL;
core_cfg = &mips_cps_core_bootcfg[core];
- vpe_cfg = &core_cfg->vpe_config[cpu_vpe_id(¤t_cpu_data)];
+ vpe_cfg = &core_cfg->vpe_config[cpu_vpe_id(smp_processor_id())];
vpe_cfg->pc = (unsigned long)mips_cps_pm_restore;
vpe_cfg->gp = (unsigned long)current_thread_info();
vpe_cfg->sp = 0;
@@ -444,7 +444,7 @@ static void *cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
/* Halt the VP via the CPC VP_STOP register */
unsigned int vpe_id;
- vpe_id = cpu_vpe_id(&cpu_data[cpu]);
+ vpe_id = cpu_vpe_id(cpu);
uasm_i_addiu(&p, t0, zero, 1 << vpe_id);
UASM_i_LA(&p, t1, (long)addr_cpc_cl_vp_stop());
uasm_i_sw(&p, t0, 0, t1);
@@ -482,7 +482,7 @@ static void *cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
* defined by the interAptiv & proAptiv SUMs as ensuring that the
* operation resulting from the preceding store is complete.
*/
- uasm_i_addiu(&p, t0, zero, 1 << cpu_core(&cpu_data[cpu]));
+ uasm_i_addiu(&p, t0, zero, 1 << cpu_core(cpu));
uasm_i_sw(&p, t0, 0, r_pcohctl);
uasm_i_lw(&p, t0, 0, r_pcohctl);
@@ -636,7 +636,7 @@ static void *cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
static int cps_pm_online_cpu(unsigned int cpu)
{
enum cps_pm_state state;
- unsigned core = cpu_core(&cpu_data[cpu]);
+ unsigned int core = cpu_core(cpu);
void *entry_fn, *core_rc;
for (state = CPS_PM_NC_WAIT; state < CPS_PM_STATE_COUNT; state++) {
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index b9fefc5dc702..92739120cb09 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -38,6 +38,7 @@
#include <asm/cpu.h>
#include <asm/debug.h>
#include <asm/dma-coherence.h>
+#include <asm/mips-cps.h>
#include <asm/sections.h>
#include <asm/setup.h>
#include <asm/smp-ops.h>
diff --git a/arch/mips/kernel/smp-cmp.c b/arch/mips/kernel/smp-cmp.c
index 76f5824cdb00..9f775195fe0d 100644
--- a/arch/mips/kernel/smp-cmp.c
+++ b/arch/mips/kernel/smp-cmp.c
@@ -21,6 +21,7 @@
#include <asm/hardirq.h>
#include <asm/mmu_context.h>
#include <asm/smp.h>
+#include <asm/mips-cps.h>
#include <asm/time.h>
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
@@ -29,8 +30,6 @@
static void cmp_init_secondary(void)
{
- struct cpuinfo_mips *c __maybe_unused = ¤t_cpu_data;
-
/* Assume GIC is present */
change_c0_status(ST0_IM, STATUSF_IP2 | STATUSF_IP3 | STATUSF_IP4 |
STATUSF_IP5 | STATUSF_IP6 | STATUSF_IP7);
@@ -39,7 +38,7 @@ static void cmp_init_secondary(void)
#ifdef CONFIG_MIPS_MT_SMP
if (cpu_has_mipsmt)
- cpu_set_vpe_id(c, (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
+ cpu_set_vpe_id(smp_processor_id(), (read_c0_tcbind() >> TCBIND_CURVPE_SHIFT) &
TCBIND_CURVPE);
#endif
}
diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c
index dbb3f1fc71ab..cf5875487d71 100644
--- a/arch/mips/kernel/smp-cps.c
+++ b/arch/mips/kernel/smp-cps.c
@@ -71,9 +71,10 @@ static void __init cps_smp_setup(void)
smp_num_siblings = core_vpes;
for (v = 0; v < min_t(int, core_vpes, NR_CPUS - nvpes); v++) {
- cpu_set_cluster(&cpu_data[nvpes + v], cl);
- cpu_set_core(&cpu_data[nvpes + v], c);
- cpu_set_vpe_id(&cpu_data[nvpes + v], v);
+ cpu_set_cluster(nvpes + v, cl);
+ cpu_set_core(nvpes + v, c);
+ cpu_set_vpe_id(nvpes + v, v);
+ update_siblings_masks(nvpes + v);
}
nvpes += core_vpes;
@@ -85,8 +86,8 @@ static void __init cps_smp_setup(void)
/* Indicate present CPUs (CPU being synonymous with VPE) */
for (v = 0; v < min_t(unsigned, nvpes, NR_CPUS); v++) {
- set_cpu_possible(v, cpu_cluster(&cpu_data[v]) == 0);
- set_cpu_present(v, cpu_cluster(&cpu_data[v]) == 0);
+ set_cpu_possible(v, cpu_cluster(v) == 0);
+ set_cpu_present(v, cpu_cluster(v) == 0);
__cpu_number_map[v] = v;
__cpu_logical_map[v] = v;
}
@@ -190,8 +191,8 @@ static void __init cps_prepare_cpus(unsigned int max_cpus)
}
/* Mark this CPU as booted */
- atomic_set(&mips_cps_core_bootcfg[cpu_core(¤t_cpu_data)].vpe_mask,
- 1 << cpu_vpe_id(¤t_cpu_data));
+ atomic_set(&mips_cps_core_bootcfg[cpu_core(smp_processor_id())].vpe_mask,
+ 1 << cpu_vpe_id(smp_processor_id()));
return;
err_out:
@@ -285,16 +286,16 @@ static void boot_core(unsigned int core, unsigned int vpe_id)
static void remote_vpe_boot(void *dummy)
{
- unsigned core = cpu_core(¤t_cpu_data);
+ unsigned int core = cpu_core(smp_processor_id());
struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
- mips_cps_boot_vpes(core_cfg, cpu_vpe_id(¤t_cpu_data));
+ mips_cps_boot_vpes(core_cfg, cpu_vpe_id(smp_processor_id()));
}
static int cps_boot_secondary(int cpu, struct task_struct *idle)
{
- unsigned core = cpu_core(&cpu_data[cpu]);
- unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
+ unsigned int core = cpu_core(cpu);
+ unsigned int vpe_id = cpu_vpe_id(cpu);
struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core];
struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id];
unsigned long core_entry;
@@ -302,14 +303,14 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle)
int err;
/* We don't yet support booting CPUs in other clusters */
- if (cpu_cluster(&cpu_data[cpu]) != cpu_cluster(&raw_current_cpu_data))
+ if (cpu_cluster(cpu) != cpu_cluster(smp_processor_id()))
return -ENOSYS;
vpe_cfg->pc = (unsigned long)&smp_bootstrap;
vpe_cfg->sp = __KSTK_TOS(idle);
vpe_cfg->gp = (unsigned long)task_thread_info(idle);
- atomic_or(1 << cpu_vpe_id(&cpu_data[cpu]), &core_cfg->vpe_mask);
+ atomic_or(1 << cpu_vpe_id(cpu), &core_cfg->vpe_mask);
preempt_disable();
@@ -406,10 +407,10 @@ static void cps_shutdown_this_cpu(enum cpu_death death)
unsigned int cpu, core, vpe_id;
cpu = smp_processor_id();
- core = cpu_core(&cpu_data[cpu]);
+ core = cpu_core(cpu);
if (death == CPU_DEATH_HALT) {
- vpe_id = cpu_vpe_id(&cpu_data[cpu]);
+ vpe_id = cpu_vpe_id(cpu);
pr_debug("Halting core %d VP%d\n", core, vpe_id);
if (cpu_has_mipsmt) {
@@ -456,8 +457,8 @@ static int cps_cpu_disable(void)
if (!cps_pm_support_state(CPS_PM_POWER_GATED))
return -EINVAL;
- core_cfg = &mips_cps_core_bootcfg[cpu_core(¤t_cpu_data)];
- atomic_sub(1 << cpu_vpe_id(¤t_cpu_data), &core_cfg->vpe_mask);
+ core_cfg = &mips_cps_core_bootcfg[cpu_core(smp_processor_id())];
+ atomic_sub(1 << cpu_vpe_id(smp_processor_id()), &core_cfg->vpe_mask);
smp_mb__after_atomic();
set_cpu_online(cpu, false);
calculate_cpu_foreign_map();
@@ -506,7 +507,7 @@ void play_dead(void)
static void wait_for_sibling_halt(void *ptr_cpu)
{
unsigned cpu = (unsigned long)ptr_cpu;
- unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]);
+ unsigned int vpe_id = cpu_vpe_id(cpu);
unsigned halted;
unsigned long flags;
@@ -520,8 +521,8 @@ static void wait_for_sibling_halt(void *ptr_cpu)
static void cps_cpu_die(unsigned int cpu)
{
- unsigned core = cpu_core(&cpu_data[cpu]);
- unsigned int vpe_id = cpu_vpe_id(&cpu_data[cpu]);
+ unsigned int core = cpu_core(cpu);
+ unsigned int vpe_id = cpu_vpe_id(cpu);
ktime_t fail_time;
unsigned stat;
int err;
diff --git a/arch/mips/kernel/smp-mt.c b/arch/mips/kernel/smp-mt.c
index 5f04a0141068..5eb31b8c8ea0 100644
--- a/arch/mips/kernel/smp-mt.c
+++ b/arch/mips/kernel/smp-mt.c
@@ -21,6 +21,7 @@
#include <asm/hardirq.h>
#include <asm/mmu_context.h>
#include <asm/time.h>
+#include <asm/topology.h>
#include <asm/mipsregs.h>
#include <asm/mipsmtregs.h>
#include <asm/mips_mt.h>
@@ -72,7 +73,7 @@ static unsigned int __init smvp_vpe_init(unsigned int tc, unsigned int mvpconf0,
if (tc != 0)
smvp_copy_vpe_config();
- cpu_set_vpe_id(&cpu_data[ncpu], tc);
+ cpu_set_vpe_id(ncpu, tc);
return ncpu;
}
diff --git a/drivers/cpuidle/cpuidle-cps.c b/drivers/cpuidle/cpuidle-cps.c
index dff0ff4cc218..e6ce01751940 100644
--- a/drivers/cpuidle/cpuidle-cps.c
+++ b/drivers/cpuidle/cpuidle-cps.c
@@ -10,6 +10,7 @@
#include <asm/idle.h>
#include <asm/pm-cps.h>
+#include <asm/topology.h>
/* Enumeration of the various idle states this driver may enter */
enum cps_idle_state {
@@ -159,7 +160,7 @@ static int __init cps_cpuidle_init(void)
device = &per_cpu(cpuidle_dev, cpu);
device->cpu = cpu;
#ifdef CONFIG_ARCH_NEEDS_CPU_IDLE_COUPLED
- cpumask_copy(&device->coupled_cpus, &cpu_sibling_map[cpu]);
+ cpumask_copy(&device->coupled_cpus, topology_sibling_cpumask(cpu));
#endif
err = cpuidle_register_device(device);
--
2.26.0.rc2
Adapt topology functions to new interface in various of kernel
parts like perf, proc.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/kernel/cacheinfo.c | 19 ++++++-------------
arch/mips/kernel/perf_event_mipsxx.c | 4 ++--
arch/mips/kernel/proc.c | 8 ++++----
arch/mips/mm/c-r4k.c | 4 ++--
arch/mips/mm/context.c | 4 ++--
arch/mips/oprofile/op_model_mipsxx.c | 4 ++--
6 files changed, 18 insertions(+), 25 deletions(-)
diff --git a/arch/mips/kernel/cacheinfo.c b/arch/mips/kernel/cacheinfo.c
index 47312c529410..9a5f12830440 100644
--- a/arch/mips/kernel/cacheinfo.c
+++ b/arch/mips/kernel/cacheinfo.c
@@ -3,6 +3,7 @@
* MIPS cacheinfo support
*/
#include <linux/cacheinfo.h>
+#include <linux/topology.h>
/* Populates leaf and increments to next leaf */
#define populate_cache(cache, leaf, c_level, c_type) \
@@ -50,22 +51,12 @@ static int __init_cache_level(unsigned int cpu)
return 0;
}
-static void fill_cpumask_siblings(int cpu, cpumask_t *cpu_map)
-{
- int cpu1;
-
- for_each_possible_cpu(cpu1)
- if (cpus_are_siblings(cpu, cpu1))
- cpumask_set_cpu(cpu1, cpu_map);
-}
-
static void fill_cpumask_cluster(int cpu, cpumask_t *cpu_map)
{
int cpu1;
- int cluster = cpu_cluster(&cpu_data[cpu]);
for_each_possible_cpu(cpu1)
- if (cpu_cluster(&cpu_data[cpu1]) == cluster)
+ if (cpu_cluster(cpu1) == cpu_cluster(cpu))
cpumask_set_cpu(cpu1, cpu_map);
}
@@ -77,9 +68,11 @@ static int __populate_cache_leaves(unsigned int cpu)
if (c->icache.waysize) {
/* L1 caches are per core */
- fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
+ cpumask_copy(&this_leaf->shared_cpu_map,
+ topology_sibling_cpumask(cpu));
populate_cache(dcache, this_leaf, 1, CACHE_TYPE_DATA);
- fill_cpumask_siblings(cpu, &this_leaf->shared_cpu_map);
+ cpumask_copy(&this_leaf->shared_cpu_map,
+ topology_sibling_cpumask(cpu));
populate_cache(icache, this_leaf, 1, CACHE_TYPE_INST);
} else {
populate_cache(dcache, this_leaf, 1, CACHE_TYPE_UNIFIED);
diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c
index 128fc9999c56..e9ed3526bad0 100644
--- a/arch/mips/kernel/perf_event_mipsxx.c
+++ b/arch/mips/kernel/perf_event_mipsxx.c
@@ -127,7 +127,7 @@ static DEFINE_RWLOCK(pmuint_rwlock);
0 : (smp_processor_id() & MIPS_CPUID_TO_COUNTER_MASK))
#else
#define vpe_id() (cpu_has_mipsmt_pertccounters ? \
- 0 : cpu_vpe_id(¤t_cpu_data))
+ 0 : cpu_vpe_id(smp_processor_id()))
#endif
/* Copied from op_model_mipsxx.c */
@@ -343,7 +343,7 @@ static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
*/
cpu = (event->cpu >= 0) ? event->cpu : smp_processor_id();
- ctrl = M_PERFCTL_VPEID(cpu_vpe_id(&cpu_data[cpu]));
+ ctrl = M_PERFCTL_VPEID(cpu_vpe_id(smp_processor_id()));
ctrl |= M_TC_EN_VPE;
cpuc->saved_ctrl[idx] |= ctrl;
pr_debug("Enabling perf counter for CPU%d\n", cpu);
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index f8d36710cd58..e8795b262ca2 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -138,14 +138,14 @@ static int show_cpuinfo(struct seq_file *m, void *v)
cpu_data[n].srsets);
seq_printf(m, "kscratch registers\t: %d\n",
hweight8(cpu_data[n].kscratch_mask));
- seq_printf(m, "package\t\t\t: %d\n", cpu_data[n].package);
- seq_printf(m, "core\t\t\t: %d\n", cpu_core(&cpu_data[n]));
+ seq_printf(m, "package\t\t\t: %d\n", cpu_cluster(n));
+ seq_printf(m, "core\t\t\t: %d\n", cpu_core(n));
#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_CPU_MIPSR6)
if (cpu_has_mipsmt)
- seq_printf(m, "VPE\t\t\t: %d\n", cpu_vpe_id(&cpu_data[n]));
+ seq_printf(m, "VPE\t\t\t: %d\n", cpu_vpe_id(n));
else if (cpu_has_vp)
- seq_printf(m, "VP\t\t\t: %d\n", cpu_vpe_id(&cpu_data[n]));
+ seq_printf(m, "VP\t\t\t: %d\n", cpu_vpe_id(n));
#endif
sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 36a311348739..851559ef0bc3 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -547,7 +547,7 @@ static inline int has_valid_asid(const struct mm_struct *mm, unsigned int type)
if (cpu_has_mmid)
return cpu_context(0, mm) != 0;
- /* cpu_sibling_map[] undeclared when !CONFIG_SMP */
+ /* topology_sibling_cpumask undeclared when !CONFIG_SMP */
#ifdef CONFIG_SMP
/*
* If r4k_on_each_cpu does SMP calls, it does them to a single VPE in
@@ -555,7 +555,7 @@ static inline int has_valid_asid(const struct mm_struct *mm, unsigned int type)
* Otherwise we need to worry about all present CPUs.
*/
if (r4k_op_needs_ipi(type))
- mask = &cpu_sibling_map[smp_processor_id()];
+ mask = topology_sibling_cpumask(smp_processor_id());
#endif
for_each_cpu(i, mask)
if (cpu_context(i, mm))
diff --git a/arch/mips/mm/context.c b/arch/mips/mm/context.c
index b25564090939..ad2d8b7f464b 100644
--- a/arch/mips/mm/context.c
+++ b/arch/mips/mm/context.c
@@ -241,12 +241,12 @@ void check_switch_mmu_context(struct mm_struct *mm)
* increase then we need to invalidate any TLB entries for our MMID
* that we might otherwise pick up from a sibling.
*
- * We ifdef on CONFIG_SMP because cpu_sibling_map isn't defined in
+ * We ifdef on CONFIG_SMP because topology_sibling_cpumask isn't defined in
* CONFIG_SMP=n kernels.
*/
#ifdef CONFIG_SMP
if (cpu_has_shared_ftlb_entries &&
- cpumask_intersects(&tlb_flush_pending, &cpu_sibling_map[cpu])) {
+ cpumask_intersects(&tlb_flush_pending, topology_sibling_cpumask(cpu))) {
/* Ensure we operate on the new MMID */
mtc0_tlbw_hazard();
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index a537bf98912c..0129dfcf5d55 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -37,9 +37,9 @@ static int perfcount_irq;
#ifdef CONFIG_MIPS_MT_SMP
#define WHAT (MIPS_PERFCTRL_MT_EN_VPE | \
- M_PERFCTL_VPEID(cpu_vpe_id(¤t_cpu_data)))
+ M_PERFCTL_VPEID(cpu_vpe_id(smp_processor_id())))
#define vpe_id() (cpu_has_mipsmt_pertccounters ? \
- 0 : cpu_vpe_id(¤t_cpu_data))
+ 0 : cpu_vpe_id(smp_processor_id()))
/*
* The number of bits to shift to convert between counters per core and
--
2.26.0.rc2
Change the parameter of cpu_vpe_id from cpu_data to cpuid.
Signed-off-by: Jiaxun Yang <[email protected]>
---
drivers/irqchip/irq-mips-cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-mips-cpu.c b/drivers/irqchip/irq-mips-cpu.c
index 95d4fd8f7a96..eed3edf8480b 100644
--- a/drivers/irqchip/irq-mips-cpu.c
+++ b/drivers/irqchip/irq-mips-cpu.c
@@ -100,7 +100,7 @@ static void mips_mt_send_ipi(struct irq_data *d, unsigned int cpu)
WARN_ON(!cpus_are_siblings(smp_processor_id(), cpu));
vpflags = dvpe();
- settc(cpu_vpe_id(&cpu_data[cpu]));
+ settc(cpu_vpe_id(cpu));
write_vpe_c0_cause(read_vpe_c0_cause() | (C_SW0 << hwirq));
evpe(vpflags);
--
2.26.0.rc2
Change the parameter of cpu_set_core from cpudata to cpuid.
Also set cluster id for bmips as it have different method to probe
actual hwid of CPU, and smp_store_cpuinfo is using cluster id to
determine if we should probe topology info again.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/kernel/smp-bmips.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index 9058e9dcf080..c40bb37eab38 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -247,7 +247,8 @@ static void bmips_init_secondary(void)
break;
case CPU_BMIPS5000:
write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
- cpu_set_core(¤t_cpu_data, (read_c0_brcm_config() >> 25) & 3);
+ cpu_set_core(smp_processor_id(), (read_c0_brcm_config() >> 25) & 3);
+ cpu_set_cluster(smp_processor_id(), 0);
break;
}
}
--
2.26.0.rc2
Use new functions to set core_id & cluster_id.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/mips/netlogic/common/smp.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/mips/netlogic/common/smp.c b/arch/mips/netlogic/common/smp.c
index 39a300bd6cc2..14bfa8a099cc 100644
--- a/arch/mips/netlogic/common/smp.c
+++ b/arch/mips/netlogic/common/smp.c
@@ -122,8 +122,8 @@ static void nlm_init_secondary(void)
int hwtid;
hwtid = hard_smp_processor_id();
- cpu_set_core(¤t_cpu_data, hwtid / NLM_THREADS_PER_CORE);
- current_cpu_data.package = nlm_nodeid();
+ cpu_set_core(smp_processor_id(), hwtid / NLM_THREADS_PER_CORE);
+ cpu_set_cluster(smp_processor_id(), nlm_nodeid());
nlm_percpu_init(hwtid);
nlm_smp_irq_init(hwtid);
}
--
2.26.0.rc2
Use the new interface to setup topology information.
Signed-off-by: Jiaxun Yang <[email protected]>
---
.../include/asm/mach-loongson64/topology.h | 2 ++
arch/mips/loongson64/smp.c | 20 +++++++++----------
2 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/arch/mips/include/asm/mach-loongson64/topology.h b/arch/mips/include/asm/mach-loongson64/topology.h
index 3414a1fd1783..999464ed0c20 100644
--- a/arch/mips/include/asm/mach-loongson64/topology.h
+++ b/arch/mips/include/asm/mach-loongson64/topology.h
@@ -2,6 +2,8 @@
#ifndef _ASM_MACH_TOPOLOGY_H
#define _ASM_MACH_TOPOLOGY_H
+#include <linux/numa.h>
+
#ifdef CONFIG_NUMA
#define cpu_to_node(cpu) (cpu_logical_map(cpu) >> 2)
diff --git a/arch/mips/loongson64/smp.c b/arch/mips/loongson64/smp.c
index e1fe8bbb377d..bb37d0a7e79c 100644
--- a/arch/mips/loongson64/smp.c
+++ b/arch/mips/loongson64/smp.c
@@ -353,10 +353,10 @@ static void loongson3_init_secondary(void)
loongson3_ipi_write32(0xffffffff, ipi_en0_regs[cpu_logical_map(i)]);
per_cpu(cpu_state, cpu) = CPU_ONLINE;
- cpu_set_core(&cpu_data[cpu],
+ cpu_set_core(cpu,
cpu_logical_map(cpu) % loongson_sysconf.cores_per_package);
- cpu_data[cpu].package =
- cpu_logical_map(cpu) / loongson_sysconf.cores_per_package;
+ cpu_set_cluster(cpu,
+ cpu_logical_map(cpu) / loongson_sysconf.cores_per_package);
i = 0;
core0_c0count[cpu] = 0;
@@ -368,7 +368,7 @@ static void loongson3_init_secondary(void)
if (i > MAX_LOOPS)
i = MAX_LOOPS;
- if (cpu_data[cpu].package)
+ if (cpu_cluster(cpu))
initcount = core0_c0count[cpu] + i;
else /* Local access is faster for loops */
initcount = core0_c0count[cpu] + i/2;
@@ -421,9 +421,9 @@ static void __init loongson3_smp_setup(void)
ipi_status0_regs_init();
ipi_en0_regs_init();
ipi_mailbox_buf_init();
- cpu_set_core(&cpu_data[0],
+ cpu_set_core(0,
cpu_logical_map(0) % loongson_sysconf.cores_per_package);
- cpu_data[0].package = cpu_logical_map(0) / loongson_sysconf.cores_per_package;
+ cpu_set_cluster(0, cpu_logical_map(0) / loongson_sysconf.cores_per_package);
}
static void __init loongson3_prepare_cpus(unsigned int max_cpus)
@@ -752,8 +752,8 @@ void play_dead(void)
static int loongson3_disable_clock(unsigned int cpu)
{
- uint64_t core_id = cpu_core(&cpu_data[cpu]);
- uint64_t package_id = cpu_data[cpu].package;
+ uint64_t core_id = cpu_core(cpu);
+ uint64_t package_id = cpu_cluster(cpu);
if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) {
LOONGSON_CHIPCFG(package_id) &= ~(1 << (12 + core_id));
@@ -766,8 +766,8 @@ static int loongson3_disable_clock(unsigned int cpu)
static int loongson3_enable_clock(unsigned int cpu)
{
- uint64_t core_id = cpu_core(&cpu_data[cpu]);
- uint64_t package_id = cpu_data[cpu].package;
+ uint64_t core_id = cpu_core(cpu);
+ uint64_t package_id = cpu_cluster(cpu);
if ((read_c0_prid() & PRID_REV_MASK) == PRID_REV_LOONGSON3A_R1) {
LOONGSON_CHIPCFG(package_id) |= 1 << (12 + core_id);
--
2.26.0.rc2
Hi Jiaxun,
I love your patch! Yet something to improve:
[auto build test ERROR on driver-core/driver-core-testing]
[also build test ERROR on pm/linux-next linus/master next-20200411]
[cannot apply to tip/perf/core tip/irq/core v5.6]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Jiaxun-Yang/MIPS-Topology-DeviceTree-CPU-rework-v2/20200412-113308
base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git a10c9c710f9ecea87b9f4bbb837467893b4bef01
config: mips-allnoconfig (attached as .config)
compiler: mips-linux-gcc (GCC) 9.3.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=9.3.0 make.cross ARCH=mips
If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot <[email protected]>
Note: the linux-review/Jiaxun-Yang/MIPS-Topology-DeviceTree-CPU-rework-v2/20200412-113308 HEAD 8e8e9d4f7aa74359f2199773786ffe2fbb7877d0 builds fine.
It only hurts bisectibility.
All errors (new ones prefixed by >>):
arch/mips/include/asm/mips-cm.h:398:31: error: passing argument 1 of 'cpu_core' makes integer from pointer without a cast [-Werror=int-conversion]
398 | unsigned int core = cpu_core(&cpu_data[cpu]);
| ^~~~~~~~~~~~~~
| |
| struct cpuinfo_mips *
In file included from include/linux/topology.h:36,
from include/linux/gfp.h:9,
from include/linux/xarray.h:14,
from include/linux/radix-tree.h:18,
from include/linux/idr.h:15,
from include/linux/kernfs.h:13,
from include/linux/sysfs.h:16,
from include/linux/kobject.h:20,
from include/linux/of.h:17,
from arch/mips/kernel/mips-cpc.c:9:
arch/mips/include/asm/topology.h:68:41: note: expected 'int' but argument is of type 'struct cpuinfo_mips *'
68 | static inline unsigned int cpu_core(int cpu)
| ~~~~^~~
In file included from arch/mips/include/asm/mips-cps.h:104,
from arch/mips/kernel/mips-cpc.c:13:
arch/mips/include/asm/mips-cm.h:399:31: error: passing argument 1 of 'cpu_vpe_id' makes integer from pointer without a cast [-Werror=int-conversion]
399 | unsigned int vp = cpu_vpe_id(&cpu_data[cpu]);
| ^~~~~~~~~~~~~~
| |
| struct cpuinfo_mips *
In file included from include/linux/topology.h:36,
from include/linux/gfp.h:9,
from include/linux/xarray.h:14,
from include/linux/radix-tree.h:18,
from include/linux/idr.h:15,
from include/linux/kernfs.h:13,
from include/linux/sysfs.h:16,
from include/linux/kobject.h:20,
from include/linux/of.h:17,
from arch/mips/kernel/mips-cpc.c:9:
arch/mips/include/asm/topology.h:73:43: note: expected 'int' but argument is of type 'struct cpuinfo_mips *'
73 | static inline unsigned int cpu_vpe_id(int cpu)
| ~~~~^~~
In file included from arch/mips/include/asm/mips-cps.h:104,
from arch/mips/kernel/mips-cpc.c:13:
arch/mips/include/asm/mips-cm.h: In function 'mips_cm_lock_other_cpu':
arch/mips/include/asm/mips-cm.h:456:33: error: passing argument 1 of 'cpu_cluster' makes integer from pointer without a cast [-Werror=int-conversion]
456 | mips_cm_lock_other(cpu_cluster(d), cpu_core(d), cpu_vpe_id(d), block);
| ^
| |
| struct cpuinfo_mips *
In file included from include/linux/topology.h:36,
from include/linux/gfp.h:9,
from include/linux/xarray.h:14,
from include/linux/radix-tree.h:18,
from include/linux/idr.h:15,
from include/linux/kernfs.h:13,
from include/linux/sysfs.h:16,
from include/linux/kobject.h:20,
from include/linux/of.h:17,
from arch/mips/kernel/mips-cpc.c:9:
arch/mips/include/asm/topology.h:63:44: note: expected 'int' but argument is of type 'struct cpuinfo_mips *'
63 | static inline unsigned int cpu_cluster(int cpu)
| ~~~~^~~
In file included from arch/mips/include/asm/mips-cps.h:104,
from arch/mips/kernel/mips-cpc.c:13:
arch/mips/include/asm/mips-cm.h:456:46: error: passing argument 1 of 'cpu_core' makes integer from pointer without a cast [-Werror=int-conversion]
456 | mips_cm_lock_other(cpu_cluster(d), cpu_core(d), cpu_vpe_id(d), block);
| ^
| |
| struct cpuinfo_mips *
In file included from include/linux/topology.h:36,
from include/linux/gfp.h:9,
from include/linux/xarray.h:14,
from include/linux/radix-tree.h:18,
from include/linux/idr.h:15,
from include/linux/kernfs.h:13,
from include/linux/sysfs.h:16,
from include/linux/kobject.h:20,
from include/linux/of.h:17,
from arch/mips/kernel/mips-cpc.c:9:
arch/mips/include/asm/topology.h:68:41: note: expected 'int' but argument is of type 'struct cpuinfo_mips *'
68 | static inline unsigned int cpu_core(int cpu)
| ~~~~^~~
In file included from arch/mips/include/asm/mips-cps.h:104,
from arch/mips/kernel/mips-cpc.c:13:
arch/mips/include/asm/mips-cm.h:456:61: error: passing argument 1 of 'cpu_vpe_id' makes integer from pointer without a cast [-Werror=int-conversion]
456 | mips_cm_lock_other(cpu_cluster(d), cpu_core(d), cpu_vpe_id(d), block);
| ^
| |
| struct cpuinfo_mips *
In file included from include/linux/topology.h:36,
from include/linux/gfp.h:9,
from include/linux/xarray.h:14,
from include/linux/radix-tree.h:18,
from include/linux/idr.h:15,
from include/linux/kernfs.h:13,
from include/linux/sysfs.h:16,
from include/linux/kobject.h:20,
from include/linux/of.h:17,
from arch/mips/kernel/mips-cpc.c:9:
arch/mips/include/asm/topology.h:73:43: note: expected 'int' but argument is of type 'struct cpuinfo_mips *'
73 | static inline unsigned int cpu_vpe_id(int cpu)
| ~~~~^~~
arch/mips/kernel/mips-cpc.c: In function 'mips_cpc_lock_other':
>> arch/mips/kernel/mips-cpc.c:97:23: error: passing argument 1 of 'cpu_core' makes integer from pointer without a cast [-Werror=int-conversion]
97 | curr_core = cpu_core(¤t_cpu_data);
In file included from include/linux/topology.h:36,
from include/linux/gfp.h:9,
from include/linux/xarray.h:14,
from include/linux/radix-tree.h:18,
from include/linux/idr.h:15,
from include/linux/kernfs.h:13,
from include/linux/sysfs.h:16,
from include/linux/kobject.h:20,
from include/linux/of.h:17,
from arch/mips/kernel/mips-cpc.c:9:
arch/mips/include/asm/topology.h:68:41: note: expected 'int' but argument is of type 'struct cpuinfo_mips *'
68 | static inline unsigned int cpu_core(int cpu)
| ~~~~^~~
arch/mips/kernel/mips-cpc.c: In function 'mips_cpc_unlock_other':
arch/mips/kernel/mips-cpc.c:117:23: error: passing argument 1 of 'cpu_core' makes integer from pointer without a cast [-Werror=int-conversion]
117 | curr_core = cpu_core(¤t_cpu_data);
In file included from include/linux/topology.h:36,
from include/linux/gfp.h:9,
from include/linux/xarray.h:14,
from include/linux/radix-tree.h:18,
from include/linux/idr.h:15,
from include/linux/kernfs.h:13,
from include/linux/sysfs.h:16,
from include/linux/kobject.h:20,
from include/linux/of.h:17,
from arch/mips/kernel/mips-cpc.c:9:
arch/mips/include/asm/topology.h:68:41: note: expected 'int' but argument is of type 'struct cpuinfo_mips *'
68 | static inline unsigned int cpu_core(int cpu)
| ~~~~^~~
cc1: all warnings being treated as errors
vim +/cpu_core +97 arch/mips/kernel/mips-cpc.c
76ae658465c231 Paul Burton 2014-02-14 87
76ae658465c231 Paul Burton 2014-02-14 88 void mips_cpc_lock_other(unsigned int core)
76ae658465c231 Paul Burton 2014-02-14 89 {
6b89d22e742aa3 Matt Redfearn 2016-09-07 90 unsigned int curr_core;
d6219420480b75 Matt Redfearn 2016-09-07 91
d6219420480b75 Matt Redfearn 2016-09-07 92 if (mips_cm_revision() >= CM_REV_CM3)
d6219420480b75 Matt Redfearn 2016-09-07 93 /* Systems with CM >= 3 lock the CPC via mips_cm_lock_other */
d6219420480b75 Matt Redfearn 2016-09-07 94 return;
d6219420480b75 Matt Redfearn 2016-09-07 95
76ae658465c231 Paul Burton 2014-02-14 96 preempt_disable();
f875a832d20285 Paul Burton 2017-08-12 @97 curr_core = cpu_core(¤t_cpu_data);
76ae658465c231 Paul Burton 2014-02-14 98 spin_lock_irqsave(&per_cpu(cpc_core_lock, curr_core),
76ae658465c231 Paul Burton 2014-02-14 99 per_cpu(cpc_core_lock_flags, curr_core));
829ca2be9c55c7 Paul Burton 2017-08-12 100 write_cpc_cl_other(core << __ffs(CPC_Cx_OTHER_CORENUM));
78a54c4d8e5a79 Paul Burton 2015-09-22 101
78a54c4d8e5a79 Paul Burton 2015-09-22 102 /*
78a54c4d8e5a79 Paul Burton 2015-09-22 103 * Ensure the core-other region reflects the appropriate core &
78a54c4d8e5a79 Paul Burton 2015-09-22 104 * VP before any accesses to it occur.
78a54c4d8e5a79 Paul Burton 2015-09-22 105 */
78a54c4d8e5a79 Paul Burton 2015-09-22 106 mb();
76ae658465c231 Paul Burton 2014-02-14 107 }
76ae658465c231 Paul Burton 2014-02-14 108
:::::: The code at line 97 was first introduced by commit
:::::: f875a832d2028523f9b53c261b67e05a359bab8b MIPS: Abstract CPU core & VP(E) ID access through accessor functions
:::::: TO: Paul Burton <[email protected]>
:::::: CC: Ralf Baechle <[email protected]>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/[email protected]
Hi Jiaxun,
I love your patch! Yet something to improve:
[auto build test ERROR on driver-core/driver-core-testing]
[also build test ERROR on pm/linux-next linus/master next-20200411]
[cannot apply to tip/perf/core tip/irq/core v5.6]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Jiaxun-Yang/MIPS-Topology-DeviceTree-CPU-rework-v2/20200412-113308
base: https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git a10c9c710f9ecea87b9f4bbb837467893b4bef01
config: mips-fuloong2e_defconfig (attached as .config)
compiler: mips64el-linux-gcc (GCC) 9.3.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=9.3.0 make.cross ARCH=mips
If you fix the issue, kindly add following tag as appropriate
Reported-by: kbuild test robot <[email protected]>
Note: the linux-review/Jiaxun-Yang/MIPS-Topology-DeviceTree-CPU-rework-v2/20200412-113308 HEAD 8e8e9d4f7aa74359f2199773786ffe2fbb7877d0 builds fine.
It only hurts bisectibility.
All errors (new ones prefixed by >>):
In file included from arch/mips/include/asm/mips-cps.h:104,
from arch/mips/kernel/process.c:43:
arch/mips/include/asm/mips-cm.h: In function 'mips_cm_vp_id':
>> arch/mips/include/asm/mips-cm.h:398:31: error: passing argument 1 of 'cpu_core' makes integer from pointer without a cast [-Werror=int-conversion]
398 | unsigned int core = cpu_core(&cpu_data[cpu]);
| ^~~~~~~~~~~~~~
| |
| struct cpuinfo_mips *
In file included from include/linux/topology.h:36,
from include/linux/gfp.h:9,
from include/linux/xarray.h:14,
from include/linux/radix-tree.h:18,
from include/linux/idr.h:15,
from include/linux/kernfs.h:13,
from include/linux/sysfs.h:16,
from include/linux/kobject.h:20,
from include/linux/of.h:17,
from include/linux/clocksource.h:19,
from include/linux/clockchips.h:14,
from include/linux/tick.h:8,
from arch/mips/kernel/process.c:17:
arch/mips/include/asm/topology.h:68:41: note: expected 'int' but argument is of type 'struct cpuinfo_mips *'
68 | static inline unsigned int cpu_core(int cpu)
| ~~~~^~~
In file included from arch/mips/include/asm/mips-cps.h:104,
from arch/mips/kernel/process.c:43:
>> arch/mips/include/asm/mips-cm.h:399:31: error: passing argument 1 of 'cpu_vpe_id' makes integer from pointer without a cast [-Werror=int-conversion]
399 | unsigned int vp = cpu_vpe_id(&cpu_data[cpu]);
| ^~~~~~~~~~~~~~
| |
| struct cpuinfo_mips *
In file included from include/linux/topology.h:36,
from include/linux/gfp.h:9,
from include/linux/xarray.h:14,
from include/linux/radix-tree.h:18,
from include/linux/idr.h:15,
from include/linux/kernfs.h:13,
from include/linux/sysfs.h:16,
from include/linux/kobject.h:20,
from include/linux/of.h:17,
from include/linux/clocksource.h:19,
from include/linux/clockchips.h:14,
from include/linux/tick.h:8,
from arch/mips/kernel/process.c:17:
arch/mips/include/asm/topology.h:73:43: note: expected 'int' but argument is of type 'struct cpuinfo_mips *'
73 | static inline unsigned int cpu_vpe_id(int cpu)
| ~~~~^~~
In file included from arch/mips/include/asm/mips-cps.h:104,
from arch/mips/kernel/process.c:43:
arch/mips/include/asm/mips-cm.h: In function 'mips_cm_lock_other_cpu':
>> arch/mips/include/asm/mips-cm.h:456:33: error: passing argument 1 of 'cpu_cluster' makes integer from pointer without a cast [-Werror=int-conversion]
456 | mips_cm_lock_other(cpu_cluster(d), cpu_core(d), cpu_vpe_id(d), block);
| ^
| |
| struct cpuinfo_mips *
In file included from include/linux/topology.h:36,
from include/linux/gfp.h:9,
from include/linux/xarray.h:14,
from include/linux/radix-tree.h:18,
from include/linux/idr.h:15,
from include/linux/kernfs.h:13,
from include/linux/sysfs.h:16,
from include/linux/kobject.h:20,
from include/linux/of.h:17,
from include/linux/clocksource.h:19,
from include/linux/clockchips.h:14,
from include/linux/tick.h:8,
from arch/mips/kernel/process.c:17:
arch/mips/include/asm/topology.h:63:44: note: expected 'int' but argument is of type 'struct cpuinfo_mips *'
63 | static inline unsigned int cpu_cluster(int cpu)
| ~~~~^~~
In file included from arch/mips/include/asm/mips-cps.h:104,
from arch/mips/kernel/process.c:43:
arch/mips/include/asm/mips-cm.h:456:46: error: passing argument 1 of 'cpu_core' makes integer from pointer without a cast [-Werror=int-conversion]
456 | mips_cm_lock_other(cpu_cluster(d), cpu_core(d), cpu_vpe_id(d), block);
| ^
| |
| struct cpuinfo_mips *
In file included from include/linux/topology.h:36,
from include/linux/gfp.h:9,
from include/linux/xarray.h:14,
from include/linux/radix-tree.h:18,
from include/linux/idr.h:15,
from include/linux/kernfs.h:13,
from include/linux/sysfs.h:16,
from include/linux/kobject.h:20,
from include/linux/of.h:17,
from include/linux/clocksource.h:19,
from include/linux/clockchips.h:14,
from include/linux/tick.h:8,
from arch/mips/kernel/process.c:17:
arch/mips/include/asm/topology.h:68:41: note: expected 'int' but argument is of type 'struct cpuinfo_mips *'
68 | static inline unsigned int cpu_core(int cpu)
| ~~~~^~~
In file included from arch/mips/include/asm/mips-cps.h:104,
from arch/mips/kernel/process.c:43:
arch/mips/include/asm/mips-cm.h:456:61: error: passing argument 1 of 'cpu_vpe_id' makes integer from pointer without a cast [-Werror=int-conversion]
456 | mips_cm_lock_other(cpu_cluster(d), cpu_core(d), cpu_vpe_id(d), block);
| ^
| |
| struct cpuinfo_mips *
In file included from include/linux/topology.h:36,
from include/linux/gfp.h:9,
from include/linux/xarray.h:14,
from include/linux/radix-tree.h:18,
from include/linux/idr.h:15,
from include/linux/kernfs.h:13,
from include/linux/sysfs.h:16,
from include/linux/kobject.h:20,
from include/linux/of.h:17,
from include/linux/clocksource.h:19,
from include/linux/clockchips.h:14,
from include/linux/tick.h:8,
from arch/mips/kernel/process.c:17:
arch/mips/include/asm/topology.h:73:43: note: expected 'int' but argument is of type 'struct cpuinfo_mips *'
73 | static inline unsigned int cpu_vpe_id(int cpu)
| ~~~~^~~
cc1: all warnings being treated as errors
--
arch/mips/kernel/cacheinfo.c: In function 'fill_cpumask_siblings':
arch/mips/kernel/cacheinfo.c:58:7: error: implicit declaration of function 'cpus_are_siblings' [-Werror=implicit-function-declaration]
58 | if (cpus_are_siblings(cpu, cpu1))
| ^~~~~~~~~~~~~~~~~
arch/mips/kernel/cacheinfo.c: In function 'fill_cpumask_cluster':
>> arch/mips/kernel/cacheinfo.c:65:16: error: implicit declaration of function 'cpu_cluster' [-Werror=implicit-function-declaration]
65 | int cluster = cpu_cluster(&cpu_data[cpu]);
| ^~~~~~~~~~~
cc1: all warnings being treated as errors
--
arch/mips/kernel/proc.c: In function 'show_cpuinfo':
>> arch/mips/kernel/proc.c:141:50: error: 'struct cpuinfo_mips' has no member named 'package'
141 | seq_printf(m, "package\t\t\t: %d\n", cpu_data[n].package);
| ^
>> arch/mips/kernel/proc.c:142:45: error: passing argument 1 of 'cpu_core' makes integer from pointer without a cast [-Werror=int-conversion]
142 | seq_printf(m, "core\t\t\t: %d\n", cpu_core(&cpu_data[n]));
| ^~~~~~~~~~~~
| |
| struct cpuinfo_mips *
In file included from include/linux/topology.h:36,
from include/linux/gfp.h:9,
from include/linux/xarray.h:14,
from include/linux/radix-tree.h:18,
from include/linux/fs.h:15,
from include/linux/seq_file.h:11,
from arch/mips/kernel/proc.c:10:
arch/mips/include/asm/topology.h:68:41: note: expected 'int' but argument is of type 'struct cpuinfo_mips *'
68 | static inline unsigned int cpu_core(int cpu)
| ~~~~^~~
cc1: all warnings being treated as errors
vim +/cpu_core +398 arch/mips/include/asm/mips-cm.h
7573b94e08aeb5 Paul Burton 2015-09-22 385
7573b94e08aeb5 Paul Burton 2015-09-22 386 /**
7573b94e08aeb5 Paul Burton 2015-09-22 387 * mips_cm_vp_id() - calculate the hardware VP ID for a CPU
7573b94e08aeb5 Paul Burton 2015-09-22 388 * @cpu: the CPU whose VP ID to calculate
7573b94e08aeb5 Paul Burton 2015-09-22 389 *
7573b94e08aeb5 Paul Burton 2015-09-22 390 * Hardware such as the GIC uses identifiers for VPs which may not match the
7573b94e08aeb5 Paul Burton 2015-09-22 391 * CPU numbers used by Linux. This function calculates the hardware VP
7573b94e08aeb5 Paul Burton 2015-09-22 392 * identifier corresponding to a given CPU.
7573b94e08aeb5 Paul Burton 2015-09-22 393 *
7573b94e08aeb5 Paul Burton 2015-09-22 394 * Return: the VP ID for the CPU.
7573b94e08aeb5 Paul Burton 2015-09-22 395 */
7573b94e08aeb5 Paul Burton 2015-09-22 396 static inline unsigned int mips_cm_vp_id(unsigned int cpu)
7573b94e08aeb5 Paul Burton 2015-09-22 397 {
f875a832d20285 Paul Burton 2017-08-12 @398 unsigned int core = cpu_core(&cpu_data[cpu]);
7573b94e08aeb5 Paul Burton 2015-09-22 @399 unsigned int vp = cpu_vpe_id(&cpu_data[cpu]);
7573b94e08aeb5 Paul Burton 2015-09-22 400
7573b94e08aeb5 Paul Burton 2015-09-22 401 return (core * mips_cm_max_vp_width()) + vp;
7573b94e08aeb5 Paul Burton 2015-09-22 402 }
7573b94e08aeb5 Paul Burton 2015-09-22 403
23d5de8efb9aed Paul Burton 2015-09-22 404 #ifdef CONFIG_MIPS_CM
23d5de8efb9aed Paul Burton 2015-09-22 405
23d5de8efb9aed Paul Burton 2015-09-22 406 /**
68923cdc2eb341 Paul Burton 2017-08-12 407 * mips_cm_lock_other - lock access to redirect/other region
68923cdc2eb341 Paul Burton 2017-08-12 408 * @cluster: the other cluster to be accessed
23d5de8efb9aed Paul Burton 2015-09-22 409 * @core: the other core to be accessed
23d5de8efb9aed Paul Burton 2015-09-22 410 * @vp: the VP within the other core to be accessed
68923cdc2eb341 Paul Burton 2017-08-12 411 * @block: the register block to be accessed
23d5de8efb9aed Paul Burton 2015-09-22 412 *
68923cdc2eb341 Paul Burton 2017-08-12 413 * Configure the redirect/other region for the local core/VP (depending upon
68923cdc2eb341 Paul Burton 2017-08-12 414 * the CM revision) to target the specified @cluster, @core, @vp & register
68923cdc2eb341 Paul Burton 2017-08-12 415 * @block. Must be called before using the redirect/other region, and followed
68923cdc2eb341 Paul Burton 2017-08-12 416 * by a call to mips_cm_unlock_other() when access to the redirect/other region
68923cdc2eb341 Paul Burton 2017-08-12 417 * is complete.
68923cdc2eb341 Paul Burton 2017-08-12 418 *
68923cdc2eb341 Paul Burton 2017-08-12 419 * This function acquires a spinlock such that code between it &
68923cdc2eb341 Paul Burton 2017-08-12 420 * mips_cm_unlock_other() calls cannot be pre-empted by anything which may
68923cdc2eb341 Paul Burton 2017-08-12 421 * reconfigure the redirect/other region, and cannot be interfered with by
68923cdc2eb341 Paul Burton 2017-08-12 422 * another VP in the core. As such calls to this function should not be nested.
23d5de8efb9aed Paul Burton 2015-09-22 423 */
68923cdc2eb341 Paul Burton 2017-08-12 424 extern void mips_cm_lock_other(unsigned int cluster, unsigned int core,
68923cdc2eb341 Paul Burton 2017-08-12 425 unsigned int vp, unsigned int block);
23d5de8efb9aed Paul Burton 2015-09-22 426
23d5de8efb9aed Paul Burton 2015-09-22 427 /**
68923cdc2eb341 Paul Burton 2017-08-12 428 * mips_cm_unlock_other - unlock access to redirect/other region
23d5de8efb9aed Paul Burton 2015-09-22 429 *
68923cdc2eb341 Paul Burton 2017-08-12 430 * Must be called after mips_cm_lock_other() once all required access to the
68923cdc2eb341 Paul Burton 2017-08-12 431 * redirect/other region has been completed.
23d5de8efb9aed Paul Burton 2015-09-22 432 */
23d5de8efb9aed Paul Burton 2015-09-22 433 extern void mips_cm_unlock_other(void);
23d5de8efb9aed Paul Burton 2015-09-22 434
23d5de8efb9aed Paul Burton 2015-09-22 435 #else /* !CONFIG_MIPS_CM */
23d5de8efb9aed Paul Burton 2015-09-22 436
68923cdc2eb341 Paul Burton 2017-08-12 437 static inline void mips_cm_lock_other(unsigned int cluster, unsigned int core,
68923cdc2eb341 Paul Burton 2017-08-12 438 unsigned int vp, unsigned int block) { }
23d5de8efb9aed Paul Burton 2015-09-22 439 static inline void mips_cm_unlock_other(void) { }
23d5de8efb9aed Paul Burton 2015-09-22 440
23d5de8efb9aed Paul Burton 2015-09-22 441 #endif /* !CONFIG_MIPS_CM */
23d5de8efb9aed Paul Burton 2015-09-22 442
68923cdc2eb341 Paul Burton 2017-08-12 443 /**
68923cdc2eb341 Paul Burton 2017-08-12 444 * mips_cm_lock_other_cpu - lock access to redirect/other region
68923cdc2eb341 Paul Burton 2017-08-12 445 * @cpu: the other CPU whose register we want to access
68923cdc2eb341 Paul Burton 2017-08-12 446 *
68923cdc2eb341 Paul Burton 2017-08-12 447 * Configure the redirect/other region for the local core/VP (depending upon
68923cdc2eb341 Paul Burton 2017-08-12 448 * the CM revision) to target the specified @cpu & register @block. This is
68923cdc2eb341 Paul Burton 2017-08-12 449 * equivalent to calling mips_cm_lock_other() but accepts a Linux CPU number
68923cdc2eb341 Paul Burton 2017-08-12 450 * for convenience.
68923cdc2eb341 Paul Burton 2017-08-12 451 */
68923cdc2eb341 Paul Burton 2017-08-12 452 static inline void mips_cm_lock_other_cpu(unsigned int cpu, unsigned int block)
68923cdc2eb341 Paul Burton 2017-08-12 453 {
68923cdc2eb341 Paul Burton 2017-08-12 454 struct cpuinfo_mips *d = &cpu_data[cpu];
68923cdc2eb341 Paul Burton 2017-08-12 455
68923cdc2eb341 Paul Burton 2017-08-12 @456 mips_cm_lock_other(cpu_cluster(d), cpu_core(d), cpu_vpe_id(d), block);
68923cdc2eb341 Paul Burton 2017-08-12 457 }
68923cdc2eb341 Paul Burton 2017-08-12 458
:::::: The code at line 398 was first introduced by commit
:::::: f875a832d2028523f9b53c261b67e05a359bab8b MIPS: Abstract CPU core & VP(E) ID access through accessor functions
:::::: TO: Paul Burton <[email protected]>
:::::: CC: Ralf Baechle <[email protected]>
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/[email protected]
On Sun, 12 Apr 2020 13:24:21 +0800
kbuild test robot <[email protected]> wrote:
> Hi Jiaxun,
>
> I love your patch! Yet something to improve:
>
> [auto build test ERROR on driver-core/driver-core-testing]
> [also build test ERROR on pm/linux-next linus/master next-20200411]
> [cannot apply to tip/perf/core tip/irq/core v5.6]
> [if your patch is applied to the wrong git tree, please drop us a
> note to help improve the system. BTW, we also suggest to use '--base'
> option to specify the base tree in git format-patch, please see
> https://stackoverflow.com/a/37406982]
>
> url:
> https://github.com/0day-ci/linux/commits/Jiaxun-Yang/MIPS-Topology-DeviceTree-CPU-rework-v2/20200412-113308
> base:
> https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git
> a10c9c710f9ecea87b9f4bbb837467893b4bef01 config: mips-allnoconfig
> (attached as .config) compiler: mips-linux-gcc (GCC) 9.3.0 reproduce:
> wget
> https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross
> -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached
> .config to linux build tree GCC_VERSION=9.3.0 make.cross ARCH=mips
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kbuild test robot <[email protected]>
>
> Note: the
> linux-review/Jiaxun-Yang/MIPS-Topology-DeviceTree-CPU-rework-v2/20200412-113308
> HEAD 8e8e9d4f7aa74359f2199773786ffe2fbb7877d0 builds fine. It only
> hurts bisectibility.
>
Hi all,
In this case I think it should be fine to break bisect, otherwise #05
will combine too many modifications in different subsystems.
Thanks.
--
Jiaxun Yang
On Sun, 12 Apr 2020 15:49:27 +0800
Jiaxun Yang <[email protected]> wrote:
> On Sun, 12 Apr 2020 13:24:21 +0800
> kbuild test robot <[email protected]> wrote:
>
> > Hi Jiaxun,
> >
> > I love your patch! Yet something to improve:
> >
> > [auto build test ERROR on driver-core/driver-core-testing]
> > [also build test ERROR on pm/linux-next linus/master next-20200411]
> > [cannot apply to tip/perf/core tip/irq/core v5.6]
> > [if your patch is applied to the wrong git tree, please drop us a
> > note to help improve the system. BTW, we also suggest to use '--base'
> > option to specify the base tree in git format-patch, please see
> > https://stackoverflow.com/a/37406982]
> >
> > url:
> > https://github.com/0day-ci/linux/commits/Jiaxun-Yang/MIPS-Topology-DeviceTree-CPU-rework-v2/20200412-113308
> > base:
> > https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git
> > a10c9c710f9ecea87b9f4bbb837467893b4bef01 config: mips-allnoconfig
> > (attached as .config) compiler: mips-linux-gcc (GCC) 9.3.0 reproduce:
> > wget
> > https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross
> > -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached
> > .config to linux build tree GCC_VERSION=9.3.0 make.cross ARCH=mips
> >
> > If you fix the issue, kindly add following tag as appropriate
> > Reported-by: kbuild test robot <[email protected]>
> >
> > Note: the
> > linux-review/Jiaxun-Yang/MIPS-Topology-DeviceTree-CPU-rework-v2/20200412-113308
> > HEAD 8e8e9d4f7aa74359f2199773786ffe2fbb7877d0 builds fine. It only
> > hurts bisectibility.
> >
> Hi all,
>
> In this case I think it should be fine to break bisect, otherwise #05
> will combine too many modifications in different subsystems.
No. It is never OK to break bisection, specially when it affects a
whole architecture.
We introduce gradual changes over multiple subsystems all the time by
using configuration symbols, no matter the number of patches. Yes, it is
sometimes hard. But breaking the kernel and forcing everyone else to
just deal with it is not acceptable.
Thanks,
M.
--
Jazz is not dead. It just smells funny...
On Sun, 12 Apr 2020 10:39:08 +0100
Marc Zyngier <[email protected]> wrote:
> On Sun, 12 Apr 2020 15:49:27 +0800
> Jiaxun Yang <[email protected]> wrote:
>
> > On Sun, 12 Apr 2020 13:24:21 +0800
> > kbuild test robot <[email protected]> wrote:
> >
> > > Hi Jiaxun,
> > >
> > > I love your patch! Yet something to improve:
> > >
> > > [auto build test ERROR on driver-core/driver-core-testing]
> > > [also build test ERROR on pm/linux-next linus/master
> > > next-20200411] [cannot apply to tip/perf/core tip/irq/core v5.6]
> > > [if your patch is applied to the wrong git tree, please drop us a
> > > note to help improve the system. BTW, we also suggest to use
> > > '--base' option to specify the base tree in git format-patch,
> > > please see https://stackoverflow.com/a/37406982]
> > >
> > > url:
> > > https://github.com/0day-ci/linux/commits/Jiaxun-Yang/MIPS-Topology-DeviceTree-CPU-rework-v2/20200412-113308
> > > base:
> > > https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core.git
> > > a10c9c710f9ecea87b9f4bbb837467893b4bef01 config: mips-allnoconfig
> > > (attached as .config) compiler: mips-linux-gcc (GCC) 9.3.0
> > > reproduce: wget
> > > https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross
> > > -O ~/bin/make.cross chmod +x ~/bin/make.cross # save the attached
> > > .config to linux build tree GCC_VERSION=9.3.0 make.cross
> > > ARCH=mips
> > >
> > > If you fix the issue, kindly add following tag as appropriate
> > > Reported-by: kbuild test robot <[email protected]>
> > >
> > > Note: the
> > > linux-review/Jiaxun-Yang/MIPS-Topology-DeviceTree-CPU-rework-v2/20200412-113308
> > > HEAD 8e8e9d4f7aa74359f2199773786ffe2fbb7877d0 builds fine. It only
> > > hurts bisectibility.
> > >
> > Hi all,
> >
> > In this case I think it should be fine to break bisect, otherwise
> > #05 will combine too many modifications in different subsystems.
>
> No. It is never OK to break bisection, specially when it affects a
> whole architecture.
I'm going to squash all these into patch #5.
It's really hard to do it gradually.
Thanks.
>
> We introduce gradual changes over multiple subsystems all the time by
> using configuration symbols, no matter the number of patches. Yes, it
> is sometimes hard. But breaking the kernel and forcing everyone else
> to just deal with it is not acceptable.
>
> Thanks,
>
> M.
--
Jiaxun Yang
On Tue, 14 Apr 2020 09:27:34 +0100
Sudeep Holla <[email protected]> wrote:
> On Sun, Apr 12, 2020 at 11:20:34AM +0800, Jiaxun Yang wrote:
> > For MIPS platform, when topology isn't probed by DeviceTree,
> > possible_cpu might be empty when calling init_cpu_topology,
> > that may result cpu_topology not fully reseted for all CPUs.
> > So here we can reset all cpus instead of possible cpus.
> >
>
> As I have told before adjust and make it default before this function
> gets called.
Hi,
That's really impossible under current MIPS code structure.
Another option would be prefill possible_cpu with all_cpu_mask before
calling topology_init, but that would make the code unnecessarily
complex.
Here simply reset the whole array won't cause any regression.
Thanks.
>
--
Jiaxun Yang
On Tue, 14 Apr 2020 09:21:36 +0100
Sudeep Holla <[email protected]> wrote:
> On Sun, Apr 12, 2020 at 11:20:31AM +0800, Jiaxun Yang wrote:
> > All the plat_smp_setup are setting up possible cpus in their
> > platform code. So prefill_possible_map is actually overwriting
> > platform's setup, which seems unreasonable.
> >
>
> Why don't you rearrange the code so that this still remains as is and
> the platforms can override if they need. If you do so, you don't need
> the change in 04/11 as I suggested previously.
Actually this code break a case that cpumask is not continuous.
It do happen on some MIPS platforms.
Yes. rearrange this is a option but I think it is making the logic
unnecessarily complex.
If you think that's better I'll do so.
Thanks.
>
--
Jiaxun Yang
On Tue, Apr 14, 2020 at 04:35:14PM +0800, Jiaxun Yang wrote:
> On Tue, 14 Apr 2020 09:27:34 +0100
> Sudeep Holla <[email protected]> wrote:
>
> > On Sun, Apr 12, 2020 at 11:20:34AM +0800, Jiaxun Yang wrote:
> > > For MIPS platform, when topology isn't probed by DeviceTree,
> > > possible_cpu might be empty when calling init_cpu_topology,
> > > that may result cpu_topology not fully reseted for all CPUs.
> > > So here we can reset all cpus instead of possible cpus.
> > >
> >
> > As I have told before adjust and make it default before this function
> > gets called.
>
> Hi,
>
> That's really impossible under current MIPS code structure.
>
I really doubt that, but I have no knowledge on MIPS port, so I would
let maintainers take that call.
> Another option would be prefill possible_cpu with all_cpu_mask before
> calling topology_init, but that would make the code unnecessarily
> complex.
>
I still prefer that. By the time we call this function on a config
with say NR_CPUS=1024, we would have parsed DT and set nr_cpus to say 8
or 16 just for sake of example, so if platforms can't figure the
possible CPUs, let them set it to NR_CPUs so that not all platforms
have to run through that loop.
> Here simply reset the whole array won't cause any regression.
>
Not necessary, please discuss and check if some simplification to MIPS
can be done rather than patching here and there to make it work.
--
Regards,
Sudeep
On Sun, Apr 12, 2020 at 11:20:31AM +0800, Jiaxun Yang wrote:
> All the plat_smp_setup are setting up possible cpus in their
> platform code. So prefill_possible_map is actually overwriting
> platform's setup, which seems unreasonable.
>
Why don't you rearrange the code so that this still remains as is and
the platforms can override if they need. If you do so, you don't need
the change in 04/11 as I suggested previously.
--
Regards,
Sudeep
On Sun, Apr 12, 2020 at 11:20:33AM +0800, Jiaxun Yang wrote:
> Simply drop unnecessary archtecture limitions and add dummy
> function for platforms without OF support.
> As some of the functions are conflicting with Arm's platform
> implementations, we mark them as weak.
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> --
> v2: Use weak instead of ifdef to exclude functions for Arm.
> ---
> drivers/base/arch_topology.c | 116 ++++++++++++++++++-----------------
> 1 file changed, 60 insertions(+), 56 deletions(-)
>
> diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c
> index 4d0a0038b476..13dc4fbf043f 100644
> --- a/drivers/base/arch_topology.c
> +++ b/drivers/base/arch_topology.c
> @@ -143,57 +143,6 @@ void topology_normalize_cpu_scale(void)
> }
> }
>
> -bool __init topology_parse_cpu_capacity(struct device_node *cpu_node, int cpu)
This function is not under any #ifdefery and you are adding it but the
commit message indicates opposite. Please state the reason why this needs
to be moved under #ifdef
--
Regards,
Sudeep
On Sun, Apr 12, 2020 at 11:20:34AM +0800, Jiaxun Yang wrote:
> For MIPS platform, when topology isn't probed by DeviceTree,
> possible_cpu might be empty when calling init_cpu_topology,
> that may result cpu_topology not fully reseted for all CPUs.
> So here we can reset all cpus instead of possible cpus.
>
As I have told before adjust and make it default before this function
gets called.
--
Regards,
Sudeep