[Re-submitting to cc dri-devel, sorry about the noise]
Hello all,
v9 cleanly applies on top of latest next-20200609 tree.
v9 does not depend on other patches as the last binding doc has been merged.
All feedback up to this point has been addressed. Specific details in
individual patch changelogs.
The biggest changes are the deprecation of the Synopsys DW bridge bind()
API in favor of of_drm_find_bridge() and .attach callbacks, the addition
of a TODO entry which outlines future planned bridge driver refactorings
and a reordering of some i.MX 6 patches to appease checkpatch.
The idea behind the TODO is to get this regmap and i.MX 6 driver merged
and then do the rest of refactorings in-tree because it's easier and the
refactorings themselves are out-of-scope of this series which is adding
i.MX 6 support and is quite big already, so please, if there are more
refactoring ideas, let's add them to the TODO doc. :) I intend to tackle
those after this series is merged to avoid two complex inter-dependent
simultaneous series.
As always more testing is welcome especially on Rockchip and STM SoCs.
Big thank you to everyone who has contributed to this up to now,
Adrian
Adrian Ratiu (11):
drm: bridge: dw_mipi_dsi: add initial regmap infrastructure
drm: bridge: dw_mipi_dsi: abstract register access using reg_fields
drm: bridge: dw_mipi_dsi: add dsi v1.01 support
drm: bridge: dw_mipi_dsi: remove bind/unbind API
dt-bindings: display: add i.MX6 MIPI DSI host controller doc
ARM: dts: imx6qdl: add missing mipi dsi properties
drm: imx: Add i.MX 6 MIPI DSI host platform driver
drm: stm: dw-mipi-dsi: let the bridge handle the HW version check
drm: bridge: dw-mipi-dsi: split low power cfg register into fields
drm: bridge: dw-mipi-dsi: fix bad register field offsets
Documentation: gpu: todo: Add dw-mipi-dsi consolidation plan
.../display/imx/fsl,mipi-dsi-imx6.yaml | 112 +++
Documentation/gpu/todo.rst | 25 +
arch/arm/boot/dts/imx6qdl.dtsi | 8 +
drivers/gpu/drm/bridge/synopsys/Kconfig | 1 +
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 713 ++++++++++++------
drivers/gpu/drm/imx/Kconfig | 8 +
drivers/gpu/drm/imx/Makefile | 1 +
drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 399 ++++++++++
.../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 7 +-
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 16 +-
10 files changed, 1059 insertions(+), 231 deletions(-)
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
--
2.27.0
In order to support multiple versions of the Synopsis MIPI DSI host
controller, which have different register layouts but almost identical
HW protocols, we add a regmap infrastructure which can abstract away
register accesses for platform drivers using the bridge.
The controller HW revision is detected during bridge probe which will
be used in future commits to load the relevant register layout which
the bridge will use transparently to the platform drivers.
Suggested-by: Ezequiel Garcia <[email protected]>
Reviewed-by: Enric Balletbo i Serra <[email protected]>
Tested-by: Adrian Pop <[email protected]>
Tested-by: Arnaud Ferraris <[email protected]>
Signed-off-by: Adrian Ratiu <[email protected]>
---
Changes since v8:
- Minor typo fix
- Added Reviewed-by Enric tag
Changes since v7:
- Minor checkpatch line fix
Changes since v6:
- Select REGMAP_MMIO in Kconfig (Enric)
- Drop unnecessary stack variable inits (Enric)
- Make bridge error ASAP after a bad revision read (Enric)
- Drop redundant read of hw_version in dphy_timing_config (Enric)
New in v5.
---
drivers/gpu/drm/bridge/synopsys/Kconfig | 1 +
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 210 ++++++++++--------
2 files changed, 121 insertions(+), 90 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/Kconfig b/drivers/gpu/drm/bridge/synopsys/Kconfig
index 21a1be3ced0f3..080146093b68e 100644
--- a/drivers/gpu/drm/bridge/synopsys/Kconfig
+++ b/drivers/gpu/drm/bridge/synopsys/Kconfig
@@ -39,3 +39,4 @@ config DRM_DW_MIPI_DSI
select DRM_KMS_HELPER
select DRM_MIPI_DSI
select DRM_PANEL_BRIDGE
+ select REGMAP_MMIO
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 5ef0f154aa7bd..34b8668ae24ea 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -15,6 +15,7 @@
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
#include <linux/reset.h>
#include <video/mipi_display.h>
@@ -227,6 +228,7 @@ struct dw_mipi_dsi {
struct drm_bridge *panel_bridge;
struct device *dev;
void __iomem *base;
+ struct regmap *regs;
struct clk *pclk;
@@ -235,6 +237,7 @@ struct dw_mipi_dsi {
u32 lanes;
u32 format;
unsigned long mode_flags;
+ u32 hw_version;
#ifdef CONFIG_DEBUG_FS
struct dentry *debugfs;
@@ -249,6 +252,13 @@ struct dw_mipi_dsi {
const struct dw_mipi_dsi_plat_data *plat_data;
};
+static const struct regmap_config dw_mipi_dsi_regmap_cfg = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .name = "dw-mipi-dsi",
+};
+
/*
* Check if either a link to a master or slave is present
*/
@@ -280,16 +290,6 @@ static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge)
return container_of(bridge, struct dw_mipi_dsi, bridge);
}
-static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val)
-{
- writel(val, dsi->base + reg);
-}
-
-static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg)
-{
- return readl(dsi->base + reg);
-}
-
static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host,
struct mipi_dsi_device *device)
{
@@ -366,8 +366,8 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
if (lpm)
val |= CMD_MODE_ALL_LP;
- dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
- dsi_write(dsi, DSI_CMD_MODE_CFG, val);
+ regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
+ regmap_write(dsi->regs, DSI_CMD_MODE_CFG, val);
}
static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
@@ -375,20 +375,20 @@ static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
int ret;
u32 val, mask;
- ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
- val, !(val & GEN_CMD_FULL), 1000,
- CMD_PKT_STATUS_TIMEOUT_US);
+ ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+ val, !(val & GEN_CMD_FULL), 1000,
+ CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "failed to get available command FIFO\n");
return ret;
}
- dsi_write(dsi, DSI_GEN_HDR, hdr_val);
+ regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val);
mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
- ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
- val, (val & mask) == mask,
- 1000, CMD_PKT_STATUS_TIMEOUT_US);
+ ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+ val, (val & mask) == mask,
+ 1000, CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "failed to write command FIFO\n");
return ret;
@@ -409,18 +409,20 @@ static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
if (len < pld_data_bytes) {
word = 0;
memcpy(&word, tx_buf, len);
- dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
+ regmap_write(dsi->regs, DSI_GEN_PLD_DATA,
+ le32_to_cpu(word));
len = 0;
} else {
memcpy(&word, tx_buf, pld_data_bytes);
- dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word));
+ regmap_write(dsi->regs, DSI_GEN_PLD_DATA,
+ le32_to_cpu(word));
tx_buf += pld_data_bytes;
len -= pld_data_bytes;
}
- ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
- val, !(val & GEN_PLD_W_FULL), 1000,
- CMD_PKT_STATUS_TIMEOUT_US);
+ ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+ val, !(val & GEN_PLD_W_FULL),
+ 1000, CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev,
"failed to get available write payload FIFO\n");
@@ -441,9 +443,9 @@ static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
u32 val;
/* Wait end of the read operation */
- ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
- val, !(val & GEN_RD_CMD_BUSY),
- 1000, CMD_PKT_STATUS_TIMEOUT_US);
+ ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+ val, !(val & GEN_RD_CMD_BUSY),
+ 1000, CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "Timeout during read operation\n");
return ret;
@@ -451,15 +453,15 @@ static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
for (i = 0; i < len; i += 4) {
/* Read fifo must not be empty before all bytes are read */
- ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
- val, !(val & GEN_PLD_R_EMPTY),
- 1000, CMD_PKT_STATUS_TIMEOUT_US);
+ ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+ val, !(val & GEN_PLD_R_EMPTY),
+ 1000, CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "Read payload FIFO is empty\n");
return ret;
}
- val = dsi_read(dsi, DSI_GEN_PLD_DATA);
+ regmap_read(dsi->regs, DSI_GEN_PLD_DATA, &val);
for (j = 0; j < 4 && j + i < len; j++)
buf[i + j] = val >> (8 * j);
}
@@ -536,29 +538,29 @@ static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
}
#endif /* CONFIG_DEBUG_FS */
- dsi_write(dsi, DSI_VID_MODE_CFG, val);
+ regmap_write(dsi->regs, DSI_VID_MODE_CFG, val);
}
static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
unsigned long mode_flags)
{
- dsi_write(dsi, DSI_PWR_UP, RESET);
+ regmap_write(dsi->regs, DSI_PWR_UP, RESET);
if (mode_flags & MIPI_DSI_MODE_VIDEO) {
- dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
+ regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
dw_mipi_dsi_video_mode_config(dsi);
- dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
+ regmap_write(dsi->regs, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
} else {
- dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
+ regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_CMD_MODE);
}
- dsi_write(dsi, DSI_PWR_UP, POWERUP);
+ regmap_write(dsi->regs, DSI_PWR_UP, POWERUP);
}
static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
{
- dsi_write(dsi, DSI_PWR_UP, RESET);
- dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ);
+ regmap_write(dsi->regs, DSI_PWR_UP, RESET);
+ regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_RSTZ);
}
static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
@@ -573,14 +575,14 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
*/
u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1;
- dsi_write(dsi, DSI_PWR_UP, RESET);
+ regmap_write(dsi->regs, DSI_PWR_UP, RESET);
/*
* TODO dw drv improvements
* timeout clock division should be computed with the
* high speed transmission counter timeout and byte lane...
*/
- dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
+ regmap_write(dsi->regs, DSI_CLKMGR_CFG, TO_CLK_DIVISION(10) |
TX_ESC_CLK_DIVISION(esc_clk_division));
}
@@ -609,22 +611,22 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
if (mode->flags & DRM_MODE_FLAG_NHSYNC)
val |= HSYNC_ACTIVE_LOW;
- dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel));
- dsi_write(dsi, DSI_DPI_COLOR_CODING, color);
- dsi_write(dsi, DSI_DPI_CFG_POL, val);
+ regmap_write(dsi->regs, DSI_DPI_VCID, DPI_VCID(dsi->channel));
+ regmap_write(dsi->regs, DSI_DPI_COLOR_CODING, color);
+ regmap_write(dsi->regs, DSI_DPI_CFG_POL, val);
/*
* TODO dw drv improvements
* largest packet sizes during hfp or during vsa/vpb/vfp
* should be computed according to byte lane, lane number and only
* if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS)
*/
- dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
+ regmap_write(dsi->regs, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4)
| INVACT_LPCMD_TIME(4));
}
static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
{
- dsi_write(dsi, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
+ regmap_write(dsi->regs, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
}
static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
@@ -638,7 +640,7 @@ static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
* non-burst video modes, see dw_mipi_dsi_video_mode_config()...
*/
- dsi_write(dsi, DSI_VID_PKT_SIZE,
+ regmap_write(dsi->regs, DSI_VID_PKT_SIZE,
dw_mipi_is_dual_mode(dsi) ?
VID_PKT_SIZE(mode->hdisplay / 2) :
VID_PKT_SIZE(mode->hdisplay));
@@ -651,14 +653,15 @@ static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
* compute high speed transmission counter timeout according
* to the timeout clock division (TO_CLK_DIVISION) and byte lane...
*/
- dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
+ regmap_write(dsi->regs, DSI_TO_CNT_CFG,
+ HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
/*
* TODO dw drv improvements
* the Bus-Turn-Around Timeout Counter should be computed
* according to byte lane...
*/
- dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00);
- dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
+ regmap_write(dsi->regs, DSI_BTA_TO_CNT, 0xd00);
+ regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_CMD_MODE);
}
/* Get lane byte clock cycles. */
@@ -692,13 +695,13 @@ static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
* computations below may be improved...
*/
lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
- dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc);
+ regmap_write(dsi->regs, DSI_VID_HLINE_TIME, lbcc);
lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
- dsi_write(dsi, DSI_VID_HSA_TIME, lbcc);
+ regmap_write(dsi->regs, DSI_VID_HSA_TIME, lbcc);
lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
- dsi_write(dsi, DSI_VID_HBP_TIME, lbcc);
+ regmap_write(dsi->regs, DSI_VID_HBP_TIME, lbcc);
}
static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
@@ -711,17 +714,16 @@ static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
vfp = mode->vsync_start - mode->vdisplay;
vbp = mode->vtotal - mode->vsync_end;
- dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive);
- dsi_write(dsi, DSI_VID_VSA_LINES, vsa);
- dsi_write(dsi, DSI_VID_VFP_LINES, vfp);
- dsi_write(dsi, DSI_VID_VBP_LINES, vbp);
+ regmap_write(dsi->regs, DSI_VID_VACTIVE_LINES, vactive);
+ regmap_write(dsi->regs, DSI_VID_VSA_LINES, vsa);
+ regmap_write(dsi->regs, DSI_VID_VFP_LINES, vfp);
+ regmap_write(dsi->regs, DSI_VID_VBP_LINES, vbp);
}
static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
{
const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops;
struct dw_mipi_dsi_dphy_timing timing;
- u32 hw_version;
int ret;
ret = phy_ops->get_timing(dsi->plat_data->priv_data,
@@ -737,23 +739,22 @@ static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
* DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
*/
- hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
-
- if (hw_version >= HWVER_131) {
- dsi_write(dsi, DSI_PHY_TMR_CFG,
- PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
- PHY_LP2HS_TIME_V131(timing.data_lp2hs));
- dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000));
+ if (dsi->hw_version >= HWVER_131) {
+ regmap_write(dsi->regs, DSI_PHY_TMR_CFG,
+ PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
+ PHY_LP2HS_TIME_V131(timing.data_lp2hs));
+ regmap_write(dsi->regs, DSI_PHY_TMR_RD_CFG,
+ MAX_RD_TIME_V131(10000));
} else {
- dsi_write(dsi, DSI_PHY_TMR_CFG,
- PHY_HS2LP_TIME(timing.data_hs2lp) |
- PHY_LP2HS_TIME(timing.data_lp2hs) |
- MAX_RD_TIME(10000));
+ regmap_write(dsi->regs, DSI_PHY_TMR_CFG,
+ PHY_HS2LP_TIME(timing.data_hs2lp) |
+ PHY_LP2HS_TIME(timing.data_lp2hs) |
+ MAX_RD_TIME(10000));
}
- dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG,
- PHY_CLKHS2LP_TIME(timing.clk_hs2lp) |
- PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
+ regmap_write(dsi->regs, DSI_PHY_TMR_LPCLK_CFG,
+ PHY_CLKHS2LP_TIME(timing.clk_hs2lp) |
+ PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
}
static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
@@ -763,18 +764,18 @@ static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
* stop wait time should be the maximum between host dsi
* and panel stop wait times
*/
- dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) |
- N_LANES(dsi->lanes));
+ regmap_write(dsi->regs, DSI_PHY_IF_CFG,
+ PHY_STOP_WAIT_TIME(0x20) | N_LANES(dsi->lanes));
}
static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
{
/* Clear PHY state */
- dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
- | PHY_RSTZ | PHY_SHUTDOWNZ);
- dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
- dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
- dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
+ regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
+ | PHY_RSTZ | PHY_SHUTDOWNZ);
+ regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
+ regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
+ regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
}
static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
@@ -782,27 +783,30 @@ static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
u32 val;
int ret;
- dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
- PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
+ regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
+ PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
- ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
- val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US);
+ ret = regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS,
+ val, val & PHY_LOCK,
+ 1000, PHY_STATUS_TIMEOUT_US);
if (ret)
DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
- ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
- val, val & PHY_STOP_STATE_CLK_LANE, 1000,
- PHY_STATUS_TIMEOUT_US);
+ ret = regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS,
+ val, val & PHY_STOP_STATE_CLK_LANE, 1000,
+ PHY_STATUS_TIMEOUT_US);
if (ret)
DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
}
static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
{
- dsi_read(dsi, DSI_INT_ST0);
- dsi_read(dsi, DSI_INT_ST1);
- dsi_write(dsi, DSI_INT_MSK0, 0);
- dsi_write(dsi, DSI_INT_MSK1, 0);
+ u32 val;
+
+ regmap_read(dsi->regs, DSI_INT_ST0, &val);
+ regmap_read(dsi->regs, DSI_INT_ST1, &val);
+ regmap_write(dsi->regs, DSI_INT_MSK0, 0);
+ regmap_write(dsi->regs, DSI_INT_MSK1, 0);
}
static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
@@ -989,6 +993,18 @@ static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) { }
#endif /* CONFIG_DEBUG_FS */
+static int dw_mipi_dsi_get_hw_version(struct dw_mipi_dsi *dsi)
+{
+ regmap_read(dsi->regs, DSI_VERSION, &dsi->hw_version);
+ dsi->hw_version &= VERSION;
+ if (!dsi->hw_version) {
+ dev_err(dsi->dev,
+ "Failed to read DSI version. Is pclk enabled?\n");
+ return -ENODEV;
+ }
+ return 0;
+}
+
static struct dw_mipi_dsi *
__dw_mipi_dsi_probe(struct platform_device *pdev,
const struct dw_mipi_dsi_plat_data *plat_data)
@@ -1020,6 +1036,14 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
dsi->base = plat_data->base;
}
+ dsi->regs = devm_regmap_init_mmio(dev, dsi->base,
+ &dw_mipi_dsi_regmap_cfg);
+ if (IS_ERR(dsi->regs)) {
+ ret = PTR_ERR(dsi->regs);
+ DRM_ERROR("Failed to create DW MIPI DSI regmap: %d\n", ret);
+ return ERR_PTR(ret);
+ }
+
dsi->pclk = devm_clk_get(dev, "pclk");
if (IS_ERR(dsi->pclk)) {
ret = PTR_ERR(dsi->pclk);
@@ -1055,6 +1079,12 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
clk_disable_unprepare(dsi->pclk);
}
+ ret = dw_mipi_dsi_get_hw_version(dsi);
+ if (ret) {
+ dev_err(dev, "Could not read HW version\n");
+ return ERR_PTR(ret);
+ }
+
dw_mipi_dsi_debugfs_init(dsi);
pm_runtime_enable(dev);
--
2.27.0
Register existence, address/offsets, field layouts, reserved bits and
so on differ between MIPI-DSI versions and between SoC vendor boards.
Despite these differences the hw IP and protocols are mostly the same
so the generic bridge can be made to compensate these differences.
The current Rockchip and STM drivers hardcoded a lot of their common
definitions in the bridge code because they're based on DSI v1.30 and
1.31 which are relatively close, but in order to support older/future
versions with more diverging layouts like the v1.01 present on imx6,
we abstract some of the register accesses via the regmap field APIs.
The bridge detects the DSI core version and initializes the required
regmap register layout. Other DSI versions / register layouts can
easily be added in the future by only changing the bridge code.
The platform drivers don't require any changes, DSI register layout
versioning will be handled transparently by the bridge, but if in
the future the regmap or layouts needs to be exposed to the drivres,
it could easily be done via plat_data or a new API in dw_mipi_dsi.h.
Suggested-by: Boris Brezillon <[email protected]>
Reviewed-by: Emil Velikov <[email protected]>
Tested-by: Adrian Pop <[email protected]>
Tested-by: Arnaud Ferraris <[email protected]>
Signed-off-by: Adrian Ratiu <[email protected]>
---
Changes since v5:
- Fix CONFIG_DEBUG_FS build (Adrian)
- Fix DRM_MODE_FLAG_* test negation (Adrian)
- Fixed cfg_phy_status range from [0,0] to [0,2]
- Replace do {} while(0) with GCC extension ({}) (Andrzej)
- Fixed payload no-op writes on STM devices (Adrian & Arnaud)
Changes since v4:
- Move regmap infrastructure logic to a separate commit (Ezequiel)
- Consolidate field infrastructure in this commit (Ezequiel)
- Move the dsi v1.01 layout logic to a separate commit (Ezequiel)
Changes since v2:
- Added const declarations to dw_mipi_dsi structs (Emil)
- Fixed commit tags (Emil)
Changes since v1:
- Moved register definitions & regmap initialization into bridge
module. Platform drivers get the regmap via plat_data after calling
the bridge probe (Emil).
---
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 499 ++++++++++++------
1 file changed, 347 insertions(+), 152 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 34b8668ae24ea..f453df4eb5072 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -31,6 +31,7 @@
#include <drm/drm_probe_helper.h>
#define HWVER_131 0x31333100 /* IP version 1.31 */
+#define HWVER_130 0x31333000 /* IP version 1.30 */
#define DSI_VERSION 0x00
#define VERSION GENMASK(31, 8)
@@ -47,7 +48,6 @@
#define DPI_VCID(vcid) ((vcid) & 0x3)
#define DSI_DPI_COLOR_CODING 0x10
-#define LOOSELY18_EN BIT(8)
#define DPI_COLOR_CODING_16BIT_1 0x0
#define DPI_COLOR_CODING_16BIT_2 0x1
#define DPI_COLOR_CODING_16BIT_3 0x2
@@ -56,11 +56,6 @@
#define DPI_COLOR_CODING_24BIT 0x5
#define DSI_DPI_CFG_POL 0x14
-#define COLORM_ACTIVE_LOW BIT(4)
-#define SHUTD_ACTIVE_LOW BIT(3)
-#define HSYNC_ACTIVE_LOW BIT(2)
-#define VSYNC_ACTIVE_LOW BIT(1)
-#define DATAEN_ACTIVE_LOW BIT(0)
#define DSI_DPI_LP_CMD_TIM 0x18
#define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16)
@@ -81,27 +76,19 @@
#define DSI_GEN_VCID 0x30
#define DSI_MODE_CFG 0x34
-#define ENABLE_VIDEO_MODE 0
-#define ENABLE_CMD_MODE BIT(0)
#define DSI_VID_MODE_CFG 0x38
-#define ENABLE_LOW_POWER (0x3f << 8)
-#define ENABLE_LOW_POWER_MASK (0x3f << 8)
+#define ENABLE_LOW_POWER 0x3f
+
#define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0
#define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1
#define VID_MODE_TYPE_BURST 0x2
-#define VID_MODE_TYPE_MASK 0x3
-#define VID_MODE_VPG_ENABLE BIT(16)
-#define VID_MODE_VPG_HORIZONTAL BIT(24)
#define DSI_VID_PKT_SIZE 0x3c
-#define VID_PKT_SIZE(p) ((p) & 0x3fff)
#define DSI_VID_NUM_CHUNKS 0x40
-#define VID_NUM_CHUNKS(c) ((c) & 0x1fff)
#define DSI_VID_NULL_SIZE 0x44
-#define VID_NULL_SIZE(b) ((b) & 0x1fff)
#define DSI_VID_HSA_TIME 0x48
#define DSI_VID_HBP_TIME 0x4c
@@ -125,7 +112,6 @@
#define GEN_SW_2P_TX_LP BIT(10)
#define GEN_SW_1P_TX_LP BIT(9)
#define GEN_SW_0P_TX_LP BIT(8)
-#define ACK_RQST_EN BIT(1)
#define TEAR_FX_EN BIT(0)
#define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \
@@ -154,8 +140,6 @@
#define GEN_CMD_EMPTY BIT(0)
#define DSI_TO_CNT_CFG 0x78
-#define HSTX_TO_CNT(p) (((p) & 0xffff) << 16)
-#define LPRX_TO_CNT(p) ((p) & 0xffff)
#define DSI_HS_RD_TO_CNT 0x7c
#define DSI_LP_RD_TO_CNT 0x80
@@ -164,52 +148,17 @@
#define DSI_BTA_TO_CNT 0x8c
#define DSI_LPCLK_CTRL 0x94
-#define AUTO_CLKLANE_CTRL BIT(1)
-#define PHY_TXREQUESTCLKHS BIT(0)
-
#define DSI_PHY_TMR_LPCLK_CFG 0x98
-#define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16)
-#define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff)
-
#define DSI_PHY_TMR_CFG 0x9c
-#define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24)
-#define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16)
-#define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff)
-#define PHY_HS2LP_TIME_V131(lbcc) (((lbcc) & 0x3ff) << 16)
-#define PHY_LP2HS_TIME_V131(lbcc) ((lbcc) & 0x3ff)
-
#define DSI_PHY_RSTZ 0xa0
-#define PHY_DISFORCEPLL 0
-#define PHY_ENFORCEPLL BIT(3)
-#define PHY_DISABLECLK 0
-#define PHY_ENABLECLK BIT(2)
-#define PHY_RSTZ 0
-#define PHY_UNRSTZ BIT(1)
-#define PHY_SHUTDOWNZ 0
-#define PHY_UNSHUTDOWNZ BIT(0)
-
#define DSI_PHY_IF_CFG 0xa4
-#define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8)
-#define N_LANES(n) (((n) - 1) & 0x3)
-
-#define DSI_PHY_ULPS_CTRL 0xa8
-#define DSI_PHY_TX_TRIGGERS 0xac
#define DSI_PHY_STATUS 0xb0
#define PHY_STOP_STATE_CLK_LANE BIT(2)
#define PHY_LOCK BIT(0)
#define DSI_PHY_TST_CTRL0 0xb4
-#define PHY_TESTCLK BIT(1)
-#define PHY_UNTESTCLK 0
-#define PHY_TESTCLR BIT(0)
-#define PHY_UNTESTCLR 0
-
#define DSI_PHY_TST_CTRL1 0xb8
-#define PHY_TESTEN BIT(16)
-#define PHY_UNTESTEN 0
-#define PHY_TESTDOUT(n) (((n) & 0xff) << 8)
-#define PHY_TESTDIN(n) ((n) & 0xff)
#define DSI_INT_ST0 0xbc
#define DSI_INT_ST1 0xc0
@@ -217,7 +166,6 @@
#define DSI_INT_MSK1 0xc8
#define DSI_PHY_TMR_RD_CFG 0xf4
-#define MAX_RD_TIME_V131(lbcc) ((lbcc) & 0x7fff)
#define PHY_STATUS_TIMEOUT_US 10000
#define CMD_PKT_STATUS_TIMEOUT_US 20000
@@ -250,6 +198,53 @@ struct dw_mipi_dsi {
struct dw_mipi_dsi *slave; /* dual-dsi slave ptr */
const struct dw_mipi_dsi_plat_data *plat_data;
+
+ struct regmap_field *field_dpi_18loosely_en;
+ struct regmap_field *field_dpi_color_coding;
+ struct regmap_field *field_dpi_vid;
+ struct regmap_field *field_dpi_vsync_active_low;
+ struct regmap_field *field_dpi_hsync_active_low;
+ struct regmap_field *field_cmd_mode_ack_rqst_en;
+ struct regmap_field *field_cmd_mode_all_lp_en;
+ struct regmap_field *field_cmd_mode_en;
+ struct regmap_field *field_cmd_pkt_status;
+ struct regmap_field *field_vid_mode_en;
+ struct regmap_field *field_vid_mode_type;
+ struct regmap_field *field_vid_mode_low_power;
+ struct regmap_field *field_vid_mode_vpg_en;
+ struct regmap_field *field_vid_mode_vpg_horiz;
+ struct regmap_field *field_vid_pkt_size;
+ struct regmap_field *field_vid_hsa_time;
+ struct regmap_field *field_vid_hbp_time;
+ struct regmap_field *field_vid_hline_time;
+ struct regmap_field *field_vid_vsa_time;
+ struct regmap_field *field_vid_vbp_time;
+ struct regmap_field *field_vid_vfp_time;
+ struct regmap_field *field_vid_vactive_time;
+ struct regmap_field *field_phy_txrequestclkhs;
+ struct regmap_field *field_phy_bta_time;
+ struct regmap_field *field_phy_max_rd_time;
+ struct regmap_field *field_phy_lp2hs_time;
+ struct regmap_field *field_phy_hs2lp_time;
+ struct regmap_field *field_phy_clklp2hs_time;
+ struct regmap_field *field_phy_clkhs2lp_time;
+ struct regmap_field *field_phy_testclr;
+ struct regmap_field *field_phy_unshutdownz;
+ struct regmap_field *field_phy_unrstz;
+ struct regmap_field *field_phy_enableclk;
+ struct regmap_field *field_phy_forcepll;
+ struct regmap_field *field_phy_nlanes;
+ struct regmap_field *field_phy_stop_wait_time;
+ struct regmap_field *field_phy_status;
+ struct regmap_field *field_pckhdl_cfg;
+ struct regmap_field *field_hstx_timeout_counter;
+ struct regmap_field *field_lprx_timeout_counter;
+ struct regmap_field *field_int_stat0;
+ struct regmap_field *field_int_stat1;
+ struct regmap_field *field_int_mask0;
+ struct regmap_field *field_int_mask1;
+ struct regmap_field *field_gen_hdr;
+ struct regmap_field *field_gen_payload;
};
static const struct regmap_config dw_mipi_dsi_regmap_cfg = {
@@ -259,6 +254,111 @@ static const struct regmap_config dw_mipi_dsi_regmap_cfg = {
.name = "dw-mipi-dsi",
};
+struct dw_mipi_dsi_variant {
+ /* Regmap field configs for DSI adapter */
+ struct reg_field cfg_dpi_18loosely_en;
+ struct reg_field cfg_dpi_color_coding;
+ struct reg_field cfg_dpi_vid;
+ struct reg_field cfg_dpi_vsync_active_low;
+ struct reg_field cfg_dpi_hsync_active_low;
+ struct reg_field cfg_cmd_mode_en;
+ struct reg_field cfg_cmd_mode_ack_rqst_en;
+ struct reg_field cfg_cmd_mode_all_lp_en;
+ struct reg_field cfg_cmd_pkt_status;
+ struct reg_field cfg_vid_mode_en;
+ struct reg_field cfg_vid_mode_type;
+ struct reg_field cfg_vid_mode_low_power;
+ struct reg_field cfg_vid_mode_vpg_en;
+ struct reg_field cfg_vid_mode_vpg_horiz;
+ struct reg_field cfg_vid_pkt_size;
+ struct reg_field cfg_vid_hsa_time;
+ struct reg_field cfg_vid_hbp_time;
+ struct reg_field cfg_vid_hline_time;
+ struct reg_field cfg_vid_vsa_time;
+ struct reg_field cfg_vid_vbp_time;
+ struct reg_field cfg_vid_vfp_time;
+ struct reg_field cfg_vid_vactive_time;
+ struct reg_field cfg_phy_txrequestclkhs;
+ struct reg_field cfg_phy_bta_time;
+ struct reg_field cfg_phy_max_rd_time;
+ struct reg_field cfg_phy_lp2hs_time;
+ struct reg_field cfg_phy_hs2lp_time;
+ struct reg_field cfg_phy_max_rd_time_v131;
+ struct reg_field cfg_phy_lp2hs_time_v131;
+ struct reg_field cfg_phy_hs2lp_time_v131;
+ struct reg_field cfg_phy_clklp2hs_time;
+ struct reg_field cfg_phy_clkhs2lp_time;
+ struct reg_field cfg_phy_testclr;
+ struct reg_field cfg_phy_unshutdownz;
+ struct reg_field cfg_phy_unrstz;
+ struct reg_field cfg_phy_enableclk;
+ struct reg_field cfg_phy_forcepll;
+ struct reg_field cfg_phy_nlanes;
+ struct reg_field cfg_phy_stop_wait_time;
+ struct reg_field cfg_phy_status;
+ struct reg_field cfg_pckhdl_cfg;
+ struct reg_field cfg_hstx_timeout_counter;
+ struct reg_field cfg_lprx_timeout_counter;
+ struct reg_field cfg_int_stat0;
+ struct reg_field cfg_int_stat1;
+ struct reg_field cfg_int_mask0;
+ struct reg_field cfg_int_mask1;
+ struct reg_field cfg_gen_hdr;
+ struct reg_field cfg_gen_payload;
+};
+
+static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
+ .cfg_dpi_color_coding = REG_FIELD(DSI_DPI_COLOR_CODING, 0, 3),
+ .cfg_dpi_18loosely_en = REG_FIELD(DSI_DPI_COLOR_CODING, 8, 8),
+ .cfg_dpi_vid = REG_FIELD(DSI_DPI_VCID, 0, 2),
+ .cfg_dpi_vsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 1, 1),
+ .cfg_dpi_hsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 2, 2),
+ .cfg_cmd_mode_ack_rqst_en = REG_FIELD(DSI_CMD_MODE_CFG, 1, 1),
+ .cfg_cmd_mode_all_lp_en = REG_FIELD(DSI_CMD_MODE_CFG, 8, 24),
+ .cfg_cmd_mode_en = REG_FIELD(DSI_MODE_CFG, 0, 31),
+ .cfg_cmd_pkt_status = REG_FIELD(DSI_CMD_PKT_STATUS, 0, 31),
+ .cfg_vid_mode_en = REG_FIELD(DSI_MODE_CFG, 0, 31),
+ .cfg_vid_mode_type = REG_FIELD(DSI_VID_MODE_CFG, 0, 1),
+ .cfg_vid_mode_low_power = REG_FIELD(DSI_VID_MODE_CFG, 8, 13),
+ .cfg_vid_mode_vpg_en = REG_FIELD(DSI_VID_MODE_CFG, 16, 16),
+ .cfg_vid_mode_vpg_horiz = REG_FIELD(DSI_VID_MODE_CFG, 24, 24),
+ .cfg_vid_pkt_size = REG_FIELD(DSI_VID_PKT_SIZE, 0, 10),
+ .cfg_vid_hsa_time = REG_FIELD(DSI_VID_HSA_TIME, 0, 31),
+ .cfg_vid_hbp_time = REG_FIELD(DSI_VID_HBP_TIME, 0, 31),
+ .cfg_vid_hline_time = REG_FIELD(DSI_VID_HLINE_TIME, 0, 31),
+ .cfg_vid_vsa_time = REG_FIELD(DSI_VID_VSA_LINES, 0, 31),
+ .cfg_vid_vbp_time = REG_FIELD(DSI_VID_VBP_LINES, 0, 31),
+ .cfg_vid_vfp_time = REG_FIELD(DSI_VID_VFP_LINES, 0, 31),
+ .cfg_vid_vactive_time = REG_FIELD(DSI_VID_VACTIVE_LINES, 0, 31),
+ .cfg_phy_txrequestclkhs = REG_FIELD(DSI_LPCLK_CTRL, 0, 0),
+ .cfg_phy_bta_time = REG_FIELD(DSI_BTA_TO_CNT, 0, 31),
+ .cfg_phy_max_rd_time = REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
+ .cfg_phy_lp2hs_time = REG_FIELD(DSI_PHY_TMR_CFG, 16, 23),
+ .cfg_phy_hs2lp_time = REG_FIELD(DSI_PHY_TMR_CFG, 24, 31),
+ .cfg_phy_max_rd_time_v131 = REG_FIELD(DSI_PHY_TMR_RD_CFG, 0, 15),
+ .cfg_phy_lp2hs_time_v131 = REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
+ .cfg_phy_hs2lp_time_v131 = REG_FIELD(DSI_PHY_TMR_CFG, 16, 31),
+ .cfg_phy_clklp2hs_time = REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 0, 15),
+ .cfg_phy_clkhs2lp_time = REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 16, 31),
+ .cfg_phy_testclr = REG_FIELD(DSI_PHY_TST_CTRL0, 0, 0),
+ .cfg_phy_unshutdownz = REG_FIELD(DSI_PHY_RSTZ, 0, 0),
+ .cfg_phy_unrstz = REG_FIELD(DSI_PHY_RSTZ, 1, 1),
+ .cfg_phy_enableclk = REG_FIELD(DSI_PHY_RSTZ, 2, 2),
+ .cfg_phy_forcepll = REG_FIELD(DSI_PHY_RSTZ, 3, 3),
+ .cfg_phy_nlanes = REG_FIELD(DSI_PHY_IF_CFG, 0, 1),
+ .cfg_phy_stop_wait_time = REG_FIELD(DSI_PHY_IF_CFG, 8, 15),
+ .cfg_phy_status = REG_FIELD(DSI_PHY_STATUS, 0, 2),
+ .cfg_pckhdl_cfg = REG_FIELD(DSI_PCKHDL_CFG, 0, 4),
+ .cfg_hstx_timeout_counter = REG_FIELD(DSI_TO_CNT_CFG, 16, 31),
+ .cfg_lprx_timeout_counter = REG_FIELD(DSI_TO_CNT_CFG, 0, 15),
+ .cfg_int_stat0 = REG_FIELD(DSI_INT_ST0, 0, 31),
+ .cfg_int_stat1 = REG_FIELD(DSI_INT_ST1, 0, 31),
+ .cfg_int_mask0 = REG_FIELD(DSI_INT_MSK0, 0, 31),
+ .cfg_int_mask1 = REG_FIELD(DSI_INT_MSK1, 0, 31),
+ .cfg_gen_hdr = REG_FIELD(DSI_GEN_HDR, 0, 31),
+ .cfg_gen_payload = REG_FIELD(DSI_GEN_PLD_DATA, 0, 31),
+};
+
/*
* Check if either a link to a master or slave is present
*/
@@ -359,15 +459,22 @@ static void dw_mipi_message_config(struct dw_mipi_dsi *dsi,
const struct mipi_dsi_msg *msg)
{
bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM;
- u32 val = 0;
+ u32 cmd_mode_lp = 0;
+
+ switch (dsi->hw_version) {
+ case HWVER_130:
+ case HWVER_131:
+ cmd_mode_lp = CMD_MODE_ALL_LP;
+ break;
+ }
if (msg->flags & MIPI_DSI_MSG_REQ_ACK)
- val |= ACK_RQST_EN;
+ regmap_field_write(dsi->field_cmd_mode_ack_rqst_en, 1);
+
if (lpm)
- val |= CMD_MODE_ALL_LP;
+ regmap_field_write(dsi->field_cmd_mode_all_lp_en, cmd_mode_lp);
- regmap_write(dsi->regs, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS);
- regmap_write(dsi->regs, DSI_CMD_MODE_CFG, val);
+ regmap_field_write(dsi->field_phy_txrequestclkhs, lpm ? 0 : 1);
}
static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
@@ -375,18 +482,18 @@ static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
int ret;
u32 val, mask;
- ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
- val, !(val & GEN_CMD_FULL), 1000,
- CMD_PKT_STATUS_TIMEOUT_US);
+ ret = regmap_field_read_poll_timeout(dsi->field_cmd_pkt_status,
+ val, !(val & GEN_CMD_FULL),
+ 1000, CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "failed to get available command FIFO\n");
return ret;
}
- regmap_write(dsi->regs, DSI_GEN_HDR, hdr_val);
+ regmap_field_write(dsi->field_gen_hdr, hdr_val);
mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY;
- ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
+ ret = regmap_field_read_poll_timeout(dsi->field_cmd_pkt_status,
val, (val & mask) == mask,
1000, CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
@@ -409,20 +516,22 @@ static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
if (len < pld_data_bytes) {
word = 0;
memcpy(&word, tx_buf, len);
- regmap_write(dsi->regs, DSI_GEN_PLD_DATA,
- le32_to_cpu(word));
+ regmap_field_force_write(dsi->field_gen_payload,
+ le32_to_cpu(word));
len = 0;
} else {
memcpy(&word, tx_buf, pld_data_bytes);
- regmap_write(dsi->regs, DSI_GEN_PLD_DATA,
- le32_to_cpu(word));
+ regmap_field_force_write(dsi->field_gen_payload,
+ le32_to_cpu(word));
tx_buf += pld_data_bytes;
len -= pld_data_bytes;
}
- ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
- val, !(val & GEN_PLD_W_FULL),
- 1000, CMD_PKT_STATUS_TIMEOUT_US);
+ ret = regmap_field_read_poll_timeout(dsi->field_cmd_pkt_status,
+ val,
+ !(val & GEN_PLD_W_FULL),
+ 1000,
+ CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev,
"failed to get available write payload FIFO\n");
@@ -443,9 +552,9 @@ static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
u32 val;
/* Wait end of the read operation */
- ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
- val, !(val & GEN_RD_CMD_BUSY),
- 1000, CMD_PKT_STATUS_TIMEOUT_US);
+ ret = regmap_field_read_poll_timeout(dsi->field_cmd_pkt_status,
+ val, !(val & GEN_RD_CMD_BUSY),
+ 1000, CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "Timeout during read operation\n");
return ret;
@@ -453,15 +562,17 @@ static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi,
for (i = 0; i < len; i += 4) {
/* Read fifo must not be empty before all bytes are read */
- ret = regmap_read_poll_timeout(dsi->regs, DSI_CMD_PKT_STATUS,
- val, !(val & GEN_PLD_R_EMPTY),
- 1000, CMD_PKT_STATUS_TIMEOUT_US);
+ ret = regmap_field_read_poll_timeout(dsi->field_cmd_pkt_status,
+ val,
+ !(val & GEN_PLD_R_EMPTY),
+ 1000,
+ CMD_PKT_STATUS_TIMEOUT_US);
if (ret) {
dev_err(dsi->dev, "Read payload FIFO is empty\n");
return ret;
}
- regmap_read(dsi->regs, DSI_GEN_PLD_DATA, &val);
+ regmap_field_read(dsi->field_gen_payload, &val);
for (j = 0; j < 4 && j + i < len; j++)
buf[i + j] = val >> (8 * j);
}
@@ -515,30 +626,30 @@ static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = {
static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi)
{
- u32 val;
-
/*
* TODO dw drv improvements
* enabling low power is panel-dependent, we should use the
* panel configuration here...
*/
- val = ENABLE_LOW_POWER;
+ regmap_field_write(dsi->field_vid_mode_low_power, ENABLE_LOW_POWER);
if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST)
- val |= VID_MODE_TYPE_BURST;
+ regmap_field_write(dsi->field_vid_mode_type,
+ VID_MODE_TYPE_BURST);
else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE)
- val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES;
+ regmap_field_write(dsi->field_vid_mode_type,
+ VID_MODE_TYPE_NON_BURST_SYNC_PULSES);
else
- val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS;
+ regmap_field_write(dsi->field_vid_mode_type,
+ VID_MODE_TYPE_NON_BURST_SYNC_EVENTS);
#ifdef CONFIG_DEBUG_FS
if (dsi->vpg) {
- val |= VID_MODE_VPG_ENABLE;
- val |= dsi->vpg_horizontal ? VID_MODE_VPG_HORIZONTAL : 0;
+ regmap_field_write(dsi->field_vid_mode_vpg_en, 1);
+ regmap_field_write(dsi->field_vid_mode_vpg_horiz,
+ dsi->vpg_horizontal ? 1 : 0);
}
#endif /* CONFIG_DEBUG_FS */
-
- regmap_write(dsi->regs, DSI_VID_MODE_CFG, val);
}
static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
@@ -547,11 +658,13 @@ static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
regmap_write(dsi->regs, DSI_PWR_UP, RESET);
if (mode_flags & MIPI_DSI_MODE_VIDEO) {
- regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_VIDEO_MODE);
+ regmap_field_write(dsi->field_cmd_mode_en, 0);
+
dw_mipi_dsi_video_mode_config(dsi);
- regmap_write(dsi->regs, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS);
+
+ regmap_field_write(dsi->field_phy_txrequestclkhs, 1);
} else {
- regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_CMD_MODE);
+ regmap_field_write(dsi->field_cmd_mode_en, 1);
}
regmap_write(dsi->regs, DSI_PWR_UP, POWERUP);
@@ -560,7 +673,7 @@ static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi,
static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi)
{
regmap_write(dsi->regs, DSI_PWR_UP, RESET);
- regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_RSTZ);
+ regmap_field_write(dsi->field_phy_unrstz, 0);
}
static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
@@ -589,14 +702,15 @@ static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi)
static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
const struct drm_display_mode *mode)
{
- u32 val = 0, color = 0;
+ u32 color = 0;
switch (dsi->format) {
case MIPI_DSI_FMT_RGB888:
color = DPI_COLOR_CODING_24BIT;
break;
case MIPI_DSI_FMT_RGB666:
- color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN;
+ color = DPI_COLOR_CODING_18BIT_2;
+ regmap_field_write(dsi->field_dpi_18loosely_en, 1);
break;
case MIPI_DSI_FMT_RGB666_PACKED:
color = DPI_COLOR_CODING_18BIT_1;
@@ -606,14 +720,14 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
break;
}
+ regmap_field_write(dsi->field_dpi_vid, DPI_VCID(dsi->channel));
+ regmap_field_write(dsi->field_dpi_color_coding, color);
+
if (mode->flags & DRM_MODE_FLAG_NVSYNC)
- val |= VSYNC_ACTIVE_LOW;
+ regmap_field_write(dsi->field_dpi_vsync_active_low, 1);
if (mode->flags & DRM_MODE_FLAG_NHSYNC)
- val |= HSYNC_ACTIVE_LOW;
+ regmap_field_write(dsi->field_dpi_hsync_active_low, 1);
- regmap_write(dsi->regs, DSI_DPI_VCID, DPI_VCID(dsi->channel));
- regmap_write(dsi->regs, DSI_DPI_COLOR_CODING, color);
- regmap_write(dsi->regs, DSI_DPI_CFG_POL, val);
/*
* TODO dw drv improvements
* largest packet sizes during hfp or during vsa/vpb/vfp
@@ -626,7 +740,8 @@ static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi,
static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi)
{
- regmap_write(dsi->regs, DSI_PCKHDL_CFG, CRC_RX_EN | ECC_RX_EN | BTA_EN);
+ regmap_field_write(dsi->field_pckhdl_cfg,
+ CRC_RX_EN | ECC_RX_EN | BTA_EN);
}
static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
@@ -639,11 +754,9 @@ static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi,
* DSI_VNPCR.NPSIZE... especially because this driver supports
* non-burst video modes, see dw_mipi_dsi_video_mode_config()...
*/
-
- regmap_write(dsi->regs, DSI_VID_PKT_SIZE,
- dw_mipi_is_dual_mode(dsi) ?
- VID_PKT_SIZE(mode->hdisplay / 2) :
- VID_PKT_SIZE(mode->hdisplay));
+ regmap_field_write(dsi->field_vid_pkt_size,
+ dw_mipi_is_dual_mode(dsi) ?
+ mode->hdisplay / 2 : mode->hdisplay);
}
static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
@@ -653,15 +766,17 @@ static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
* compute high speed transmission counter timeout according
* to the timeout clock division (TO_CLK_DIVISION) and byte lane...
*/
- regmap_write(dsi->regs, DSI_TO_CNT_CFG,
- HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000));
+ regmap_field_write(dsi->field_hstx_timeout_counter, 1000);
+ regmap_field_write(dsi->field_lprx_timeout_counter, 1000);
+
/*
* TODO dw drv improvements
* the Bus-Turn-Around Timeout Counter should be computed
* according to byte lane...
*/
- regmap_write(dsi->regs, DSI_BTA_TO_CNT, 0xd00);
- regmap_write(dsi->regs, DSI_MODE_CFG, ENABLE_CMD_MODE);
+ regmap_field_write(dsi->field_phy_bta_time, 0xd00);
+
+ regmap_field_write(dsi->field_cmd_mode_en, 1);
}
/* Get lane byte clock cycles. */
@@ -695,13 +810,13 @@ static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi,
* computations below may be improved...
*/
lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal);
- regmap_write(dsi->regs, DSI_VID_HLINE_TIME, lbcc);
+ regmap_field_write(dsi->field_vid_hline_time, lbcc);
lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa);
- regmap_write(dsi->regs, DSI_VID_HSA_TIME, lbcc);
+ regmap_field_write(dsi->field_vid_hsa_time, lbcc);
lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp);
- regmap_write(dsi->regs, DSI_VID_HBP_TIME, lbcc);
+ regmap_field_write(dsi->field_vid_hbp_time, lbcc);
}
static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
@@ -714,10 +829,10 @@ static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi,
vfp = mode->vsync_start - mode->vdisplay;
vbp = mode->vtotal - mode->vsync_end;
- regmap_write(dsi->regs, DSI_VID_VACTIVE_LINES, vactive);
- regmap_write(dsi->regs, DSI_VID_VSA_LINES, vsa);
- regmap_write(dsi->regs, DSI_VID_VFP_LINES, vfp);
- regmap_write(dsi->regs, DSI_VID_VBP_LINES, vbp);
+ regmap_field_write(dsi->field_vid_vactive_time, vactive);
+ regmap_field_write(dsi->field_vid_vsa_time, vsa);
+ regmap_field_write(dsi->field_vid_vfp_time, vfp);
+ regmap_field_write(dsi->field_vid_vbp_time, vbp);
}
static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
@@ -738,23 +853,12 @@ static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi)
* note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with
* DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP)
*/
+ regmap_field_write(dsi->field_phy_lp2hs_time, timing.data_lp2hs);
+ regmap_field_write(dsi->field_phy_hs2lp_time, timing.data_hs2lp);
- if (dsi->hw_version >= HWVER_131) {
- regmap_write(dsi->regs, DSI_PHY_TMR_CFG,
- PHY_HS2LP_TIME_V131(timing.data_hs2lp) |
- PHY_LP2HS_TIME_V131(timing.data_lp2hs));
- regmap_write(dsi->regs, DSI_PHY_TMR_RD_CFG,
- MAX_RD_TIME_V131(10000));
- } else {
- regmap_write(dsi->regs, DSI_PHY_TMR_CFG,
- PHY_HS2LP_TIME(timing.data_hs2lp) |
- PHY_LP2HS_TIME(timing.data_lp2hs) |
- MAX_RD_TIME(10000));
- }
-
- regmap_write(dsi->regs, DSI_PHY_TMR_LPCLK_CFG,
- PHY_CLKHS2LP_TIME(timing.clk_hs2lp) |
- PHY_CLKLP2HS_TIME(timing.clk_lp2hs));
+ regmap_field_write(dsi->field_phy_max_rd_time, 10000);
+ regmap_field_write(dsi->field_phy_clkhs2lp_time, timing.clk_hs2lp);
+ regmap_field_write(dsi->field_phy_clklp2hs_time, timing.clk_lp2hs);
}
static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
@@ -764,18 +868,22 @@ static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi)
* stop wait time should be the maximum between host dsi
* and panel stop wait times
*/
- regmap_write(dsi->regs, DSI_PHY_IF_CFG,
- PHY_STOP_WAIT_TIME(0x20) | N_LANES(dsi->lanes));
+ regmap_field_write(dsi->field_phy_stop_wait_time, 0x20);
+ regmap_field_write(dsi->field_phy_nlanes, dsi->lanes - 1);
}
static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi)
{
/* Clear PHY state */
- regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK
- | PHY_RSTZ | PHY_SHUTDOWNZ);
- regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
- regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_TESTCLR);
- regmap_write(dsi->regs, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR);
+ regmap_field_write(dsi->field_phy_enableclk, 0);
+ regmap_field_write(dsi->field_phy_unrstz, 0);
+ regmap_field_write(dsi->field_phy_unshutdownz, 0);
+
+ regmap_field_write(dsi->field_phy_forcepll, 0);
+
+ regmap_field_write(dsi->field_phy_testclr, 0);
+ regmap_field_write(dsi->field_phy_testclr, 1);
+ regmap_field_write(dsi->field_phy_testclr, 0);
}
static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
@@ -783,18 +891,21 @@ static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
u32 val;
int ret;
- regmap_write(dsi->regs, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK |
- PHY_UNRSTZ | PHY_UNSHUTDOWNZ);
+ regmap_field_write(dsi->field_phy_enableclk, 1);
+ regmap_field_write(dsi->field_phy_unrstz, 1);
+ regmap_field_write(dsi->field_phy_unshutdownz, 1);
- ret = regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS,
- val, val & PHY_LOCK,
- 1000, PHY_STATUS_TIMEOUT_US);
+ regmap_field_write(dsi->field_phy_forcepll, 1);
+
+ ret = regmap_field_read_poll_timeout(dsi->field_phy_status,
+ val, val & PHY_LOCK,
+ 1000, PHY_STATUS_TIMEOUT_US);
if (ret)
DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
- ret = regmap_read_poll_timeout(dsi->regs, DSI_PHY_STATUS,
- val, val & PHY_STOP_STATE_CLK_LANE, 1000,
- PHY_STATUS_TIMEOUT_US);
+ ret = regmap_field_read_poll_timeout(dsi->field_phy_status,
+ val, val & PHY_STOP_STATE_CLK_LANE,
+ 1000, PHY_STATUS_TIMEOUT_US);
if (ret)
DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
}
@@ -803,10 +914,10 @@ static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi)
{
u32 val;
- regmap_read(dsi->regs, DSI_INT_ST0, &val);
- regmap_read(dsi->regs, DSI_INT_ST1, &val);
- regmap_write(dsi->regs, DSI_INT_MSK0, 0);
- regmap_write(dsi->regs, DSI_INT_MSK1, 0);
+ regmap_field_read(dsi->field_int_stat0, &val);
+ regmap_field_read(dsi->field_int_stat1, &val);
+ regmap_field_write(dsi->field_int_mask0, 0);
+ regmap_field_write(dsi->field_int_mask1, 0);
}
static void dw_mipi_dsi_bridge_post_disable(struct drm_bridge *bridge)
@@ -1005,6 +1116,84 @@ static int dw_mipi_dsi_get_hw_version(struct dw_mipi_dsi *dsi)
return 0;
}
+#define INIT_FIELD(f) INIT_FIELD_CFG(field_##f, cfg_##f)
+#define INIT_FIELD_CFG(f, conf) ({ \
+ dsi->f = devm_regmap_field_alloc(dsi->dev, dsi->regs, \
+ variant->conf); \
+ if (IS_ERR(dsi->f)) \
+ dev_warn(dsi->dev, "Ignoring regmap field " #f "\n"); })
+
+static int dw_mipi_dsi_regmap_fields_init(struct dw_mipi_dsi *dsi)
+{
+ const struct dw_mipi_dsi_variant *variant;
+
+ switch (dsi->hw_version) {
+ case HWVER_130:
+ case HWVER_131:
+ variant = &dw_mipi_dsi_v130_v131_layout;
+ break;
+ default:
+ DRM_ERROR("Unrecognized DSI host controller HW revision\n");
+ return -ENODEV;
+ }
+
+ INIT_FIELD(dpi_18loosely_en);
+ INIT_FIELD(dpi_vid);
+ INIT_FIELD(dpi_color_coding);
+ INIT_FIELD(dpi_vsync_active_low);
+ INIT_FIELD(dpi_hsync_active_low);
+ INIT_FIELD(cmd_mode_ack_rqst_en);
+ INIT_FIELD(cmd_mode_all_lp_en);
+ INIT_FIELD(cmd_mode_en);
+ INIT_FIELD(cmd_pkt_status);
+ INIT_FIELD(vid_mode_en);
+ INIT_FIELD(vid_mode_type);
+ INIT_FIELD(vid_mode_low_power);
+ INIT_FIELD(vid_pkt_size);
+ INIT_FIELD(vid_hsa_time);
+ INIT_FIELD(vid_hbp_time);
+ INIT_FIELD(vid_hline_time);
+ INIT_FIELD(vid_vsa_time);
+ INIT_FIELD(vid_vbp_time);
+ INIT_FIELD(vid_vfp_time);
+ INIT_FIELD(vid_vactive_time);
+ INIT_FIELD(phy_txrequestclkhs);
+ INIT_FIELD(phy_testclr);
+ INIT_FIELD(phy_unshutdownz);
+ INIT_FIELD(phy_unrstz);
+ INIT_FIELD(phy_enableclk);
+ INIT_FIELD(phy_nlanes);
+ INIT_FIELD(phy_stop_wait_time);
+ INIT_FIELD(phy_status);
+ INIT_FIELD(pckhdl_cfg);
+ INIT_FIELD(hstx_timeout_counter);
+ INIT_FIELD(lprx_timeout_counter);
+ INIT_FIELD(int_stat0);
+ INIT_FIELD(int_stat1);
+ INIT_FIELD(int_mask0);
+ INIT_FIELD(int_mask1);
+ INIT_FIELD(gen_hdr);
+ INIT_FIELD(gen_payload);
+ INIT_FIELD(phy_bta_time);
+ INIT_FIELD(vid_mode_vpg_en);
+ INIT_FIELD(vid_mode_vpg_horiz);
+ INIT_FIELD(phy_clklp2hs_time);
+ INIT_FIELD(phy_clkhs2lp_time);
+ INIT_FIELD(phy_forcepll);
+
+ if (dsi->hw_version == HWVER_131) {
+ INIT_FIELD_CFG(field_phy_max_rd_time, cfg_phy_max_rd_time_v131);
+ INIT_FIELD_CFG(field_phy_lp2hs_time, cfg_phy_lp2hs_time_v131);
+ INIT_FIELD_CFG(field_phy_hs2lp_time, cfg_phy_hs2lp_time_v131);
+ } else {
+ INIT_FIELD(phy_max_rd_time);
+ INIT_FIELD(phy_lp2hs_time);
+ INIT_FIELD(phy_hs2lp_time);
+ }
+
+ return 0;
+}
+
static struct dw_mipi_dsi *
__dw_mipi_dsi_probe(struct platform_device *pdev,
const struct dw_mipi_dsi_plat_data *plat_data)
@@ -1085,6 +1274,12 @@ __dw_mipi_dsi_probe(struct platform_device *pdev,
return ERR_PTR(ret);
}
+ ret = dw_mipi_dsi_regmap_fields_init(dsi);
+ if (ret) {
+ dev_err(dev, "Failed to init register layout map: %d\n", ret);
+ return ERR_PTR(ret);
+ }
+
dw_mipi_dsi_debugfs_init(dsi);
pm_runtime_enable(dev);
--
2.27.0
This provides an example DT binding for the MIPI DSI host controller
present on the i.MX6 SoC based on Synopsis DesignWare v1.01 IP.
Cc: Rob Herring <[email protected]>
Cc: Neil Armstrong <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Laurent Pinchart <[email protected]>
Cc: [email protected]
Tested-by: Adrian Pop <[email protected]>
Tested-by: Arnaud Ferraris <[email protected]>
Signed-off-by: Sjoerd Simons <[email protected]>
Signed-off-by: Martyn Welch <[email protected]>
Signed-off-by: Adrian Ratiu <[email protected]>
---
Changes since v8:
- Fixed small compatible string typo caught by checkpatch
- Added custom select for 'fsl,imx6-mipi-dsi' (Rob)
- Replaced additionalProperties -> unevaluatedProperties (Rob)
- Dropped all nodes not adding any new constraints apart from
the recently upstreamed snps,dw-mipi-dsi.yaml (Rob)
Changes since v7:
- Clarified port@0,1 descriptions, marked them as required and
added missing port@0 in example (Laurent)
Changes since v6:
- Added ref to the newly created snps,dw-mipi-dsi.yaml (Laurent)
- Moved *-cells properties outside patternProperties (Laurent)
- Removed the panel port documentation (Laurent)
- Wrapped lines at 80 chars, typo fixes, sort includes (Laurent)
Changes since v5:
- Fixed missing reg warning (Fabio)
- Updated dt-schema and fixed warnings (Rob)
Changes since v4:
- Fixed yaml binding to pass `make dt_binding_check dtbs_check`
and addressed received binding feedback (Rob)
Changes since v3:
- Added commit message (Neil)
- Converted to yaml format (Neil)
- Minor dt node + driver fixes (Rob)
- Added small panel example to the host controller binding
Changes since v2:
- Fixed commit tags (Emil)
---
.../display/imx/fsl,mipi-dsi-imx6.yaml | 112 ++++++++++++++++++
1 file changed, 112 insertions(+)
create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
diff --git a/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
new file mode 100644
index 0000000000000..86093729fd5f9
--- /dev/null
+++ b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/imx/fsl,mipi-dsi-imx6.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale i.MX6 DW MIPI DSI Host Controller
+
+maintainers:
+ - Adrian Ratiu <[email protected]>
+
+description: |
+ The i.MX6 DSI host controller is a Synopsys DesignWare MIPI DSI v1.01
+ IP block with a companion PHY IP.
+
+ These DT bindings follow the Synopsys DW MIPI DSI bindings defined in
+ Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt with
+ the following device-specific properties.
+
+allOf:
+ - $ref: ../bridge/snps,dw-mipi-dsi.yaml#
+
+# Need a custom select here or 'snps,dw-mipi-dsi' will match lots of nodes
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx6-mipi-dsi
+ required:
+ - compatible
+
+properties:
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ compatible:
+ items:
+ - const: fsl,imx6-mipi-dsi
+ - const: snps,dw-mipi-dsi
+
+ interrupts:
+ maxItems: 1
+
+ fsl,gpr:
+ description:
+ Phandle to the iomuxc-gpr region containing the multiplexer ctrl register.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+unevaluatedProperties: false
+
+required:
+ - "#address-cells"
+ - "#size-cells"
+ - compatible
+ - interrupts
+
+examples:
+ - |+
+ #include <dt-bindings/clock/imx6qdl-clock.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ dsi: dsi@21e0000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "fsl,imx6-mipi-dsi", "snps,dw-mipi-dsi";
+ reg = <0x021e0000 0x4000>;
+ interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,gpr = <&gpr>;
+ clocks = <&clks IMX6QDL_CLK_MIPI_CORE_CFG>,
+ <&clks IMX6QDL_CLK_MIPI_IPG>;
+ clock-names = "ref", "pclk";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ mipi_mux_0: endpoint {
+ remote-endpoint = <&ipu1_di0_mipi>;
+ };
+ };
+ port@1 {
+ reg = <1>;
+ dsi_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+
+ panel@0 {
+ compatible = "sharp,ls032b3sx01";
+ reg = <0>;
+ reset-gpios = <&gpio6 8 GPIO_ACTIVE_LOW>;
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ port@0 {
+ reg = <0>;
+ panel_in: endpoint {
+ remote-endpoint = <&dsi_out>;
+ };
+ };
+ };
+ };
+ };
+
+...
--
2.27.0
The stm mipi-dsi platform driver added a version test in
commit fa6251a747b7 ("drm/stm: dsi: check hardware version")
so that HW revisions other than v1.3x get rejected. The rockchip
driver had no such check and just assumed register layouts are
v1.3x compatible.
Having such tests was a good idea because only v130/v131 layouts
were supported at the time, however since adding multiple layout
support in the bridge, the version is automatically checked for
all drivers, compatible layouts get picked and unsupported HW is
automatically rejected by the bridge, so there's no use keeping
the test in the stm driver.
The main reason prompting this change is that the stm driver
test immediately disabled the peripheral clock after reading
the version, making the bridge read version 0x0 immediately
after in its own probe(), so we move the clock disabling after
the bridge does the version test.
Tested on STM32F769 and STM32MP1.
Cc: [email protected]
Cc: Emil Velikov <[email protected]>
Reported-by: Adrian Pop <[email protected]>
Tested-by: Adrian Pop <[email protected]>
Tested-by: Arnaud Ferraris <[email protected]>
Signed-off-by: Adrian Ratiu <[email protected]>
---
New in v6.
---
drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 16 +++++++---------
1 file changed, 7 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
index 2e1f2664495d0..45f67f8a5f6c8 100644
--- a/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
+++ b/drivers/gpu/drm/stm/dw_mipi_dsi-stm.c
@@ -396,26 +396,19 @@ static int dw_mipi_dsi_stm_probe(struct platform_device *pdev)
goto err_dsi_probe;
}
+ /* enable pclk so MMIO register values can be read, else reads == 0x0 */
ret = clk_prepare_enable(pclk);
if (ret) {
DRM_ERROR("%s: Failed to enable peripheral clk\n", __func__);
goto err_dsi_probe;
}
- dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
- clk_disable_unprepare(pclk);
-
- if (dsi->hw_version != HWVER_130 && dsi->hw_version != HWVER_131) {
- ret = -ENODEV;
- DRM_ERROR("bad dsi hardware version\n");
- goto err_dsi_probe;
- }
-
dw_mipi_dsi_stm_plat_data.base = dsi->base;
dw_mipi_dsi_stm_plat_data.priv_data = dsi;
platform_set_drvdata(pdev, dsi);
+ /* setup the bridge, this will also access MMIO registers via regmap */
dsi->dsi = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data);
if (IS_ERR(dsi->dsi)) {
ret = PTR_ERR(dsi->dsi);
@@ -423,6 +416,11 @@ static int dw_mipi_dsi_stm_probe(struct platform_device *pdev)
goto err_dsi_probe;
}
+ dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;
+
+ /* initial MMIO config done, disable clk to save power */
+ clk_disable_unprepare(pclk);
+
return 0;
err_dsi_probe:
--
2.27.0
This documents the longer-term plan to cleanup the dw-mipi-dsi bridge
based drivers after the regmap refactor and i.MX6 driver have landed.
The goal is to get the entire bridge logic in one place and continue
the refactorings under the drm/bridge tree.
Cc: Laurent Pinchart <[email protected]>
Cc: Boris Brezillon <[email protected]>
Cc: Sam Ravnborg <[email protected]>
Cc: Daniel Vetter <[email protected]>
Signed-off-by: Adrian Ratiu <[email protected]>
---
Documentation/gpu/todo.rst | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst
index 658b52f7ffc6c..2b142980a4b16 100644
--- a/Documentation/gpu/todo.rst
+++ b/Documentation/gpu/todo.rst
@@ -548,6 +548,31 @@ See drivers/gpu/drm/amd/display/TODO for tasks.
Contact: Harry Wentland, Alex Deucher
+Reorganize dw-mipi-dsi bridge-based host-controller drivers
+-----------------------------------------------------------
+
+The Synopsys DW MIPI DSI bridge is used by a number of SoC platform drivers
+(STM, Rockchip, i.MX) which don't cleanly encapsulate their bridge logic which
+gets split between the Synopsys bridge (drm/bridge/synopsys/dw-mipi-dsi.c) and
+platform drivers like drm/imx/dw_mipi_dsi-imx6.c by passing around the bridge
+configuration regmap, creating new bridges / daisy chaining in platform drivers,
+duplicating encoder creation, having too much encoder logic instead of using the
+simple encoder interface and so on.
+
+The goal of this rework is to make the dw-mipi-dsi driver a better encapsulated
+bridge by moving all bridge-related logic under drm/bridge, including the SoC
+bindings which chain to the core Synopsys code under drm/bridge/dw-mipi-dsi/
+from which they can be further consolidated and cleaned up.
+
+If this goal proves to be impossible then drm_bridge might not be the correct
+abstraction for these host controllers and unifying their logic into a helper
+library encapsulating a drm_encoder might be more desirable, in other words to
+move away from drm_bridge entirely.
+
+Contact: Adrian Ratiu, Daniel Vetter, Laurent Pinchart
+
+Level: Intermediate
+
Bootsplash
==========
--
2.27.0
According to the DSI Host Registers sections available in the IMX,
STM and RK ref manuals for 1.01, 1.30 and 1.31, the register fields
are smaller or bigger than what's coded in the driver, leading to
r/w in reserved spaces which might cause undefined behaviours.
Tested-by: Adrian Pop <[email protected]>
Tested-by: Arnaud Ferraris <[email protected]>
Signed-off-by: Adrian Ratiu <[email protected]>
---
New in v6.
---
drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 46 +++++++++----------
1 file changed, 23 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
index 1e47d40b5becb..d274216c5a7c2 100644
--- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
+++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
@@ -316,7 +316,7 @@ struct dw_mipi_dsi_variant {
static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
.cfg_dpi_color_coding = REG_FIELD(DSI_DPI_COLOR_CODING, 0, 3),
.cfg_dpi_18loosely_en = REG_FIELD(DSI_DPI_COLOR_CODING, 8, 8),
- .cfg_dpi_vid = REG_FIELD(DSI_DPI_VCID, 0, 2),
+ .cfg_dpi_vid = REG_FIELD(DSI_DPI_VCID, 0, 1),
.cfg_dpi_vsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 1, 1),
.cfg_dpi_hsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 2, 2),
.cfg_cmd_mode_ack_rqst_en = REG_FIELD(DSI_CMD_MODE_CFG, 1, 1),
@@ -325,29 +325,29 @@ static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
.cfg_cmd_mode_dcs_sw_sr_en = REG_FIELD(DSI_CMD_MODE_CFG, 16, 18),
.cfg_cmd_mode_dcs_lw_en = REG_FIELD(DSI_CMD_MODE_CFG, 19, 19),
.cfg_cmd_mode_max_rd_pkt_size = REG_FIELD(DSI_CMD_MODE_CFG, 24, 24),
- .cfg_cmd_mode_en = REG_FIELD(DSI_MODE_CFG, 0, 31),
- .cfg_cmd_pkt_status = REG_FIELD(DSI_CMD_PKT_STATUS, 0, 31),
- .cfg_vid_mode_en = REG_FIELD(DSI_MODE_CFG, 0, 31),
+ .cfg_cmd_mode_en = REG_FIELD(DSI_MODE_CFG, 0, 0),
+ .cfg_cmd_pkt_status = REG_FIELD(DSI_CMD_PKT_STATUS, 0, 6),
+ .cfg_vid_mode_en = REG_FIELD(DSI_MODE_CFG, 0, 0),
.cfg_vid_mode_type = REG_FIELD(DSI_VID_MODE_CFG, 0, 1),
.cfg_vid_mode_low_power = REG_FIELD(DSI_VID_MODE_CFG, 8, 13),
.cfg_vid_mode_vpg_en = REG_FIELD(DSI_VID_MODE_CFG, 16, 16),
.cfg_vid_mode_vpg_horiz = REG_FIELD(DSI_VID_MODE_CFG, 24, 24),
- .cfg_vid_pkt_size = REG_FIELD(DSI_VID_PKT_SIZE, 0, 10),
- .cfg_vid_hsa_time = REG_FIELD(DSI_VID_HSA_TIME, 0, 31),
- .cfg_vid_hbp_time = REG_FIELD(DSI_VID_HBP_TIME, 0, 31),
- .cfg_vid_hline_time = REG_FIELD(DSI_VID_HLINE_TIME, 0, 31),
- .cfg_vid_vsa_time = REG_FIELD(DSI_VID_VSA_LINES, 0, 31),
- .cfg_vid_vbp_time = REG_FIELD(DSI_VID_VBP_LINES, 0, 31),
- .cfg_vid_vfp_time = REG_FIELD(DSI_VID_VFP_LINES, 0, 31),
- .cfg_vid_vactive_time = REG_FIELD(DSI_VID_VACTIVE_LINES, 0, 31),
+ .cfg_vid_pkt_size = REG_FIELD(DSI_VID_PKT_SIZE, 0, 13),
+ .cfg_vid_hsa_time = REG_FIELD(DSI_VID_HSA_TIME, 0, 11),
+ .cfg_vid_hbp_time = REG_FIELD(DSI_VID_HBP_TIME, 0, 11),
+ .cfg_vid_hline_time = REG_FIELD(DSI_VID_HLINE_TIME, 0, 14),
+ .cfg_vid_vsa_time = REG_FIELD(DSI_VID_VSA_LINES, 0, 9),
+ .cfg_vid_vbp_time = REG_FIELD(DSI_VID_VBP_LINES, 0, 9),
+ .cfg_vid_vfp_time = REG_FIELD(DSI_VID_VFP_LINES, 0, 9),
+ .cfg_vid_vactive_time = REG_FIELD(DSI_VID_VACTIVE_LINES, 0, 13),
.cfg_phy_txrequestclkhs = REG_FIELD(DSI_LPCLK_CTRL, 0, 0),
- .cfg_phy_bta_time = REG_FIELD(DSI_BTA_TO_CNT, 0, 31),
- .cfg_phy_max_rd_time = REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
+ .cfg_phy_bta_time = REG_FIELD(DSI_BTA_TO_CNT, 0, 15),
+ .cfg_phy_max_rd_time = REG_FIELD(DSI_PHY_TMR_CFG, 0, 14),
.cfg_phy_lp2hs_time = REG_FIELD(DSI_PHY_TMR_CFG, 16, 23),
.cfg_phy_hs2lp_time = REG_FIELD(DSI_PHY_TMR_CFG, 24, 31),
- .cfg_phy_max_rd_time_v131 = REG_FIELD(DSI_PHY_TMR_RD_CFG, 0, 15),
- .cfg_phy_lp2hs_time_v131 = REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
- .cfg_phy_hs2lp_time_v131 = REG_FIELD(DSI_PHY_TMR_CFG, 16, 31),
+ .cfg_phy_max_rd_time_v131 = REG_FIELD(DSI_PHY_TMR_RD_CFG, 0, 14),
+ .cfg_phy_lp2hs_time_v131 = REG_FIELD(DSI_PHY_TMR_CFG, 0, 9),
+ .cfg_phy_hs2lp_time_v131 = REG_FIELD(DSI_PHY_TMR_CFG, 16, 25),
.cfg_phy_clklp2hs_time = REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 0, 15),
.cfg_phy_clkhs2lp_time = REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 16, 31),
.cfg_phy_testclr = REG_FIELD(DSI_PHY_TST_CTRL0, 0, 0),
@@ -361,11 +361,11 @@ static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
.cfg_pckhdl_cfg = REG_FIELD(DSI_PCKHDL_CFG, 0, 4),
.cfg_hstx_timeout_counter = REG_FIELD(DSI_TO_CNT_CFG, 16, 31),
.cfg_lprx_timeout_counter = REG_FIELD(DSI_TO_CNT_CFG, 0, 15),
- .cfg_int_stat0 = REG_FIELD(DSI_INT_ST0, 0, 31),
- .cfg_int_stat1 = REG_FIELD(DSI_INT_ST1, 0, 31),
- .cfg_int_mask0 = REG_FIELD(DSI_INT_MSK0, 0, 31),
- .cfg_int_mask1 = REG_FIELD(DSI_INT_MSK1, 0, 31),
- .cfg_gen_hdr = REG_FIELD(DSI_GEN_HDR, 0, 31),
+ .cfg_int_stat0 = REG_FIELD(DSI_INT_ST0, 0, 20),
+ .cfg_int_stat1 = REG_FIELD(DSI_INT_ST1, 0, 12),
+ .cfg_int_mask0 = REG_FIELD(DSI_INT_MSK0, 0, 20),
+ .cfg_int_mask1 = REG_FIELD(DSI_INT_MSK1, 0, 12),
+ .cfg_gen_hdr = REG_FIELD(DSI_GEN_HDR, 0, 23),
.cfg_gen_payload = REG_FIELD(DSI_GEN_PLD_DATA, 0, 31),
};
@@ -382,7 +382,7 @@ static const struct dw_mipi_dsi_variant dw_mipi_dsi_v101_layout = {
.cfg_cmd_mode_gen_lw_en = REG_FIELD(DSI_CMD_MODE_CFG, 11, 11),
.cfg_cmd_mode_dcs_lw_en = REG_FIELD(DSI_CMD_MODE_CFG, 12, 12),
.cfg_cmd_mode_ack_rqst_en = REG_FIELD(DSI_CMD_MODE_CFG_V101, 13, 13),
- .cfg_cmd_pkt_status = REG_FIELD(DSI_CMD_PKT_STATUS_V101, 0, 14),
+ .cfg_cmd_pkt_status = REG_FIELD(DSI_CMD_PKT_STATUS_V101, 0, 6),
.cfg_vid_mode_en = REG_FIELD(DSI_VID_MODE_CFG_V101, 0, 0),
.cfg_vid_mode_type = REG_FIELD(DSI_VID_MODE_CFG_V101, 1, 2),
.cfg_vid_mode_low_power = REG_FIELD(DSI_VID_MODE_CFG_V101, 3, 8),
--
2.27.0
Now that we have a proper driver for the imx6 mipi dsi host controller
we can fill in the missing properties to get it working.
Cc: Laurent Pinchart <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: [email protected]
Signed-off-by: Adrian Ratiu <[email protected]>
---
New in v8.
---
arch/arm/boot/dts/imx6qdl.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 7eec1122e5d74..d2f4fdfe4a252 100644
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -1222,7 +1222,15 @@ mipi_csi: mipi@21dc000 {
};
mipi_dsi: mipi@21e0000 {
+ compatible = "fsl,imx6-mipi-dsi", "snps,dw-mipi-dsi";
+ #address-cells = <1>;
+ #size-cells = <0>;
reg = <0x021e0000 0x4000>;
+ interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+ fsl,gpr = <&gpr>;
+ clocks = <&clks IMX6QDL_CLK_MIPI_CORE_CFG>,
+ <&clks IMX6QDL_CLK_MIPI_IPG>;
+ clock-names = "ref", "pclk";
status = "disabled";
ports {
--
2.27.0
Hi Adrian,
thanks for the pach: tested on stm32mp1.
Tested-by: Yannick Fertré <[email protected]>
On 6/9/20 7:49 PM, Adrian Ratiu wrote:
> According to the DSI Host Registers sections available in the IMX,
> STM and RK ref manuals for 1.01, 1.30 and 1.31, the register fields
> are smaller or bigger than what's coded in the driver, leading to
> r/w in reserved spaces which might cause undefined behaviours.
>
> Tested-by: Adrian Pop <[email protected]>
> Tested-by: Arnaud Ferraris <[email protected]>
> Signed-off-by: Adrian Ratiu <[email protected]>
> ---
> New in v6.
> ---
> drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 46 +++++++++----------
> 1 file changed, 23 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> index 1e47d40b5becb..d274216c5a7c2 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> @@ -316,7 +316,7 @@ struct dw_mipi_dsi_variant {
> static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
> .cfg_dpi_color_coding = REG_FIELD(DSI_DPI_COLOR_CODING, 0, 3),
> .cfg_dpi_18loosely_en = REG_FIELD(DSI_DPI_COLOR_CODING, 8, 8),
> - .cfg_dpi_vid = REG_FIELD(DSI_DPI_VCID, 0, 2),
> + .cfg_dpi_vid = REG_FIELD(DSI_DPI_VCID, 0, 1),
> .cfg_dpi_vsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 1, 1),
> .cfg_dpi_hsync_active_low = REG_FIELD(DSI_DPI_CFG_POL, 2, 2),
> .cfg_cmd_mode_ack_rqst_en = REG_FIELD(DSI_CMD_MODE_CFG, 1, 1),
> @@ -325,29 +325,29 @@ static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
> .cfg_cmd_mode_dcs_sw_sr_en = REG_FIELD(DSI_CMD_MODE_CFG, 16, 18),
> .cfg_cmd_mode_dcs_lw_en = REG_FIELD(DSI_CMD_MODE_CFG, 19, 19),
> .cfg_cmd_mode_max_rd_pkt_size = REG_FIELD(DSI_CMD_MODE_CFG, 24, 24),
> - .cfg_cmd_mode_en = REG_FIELD(DSI_MODE_CFG, 0, 31),
> - .cfg_cmd_pkt_status = REG_FIELD(DSI_CMD_PKT_STATUS, 0, 31),
> - .cfg_vid_mode_en = REG_FIELD(DSI_MODE_CFG, 0, 31),
> + .cfg_cmd_mode_en = REG_FIELD(DSI_MODE_CFG, 0, 0),
> + .cfg_cmd_pkt_status = REG_FIELD(DSI_CMD_PKT_STATUS, 0, 6),
> + .cfg_vid_mode_en = REG_FIELD(DSI_MODE_CFG, 0, 0),
> .cfg_vid_mode_type = REG_FIELD(DSI_VID_MODE_CFG, 0, 1),
> .cfg_vid_mode_low_power = REG_FIELD(DSI_VID_MODE_CFG, 8, 13),
> .cfg_vid_mode_vpg_en = REG_FIELD(DSI_VID_MODE_CFG, 16, 16),
> .cfg_vid_mode_vpg_horiz = REG_FIELD(DSI_VID_MODE_CFG, 24, 24),
> - .cfg_vid_pkt_size = REG_FIELD(DSI_VID_PKT_SIZE, 0, 10),
> - .cfg_vid_hsa_time = REG_FIELD(DSI_VID_HSA_TIME, 0, 31),
> - .cfg_vid_hbp_time = REG_FIELD(DSI_VID_HBP_TIME, 0, 31),
> - .cfg_vid_hline_time = REG_FIELD(DSI_VID_HLINE_TIME, 0, 31),
> - .cfg_vid_vsa_time = REG_FIELD(DSI_VID_VSA_LINES, 0, 31),
> - .cfg_vid_vbp_time = REG_FIELD(DSI_VID_VBP_LINES, 0, 31),
> - .cfg_vid_vfp_time = REG_FIELD(DSI_VID_VFP_LINES, 0, 31),
> - .cfg_vid_vactive_time = REG_FIELD(DSI_VID_VACTIVE_LINES, 0, 31),
> + .cfg_vid_pkt_size = REG_FIELD(DSI_VID_PKT_SIZE, 0, 13),
> + .cfg_vid_hsa_time = REG_FIELD(DSI_VID_HSA_TIME, 0, 11),
> + .cfg_vid_hbp_time = REG_FIELD(DSI_VID_HBP_TIME, 0, 11),
> + .cfg_vid_hline_time = REG_FIELD(DSI_VID_HLINE_TIME, 0, 14),
> + .cfg_vid_vsa_time = REG_FIELD(DSI_VID_VSA_LINES, 0, 9),
> + .cfg_vid_vbp_time = REG_FIELD(DSI_VID_VBP_LINES, 0, 9),
> + .cfg_vid_vfp_time = REG_FIELD(DSI_VID_VFP_LINES, 0, 9),
> + .cfg_vid_vactive_time = REG_FIELD(DSI_VID_VACTIVE_LINES, 0, 13),
> .cfg_phy_txrequestclkhs = REG_FIELD(DSI_LPCLK_CTRL, 0, 0),
> - .cfg_phy_bta_time = REG_FIELD(DSI_BTA_TO_CNT, 0, 31),
> - .cfg_phy_max_rd_time = REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
> + .cfg_phy_bta_time = REG_FIELD(DSI_BTA_TO_CNT, 0, 15),
> + .cfg_phy_max_rd_time = REG_FIELD(DSI_PHY_TMR_CFG, 0, 14),
> .cfg_phy_lp2hs_time = REG_FIELD(DSI_PHY_TMR_CFG, 16, 23),
> .cfg_phy_hs2lp_time = REG_FIELD(DSI_PHY_TMR_CFG, 24, 31),
> - .cfg_phy_max_rd_time_v131 = REG_FIELD(DSI_PHY_TMR_RD_CFG, 0, 15),
> - .cfg_phy_lp2hs_time_v131 = REG_FIELD(DSI_PHY_TMR_CFG, 0, 15),
> - .cfg_phy_hs2lp_time_v131 = REG_FIELD(DSI_PHY_TMR_CFG, 16, 31),
> + .cfg_phy_max_rd_time_v131 = REG_FIELD(DSI_PHY_TMR_RD_CFG, 0, 14),
> + .cfg_phy_lp2hs_time_v131 = REG_FIELD(DSI_PHY_TMR_CFG, 0, 9),
> + .cfg_phy_hs2lp_time_v131 = REG_FIELD(DSI_PHY_TMR_CFG, 16, 25),
> .cfg_phy_clklp2hs_time = REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 0, 15),
> .cfg_phy_clkhs2lp_time = REG_FIELD(DSI_PHY_TMR_LPCLK_CFG, 16, 31),
> .cfg_phy_testclr = REG_FIELD(DSI_PHY_TST_CTRL0, 0, 0),
> @@ -361,11 +361,11 @@ static const struct dw_mipi_dsi_variant dw_mipi_dsi_v130_v131_layout = {
> .cfg_pckhdl_cfg = REG_FIELD(DSI_PCKHDL_CFG, 0, 4),
> .cfg_hstx_timeout_counter = REG_FIELD(DSI_TO_CNT_CFG, 16, 31),
> .cfg_lprx_timeout_counter = REG_FIELD(DSI_TO_CNT_CFG, 0, 15),
> - .cfg_int_stat0 = REG_FIELD(DSI_INT_ST0, 0, 31),
> - .cfg_int_stat1 = REG_FIELD(DSI_INT_ST1, 0, 31),
> - .cfg_int_mask0 = REG_FIELD(DSI_INT_MSK0, 0, 31),
> - .cfg_int_mask1 = REG_FIELD(DSI_INT_MSK1, 0, 31),
> - .cfg_gen_hdr = REG_FIELD(DSI_GEN_HDR, 0, 31),
> + .cfg_int_stat0 = REG_FIELD(DSI_INT_ST0, 0, 20),
> + .cfg_int_stat1 = REG_FIELD(DSI_INT_ST1, 0, 12),
> + .cfg_int_mask0 = REG_FIELD(DSI_INT_MSK0, 0, 20),
> + .cfg_int_mask1 = REG_FIELD(DSI_INT_MSK1, 0, 12),
> + .cfg_gen_hdr = REG_FIELD(DSI_GEN_HDR, 0, 23),
> .cfg_gen_payload = REG_FIELD(DSI_GEN_PLD_DATA, 0, 31),
> };
>
> @@ -382,7 +382,7 @@ static const struct dw_mipi_dsi_variant dw_mipi_dsi_v101_layout = {
> .cfg_cmd_mode_gen_lw_en = REG_FIELD(DSI_CMD_MODE_CFG, 11, 11),
> .cfg_cmd_mode_dcs_lw_en = REG_FIELD(DSI_CMD_MODE_CFG, 12, 12),
> .cfg_cmd_mode_ack_rqst_en = REG_FIELD(DSI_CMD_MODE_CFG_V101, 13, 13),
> - .cfg_cmd_pkt_status = REG_FIELD(DSI_CMD_PKT_STATUS_V101, 0, 14),
> + .cfg_cmd_pkt_status = REG_FIELD(DSI_CMD_PKT_STATUS_V101, 0, 6),
> .cfg_vid_mode_en = REG_FIELD(DSI_VID_MODE_CFG_V101, 0, 0),
> .cfg_vid_mode_type = REG_FIELD(DSI_VID_MODE_CFG_V101, 1, 2),
> .cfg_vid_mode_low_power = REG_FIELD(DSI_VID_MODE_CFG_V101, 3, 8),
On Tue, Jun 09, 2020 at 08:49:53PM +0300, Adrian Ratiu wrote:
> This provides an example DT binding for the MIPI DSI host controller
It's not an example. It defines the exact binding for this peripheral.
> present on the i.MX6 SoC based on Synopsis DesignWare v1.01 IP.
>
> Cc: Rob Herring <[email protected]>
> Cc: Neil Armstrong <[email protected]>
> Cc: Fabio Estevam <[email protected]>
> Cc: Laurent Pinchart <[email protected]>
> Cc: [email protected]
> Tested-by: Adrian Pop <[email protected]>
> Tested-by: Arnaud Ferraris <[email protected]>
> Signed-off-by: Sjoerd Simons <[email protected]>
> Signed-off-by: Martyn Welch <[email protected]>
> Signed-off-by: Adrian Ratiu <[email protected]>
> ---
> Changes since v8:
> - Fixed small compatible string typo caught by checkpatch
> - Added custom select for 'fsl,imx6-mipi-dsi' (Rob)
> - Replaced additionalProperties -> unevaluatedProperties (Rob)
> - Dropped all nodes not adding any new constraints apart from
> the recently upstreamed snps,dw-mipi-dsi.yaml (Rob)
>
> Changes since v7:
> - Clarified port@0,1 descriptions, marked them as required and
> added missing port@0 in example (Laurent)
>
> Changes since v6:
> - Added ref to the newly created snps,dw-mipi-dsi.yaml (Laurent)
> - Moved *-cells properties outside patternProperties (Laurent)
> - Removed the panel port documentation (Laurent)
> - Wrapped lines at 80 chars, typo fixes, sort includes (Laurent)
>
> Changes since v5:
> - Fixed missing reg warning (Fabio)
> - Updated dt-schema and fixed warnings (Rob)
>
> Changes since v4:
> - Fixed yaml binding to pass `make dt_binding_check dtbs_check`
> and addressed received binding feedback (Rob)
>
> Changes since v3:
> - Added commit message (Neil)
> - Converted to yaml format (Neil)
> - Minor dt node + driver fixes (Rob)
> - Added small panel example to the host controller binding
>
> Changes since v2:
> - Fixed commit tags (Emil)
> ---
> .../display/imx/fsl,mipi-dsi-imx6.yaml | 112 ++++++++++++++++++
> 1 file changed, 112 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
>
> diff --git a/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
> new file mode 100644
> index 0000000000000..86093729fd5f9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
> @@ -0,0 +1,112 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/display/imx/fsl,mipi-dsi-imx6.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Freescale i.MX6 DW MIPI DSI Host Controller
> +
> +maintainers:
> + - Adrian Ratiu <[email protected]>
> +
> +description: |
> + The i.MX6 DSI host controller is a Synopsys DesignWare MIPI DSI v1.01
> + IP block with a companion PHY IP.
> +
> + These DT bindings follow the Synopsys DW MIPI DSI bindings defined in
> + Documentation/devicetree/bindings/display/bridge/dw_mipi_dsi.txt with
> + the following device-specific properties.
> +
> +allOf:
> + - $ref: ../bridge/snps,dw-mipi-dsi.yaml#
> +
> +# Need a custom select here or 'snps,dw-mipi-dsi' will match lots of nodes
> +select:
> + properties:
> + compatible:
> + contains:
> + enum:
> + - fsl,imx6-mipi-dsi
> + required:
> + - compatible
> +
> +properties:
> + '#address-cells':
> + const: 1
> +
> + '#size-cells':
> + const: 0
These 2 are covered by dsi-controller.yaml, so you can drop them.
Otherwise,
Reviewed-by: Rob Herring <[email protected]>
Hi Adrian,
On 09/06/2020 19:49, Adrian Ratiu wrote:
> [Re-submitting to cc dri-devel, sorry about the noise]
>
> Hello all,
>
> v9 cleanly applies on top of latest next-20200609 tree.
>
> v9 does not depend on other patches as the last binding doc has been merged.
>
> All feedback up to this point has been addressed. Specific details in
> individual patch changelogs.
>
> The biggest changes are the deprecation of the Synopsys DW bridge bind()
> API in favor of of_drm_find_bridge() and .attach callbacks, the addition
> of a TODO entry which outlines future planned bridge driver refactorings
> and a reordering of some i.MX 6 patches to appease checkpatch.
>
> The idea behind the TODO is to get this regmap and i.MX 6 driver merged
> and then do the rest of refactorings in-tree because it's easier and the
> refactorings themselves are out-of-scope of this series which is adding
> i.MX 6 support and is quite big already, so please, if there are more
> refactoring ideas, let's add them to the TODO doc. :) I intend to tackle
> those after this series is merged to avoid two complex inter-dependent
> simultaneous series.
This has been around here for a long time and you seem to have addressed all
the reviews.
>
> As always more testing is welcome especially on Rockchip and STM SoCs.
It has been tested on STM, but I'd like a feedback on RK platform before applying
the bridge parts.
Can the imx & stm patches be applied separately ?
Neil
>
> Big thank you to everyone who has contributed to this up to now,
> Adrian
>
> Adrian Ratiu (11):
> drm: bridge: dw_mipi_dsi: add initial regmap infrastructure
> drm: bridge: dw_mipi_dsi: abstract register access using reg_fields
> drm: bridge: dw_mipi_dsi: add dsi v1.01 support
> drm: bridge: dw_mipi_dsi: remove bind/unbind API
> dt-bindings: display: add i.MX6 MIPI DSI host controller doc
> ARM: dts: imx6qdl: add missing mipi dsi properties
> drm: imx: Add i.MX 6 MIPI DSI host platform driver
> drm: stm: dw-mipi-dsi: let the bridge handle the HW version check
> drm: bridge: dw-mipi-dsi: split low power cfg register into fields
> drm: bridge: dw-mipi-dsi: fix bad register field offsets
> Documentation: gpu: todo: Add dw-mipi-dsi consolidation plan
>
> .../display/imx/fsl,mipi-dsi-imx6.yaml | 112 +++
> Documentation/gpu/todo.rst | 25 +
> arch/arm/boot/dts/imx6qdl.dtsi | 8 +
> drivers/gpu/drm/bridge/synopsys/Kconfig | 1 +
> drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 713 ++++++++++++------
> drivers/gpu/drm/imx/Kconfig | 8 +
> drivers/gpu/drm/imx/Makefile | 1 +
> drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 399 ++++++++++
> .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 7 +-
> drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 16 +-
> 10 files changed, 1059 insertions(+), 231 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
> create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
>
Hi Neil,
On Mon, 29 Jun 2020, Neil Armstrong <[email protected]>
wrote:
> Hi Adrian,
>
> On 09/06/2020 19:49, Adrian Ratiu wrote:
>> [Re-submitting to cc dri-devel, sorry about the noise] Hello
>> all, v9 cleanly applies on top of latest next-20200609 tree.
>> v9 does not depend on other patches as the last binding doc has
>> been merged. All feedback up to this point has been
>> addressed. Specific details in individual patch changelogs.
>> The biggest changes are the deprecation of the Synopsys DW
>> bridge bind() API in favor of of_drm_find_bridge() and .attach
>> callbacks, the addition of a TODO entry which outlines future
>> planned bridge driver refactorings and a reordering of some
>> i.MX 6 patches to appease checkpatch. The idea behind the
>> TODO is to get this regmap and i.MX 6 driver merged and then do
>> the rest of refactorings in-tree because it's easier and the
>> refactorings themselves are out-of-scope of this series which
>> is adding i.MX 6 support and is quite big already, so please,
>> if there are more refactoring ideas, let's add them to the TODO
>> doc. :) I intend to tackle those after this series is merged to
>> avoid two complex inter-dependent simultaneous series.
>
> This has been around here for a long time and you seem to have
> addressed all the reviews.
>
>> As always more testing is welcome especially on Rockchip and
>> STM SoCs.
>
> It has been tested on STM, but I'd like a feedback on RK
> platform before applying the bridge parts.
>
> Can the imx & stm patches be applied separately ?
>
Yes the IMX and STM patches can be applied separately, they just
both depend on the common regmap patches.
The binding API removal change which directly touches RK can also
be applied separately, but unfortunately I do not have access to a
RK board with a DSI display to test it (or the bridge regmap logic
on RK btw...), I just "eye-balled" the RK code based on the public
docs and it LGTM.
> Neil
>
>>
>> Big thank you to everyone who has contributed to this up to now,
>> Adrian
>>
>> Adrian Ratiu (11):
>> drm: bridge: dw_mipi_dsi: add initial regmap infrastructure
>> drm: bridge: dw_mipi_dsi: abstract register access using reg_fields
>> drm: bridge: dw_mipi_dsi: add dsi v1.01 support
>> drm: bridge: dw_mipi_dsi: remove bind/unbind API
>> dt-bindings: display: add i.MX6 MIPI DSI host controller doc
>> ARM: dts: imx6qdl: add missing mipi dsi properties
>> drm: imx: Add i.MX 6 MIPI DSI host platform driver
>> drm: stm: dw-mipi-dsi: let the bridge handle the HW version check
>> drm: bridge: dw-mipi-dsi: split low power cfg register into fields
>> drm: bridge: dw-mipi-dsi: fix bad register field offsets
>> Documentation: gpu: todo: Add dw-mipi-dsi consolidation plan
>>
>> .../display/imx/fsl,mipi-dsi-imx6.yaml | 112 +++
>> Documentation/gpu/todo.rst | 25 +
>> arch/arm/boot/dts/imx6qdl.dtsi | 8 +
>> drivers/gpu/drm/bridge/synopsys/Kconfig | 1 +
>> drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 713 ++++++++++++------
>> drivers/gpu/drm/imx/Kconfig | 8 +
>> drivers/gpu/drm/imx/Makefile | 1 +
>> drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 399 ++++++++++
>> .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 7 +-
>> drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 16 +-
>> 10 files changed, 1059 insertions(+), 231 deletions(-)
>> create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
>> create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
>>
Hi Heiko,
Do you think someone can have a try of this patchset on a RK SoC ?
Thanks,
Neil
On 01/07/2020 08:35, Adrian Ratiu wrote:
> Hi Neil,
>
> On Mon, 29 Jun 2020, Neil Armstrong <[email protected]> wrote:
>> Hi Adrian,
>> On 09/06/2020 19:49, Adrian Ratiu wrote:
>>> [Re-submitting to cc dri-devel, sorry about the noise] Hello all, v9 cleanly applies on top of latest next-20200609 tree. v9 does not depend on other patches as the last binding doc has been merged. All feedback up to this point has been addressed. Specific details in individual patch changelogs. The biggest changes are the deprecation of the Synopsys DW bridge bind() API in favor of of_drm_find_bridge() and .attach callbacks, the addition of a TODO entry which outlines future planned bridge driver refactorings and a reordering of some i.MX 6 patches to appease checkpatch. The idea behind the TODO is to get this regmap and i.MX 6 driver merged and then do the rest of refactorings in-tree because it's easier and the refactorings themselves are out-of-scope of this series which is adding i.MX 6 support and is quite big already, so please, if there are more refactoring ideas, let's add them to the TODO doc. :) I intend to tackle those after this series is merged to
>>> avoid two complex inter-dependent simultaneous series.
>>
>> This has been around here for a long time and you seem to have addressed all the reviews.
>>> As always more testing is welcome especially on Rockchip and STM SoCs.
>>
>> It has been tested on STM, but I'd like a feedback on RK platform before applying the bridge parts.
>> Can the imx & stm patches be applied separately ?
>
> Yes the IMX and STM patches can be applied separately, they just both depend on the common regmap patches.
>
> The binding API removal change which directly touches RK can also be applied separately, but unfortunately I do not have access to a RK board with a DSI display to test it (or the bridge regmap logic on RK btw...), I just "eye-balled" the RK code based on the public docs and it LGTM.
>
>> Neil
>>
>>>
>>> Big thank you to everyone who has contributed to this up to now,
>>> Adrian
>>>
>>> Adrian Ratiu (11):
>>> drm: bridge: dw_mipi_dsi: add initial regmap infrastructure
>>> drm: bridge: dw_mipi_dsi: abstract register access using reg_fields
>>> drm: bridge: dw_mipi_dsi: add dsi v1.01 support
>>> drm: bridge: dw_mipi_dsi: remove bind/unbind API
>>> dt-bindings: display: add i.MX6 MIPI DSI host controller doc
>>> ARM: dts: imx6qdl: add missing mipi dsi properties
>>> drm: imx: Add i.MX 6 MIPI DSI host platform driver
>>> drm: stm: dw-mipi-dsi: let the bridge handle the HW version check
>>> drm: bridge: dw-mipi-dsi: split low power cfg register into fields
>>> drm: bridge: dw-mipi-dsi: fix bad register field offsets
>>> Documentation: gpu: todo: Add dw-mipi-dsi consolidation plan
>>>
>>> .../display/imx/fsl,mipi-dsi-imx6.yaml | 112 +++
>>> Documentation/gpu/todo.rst | 25 +
>>> arch/arm/boot/dts/imx6qdl.dtsi | 8 +
>>> drivers/gpu/drm/bridge/synopsys/Kconfig | 1 +
>>> drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 713 ++++++++++++------
>>> drivers/gpu/drm/imx/Kconfig | 8 +
>>> drivers/gpu/drm/imx/Makefile | 1 +
>>> drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 399 ++++++++++
>>> .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 7 +-
>>> drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 16 +-
>>> 10 files changed, 1059 insertions(+), 231 deletions(-)
>>> create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
>>> create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
>>>
Hi Adrian,
Am Dienstag, 9. Juni 2020, 19:49:48 CEST schrieb Adrian Ratiu:
> [Re-submitting to cc dri-devel, sorry about the noise]
>
> Hello all,
>
> v9 cleanly applies on top of latest next-20200609 tree.
at least it doesn't apply on top of current drm-misc-next for me
which I really don't understand.
Like patch 2/11 does
@@ -31,6 +31,7 @@
#include <drm/drm_probe_helper.h>
.
#define HWVER_131<----><------><------>0x31333100<---->/* IP version 1.31 */
+#define HWVER_130<----><------><------>0x31333000<---->/* IP version 1.30 */
.
#define DSI_VERSION<--><------><------>0x00
#define VERSION<------><------><------><------>GENMASK(31, 8)
where the file currently looks like
#include <drm/drm_atomic_helper.h>
#include <drm/drm_bridge.h>
#include <drm/drm_crtc.h>
#include <drm/drm_mipi_dsi.h>
#include <drm/drm_modes.h>
#include <drm/drm_of.h>
#include <drm/drm_print.h>
#define HWVER_131 0x31333100 /* IP version 1.31 */
#define DSI_VERSION 0x00
#define VERSION GENMASK(31, 8)
even in Linux-next
So I guess ideally rebase on top of drm-misc-next
Thanks
Heiko
Hi Heiko,
On Wed, 01 Jul 2020, Heiko Stübner <[email protected]> wrote:
> Hi Adrian,
>
> Am Dienstag, 9. Juni 2020, 19:49:48 CEST schrieb Adrian Ratiu:
>> [Re-submitting to cc dri-devel, sorry about the noise] Hello
>> all, v9 cleanly applies on top of latest next-20200609 tree.
>
> at least it doesn't apply on top of current drm-misc-next for me
> which I really don't understand.
>
> Like patch 2/11 does
>
> @@ -31,6 +31,7 @@
> #include <drm/drm_probe_helper.h>
> .
> #define HWVER_131<----><------><------>0x31333100<---->/* IP
> version 1.31 */
> +#define HWVER_130<----><------><------>0x31333000<---->/* IP
> version 1.30 */ .
> #define DSI_VERSION<--><------><------>0x00 #define
> VERSION<------><------><------><------>GENMASK(31, 8)
>
> where the file currently looks like
>
> #include <drm/drm_atomic_helper.h> #include <drm/drm_bridge.h>
> #include <drm/drm_crtc.h> #include <drm/drm_mipi_dsi.h> #include
> <drm/drm_modes.h> #include <drm/drm_of.h> #include
> <drm/drm_print.h>
>
> #define HWVER_131 0x31333100 /* IP
> version 1.31 */
>
> #define DSI_VERSION 0x00 #define VERSION
> GENMASK(31, 8)
>
> even in Linux-next
>
> So I guess ideally rebase on top of drm-misc-next
I will send a rebase on top of drm-misc-next soon (with the last
DTS nitpick fixed and the latest acks and reviewed-by tags added).
In the meantime I also found someone within Collabora who has a RK
with a DSI panel and found a bug (likely clock is not enabled
early enough to access the cfg registers to get the version for
regmap).
I'm super happy this is getting tested on RK, thank you!
>
>
> Thanks
> Heiko
Hi Neil,
On Wed, 2020-07-01 at 09:35 +0300, Adrian Ratiu wrote:
> Hi Neil,
>
> On Mon, 29 Jun 2020, Neil Armstrong <[email protected]>
> wrote:
> > Hi Adrian,
> >
> > On 09/06/2020 19:49, Adrian Ratiu wrote:
> > > [Re-submitting to cc dri-devel, sorry about the noise] Hello
> > > all, v9 cleanly applies on top of latest next-20200609 tree.
> > > v9 does not depend on other patches as the last binding doc has
> > > been merged. All feedback up to this point has been
> > > addressed. Specific details in individual patch changelogs.
> > > The biggest changes are the deprecation of the Synopsys DW
> > > bridge bind() API in favor of of_drm_find_bridge() and .attach
> > > callbacks, the addition of a TODO entry which outlines future
> > > planned bridge driver refactorings and a reordering of some
> > > i.MX 6 patches to appease checkpatch. The idea behind the
> > > TODO is to get this regmap and i.MX 6 driver merged and then do
> > > the rest of refactorings in-tree because it's easier and the
> > > refactorings themselves are out-of-scope of this series which
> > > is adding i.MX 6 support and is quite big already, so please,
> > > if there are more refactoring ideas, let's add them to the TODO
> > > doc. :) I intend to tackle those after this series is merged to
> > > avoid two complex inter-dependent simultaneous series.
> >
> > This has been around here for a long time and you seem to have
> > addressed all the reviews.
> >
> > > As always more testing is welcome especially on Rockchip and
> > > STM SoCs.
> >
> > It has been tested on STM, but I'd like a feedback on RK
> > platform before applying the bridge parts.
> >
> > Can the imx & stm patches be applied separately ?
> >
>
> Yes the IMX and STM patches can be applied separately, they just
> both depend on the common regmap patches.
>
It's been a month so I think it's a good idea to go forward
applying IMX and STM patches (probably with the usual
rebase dance).
As for Rockchip...
> The binding API removal change which directly touches RK can also
> be applied separately, but unfortunately I do not have access to a
> RK board with a DSI display to test it (or the bridge regmap logic
> on RK btw...), I just "eye-balled" the RK code based on the public
> docs and it LGTM.
>
... I'll be getting some DSI hardware to help with the pending
Rockchip issues, so we can tackle Rockchip as well. I'm quite sure
we'll loop Heiko as well if needed :-)
Cheers,
Ezequiel
> > Neil
> >
> > > Big thank you to everyone who has contributed to this up to now,
> > > Adrian
> > >
> > > Adrian Ratiu (11):
> > > drm: bridge: dw_mipi_dsi: add initial regmap infrastructure
> > > drm: bridge: dw_mipi_dsi: abstract register access using reg_fields
> > > drm: bridge: dw_mipi_dsi: add dsi v1.01 support
> > > drm: bridge: dw_mipi_dsi: remove bind/unbind API
> > > dt-bindings: display: add i.MX6 MIPI DSI host controller doc
> > > ARM: dts: imx6qdl: add missing mipi dsi properties
> > > drm: imx: Add i.MX 6 MIPI DSI host platform driver
> > > drm: stm: dw-mipi-dsi: let the bridge handle the HW version check
> > > drm: bridge: dw-mipi-dsi: split low power cfg register into fields
> > > drm: bridge: dw-mipi-dsi: fix bad register field offsets
> > > Documentation: gpu: todo: Add dw-mipi-dsi consolidation plan
> > >
> > > .../display/imx/fsl,mipi-dsi-imx6.yaml | 112 +++
> > > Documentation/gpu/todo.rst | 25 +
> > > arch/arm/boot/dts/imx6qdl.dtsi | 8 +
> > > drivers/gpu/drm/bridge/synopsys/Kconfig | 1 +
> > > drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 713 ++++++++++++------
> > > drivers/gpu/drm/imx/Kconfig | 8 +
> > > drivers/gpu/drm/imx/Makefile | 1 +
> > > drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 399 ++++++++++
> > > .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 7 +-
> > > drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 16 +-
> > > 10 files changed, 1059 insertions(+), 231 deletions(-)
> > > create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
> > > create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
> > >
Hi,
On 15/08/2020 15:05, Ezequiel Garcia wrote:
> Hi Neil,
>
> On Wed, 2020-07-01 at 09:35 +0300, Adrian Ratiu wrote:
>> Hi Neil,
>>
>> On Mon, 29 Jun 2020, Neil Armstrong <[email protected]>
>> wrote:
>>> Hi Adrian,
>>>
>>> On 09/06/2020 19:49, Adrian Ratiu wrote:
[...]
>>
>
> It's been a month so I think it's a good idea to go forward
> applying IMX and STM patches (probably with the usual
> rebase dance).
>
> As for Rockchip...
>
>> The binding API removal change which directly touches RK can also
>> be applied separately, but unfortunately I do not have access to a
>> RK board with a DSI display to test it (or the bridge regmap logic
>> on RK btw...), I just "eye-balled" the RK code based on the public
>> docs and it LGTM.
>>
>
> ... I'll be getting some DSI hardware to help with the pending
> Rockchip issues, so we can tackle Rockchip as well. I'm quite sure
> we'll loop Heiko as well if needed :-)
Sure, Adrian, can you rebase on drm-misc-next so I can apply the IMX and STM patches ?
>
> Cheers,
> Ezequiel
>
>>> Neil
>>>
>>>> Big thank you to everyone who has contributed to this up to now,
>>>> Adrian
>>>>
>>>> Adrian Ratiu (11):
>>>> drm: bridge: dw_mipi_dsi: add initial regmap infrastructure
>>>> drm: bridge: dw_mipi_dsi: abstract register access using reg_fields
>>>> drm: bridge: dw_mipi_dsi: add dsi v1.01 support
>>>> drm: bridge: dw_mipi_dsi: remove bind/unbind API
>>>> dt-bindings: display: add i.MX6 MIPI DSI host controller doc
>>>> ARM: dts: imx6qdl: add missing mipi dsi properties
>>>> drm: imx: Add i.MX 6 MIPI DSI host platform driver
>>>> drm: stm: dw-mipi-dsi: let the bridge handle the HW version check
>>>> drm: bridge: dw-mipi-dsi: split low power cfg register into fields
>>>> drm: bridge: dw-mipi-dsi: fix bad register field offsets
>>>> Documentation: gpu: todo: Add dw-mipi-dsi consolidation plan
>>>>
>>>> .../display/imx/fsl,mipi-dsi-imx6.yaml | 112 +++
>>>> Documentation/gpu/todo.rst | 25 +
>>>> arch/arm/boot/dts/imx6qdl.dtsi | 8 +
>>>> drivers/gpu/drm/bridge/synopsys/Kconfig | 1 +
>>>> drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 713 ++++++++++++------
>>>> drivers/gpu/drm/imx/Kconfig | 8 +
>>>> drivers/gpu/drm/imx/Makefile | 1 +
>>>> drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 399 ++++++++++
>>>> .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 7 +-
>>>> drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 16 +-
>>>> 10 files changed, 1059 insertions(+), 231 deletions(-)
>>>> create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
>>>> create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
>>>>
>
Hi Adrian,
Gentle ping.
can you rebase on drm-misc-next so I can apply the IMX and STM patches ?
On 24/08/2020 11:47, Neil Armstrong wrote:
> Hi,
>
>
> On 15/08/2020 15:05, Ezequiel Garcia wrote:
>> Hi Neil,
>>
>> On Wed, 2020-07-01 at 09:35 +0300, Adrian Ratiu wrote:
>>> Hi Neil,
>>>
>>> On Mon, 29 Jun 2020, Neil Armstrong <[email protected]>
>>> wrote:
>>>> Hi Adrian,
>>>>
>>>> On 09/06/2020 19:49, Adrian Ratiu wrote:
> [...]
>>>
>>
>> It's been a month so I think it's a good idea to go forward
>> applying IMX and STM patches (probably with the usual
>> rebase dance).
>>
>> As for Rockchip...
>>
>>> The binding API removal change which directly touches RK can also
>>> be applied separately, but unfortunately I do not have access to a
>>> RK board with a DSI display to test it (or the bridge regmap logic
>>> on RK btw...), I just "eye-balled" the RK code based on the public
>>> docs and it LGTM.
>>>
>>
>> ... I'll be getting some DSI hardware to help with the pending
>> Rockchip issues, so we can tackle Rockchip as well. I'm quite sure
>> we'll loop Heiko as well if needed :-)
>
> Sure, Adrian, can you rebase on drm-misc-next so I can apply the IMX and STM patches ?
>
>>
>> Cheers,
>> Ezequiel
>>
>>>> Neil
>>>>
>>>>> Big thank you to everyone who has contributed to this up to now,
>>>>> Adrian
>>>>>
>>>>> Adrian Ratiu (11):
>>>>> drm: bridge: dw_mipi_dsi: add initial regmap infrastructure
>>>>> drm: bridge: dw_mipi_dsi: abstract register access using reg_fields
>>>>> drm: bridge: dw_mipi_dsi: add dsi v1.01 support
>>>>> drm: bridge: dw_mipi_dsi: remove bind/unbind API
>>>>> dt-bindings: display: add i.MX6 MIPI DSI host controller doc
>>>>> ARM: dts: imx6qdl: add missing mipi dsi properties
>>>>> drm: imx: Add i.MX 6 MIPI DSI host platform driver
>>>>> drm: stm: dw-mipi-dsi: let the bridge handle the HW version check
>>>>> drm: bridge: dw-mipi-dsi: split low power cfg register into fields
>>>>> drm: bridge: dw-mipi-dsi: fix bad register field offsets
>>>>> Documentation: gpu: todo: Add dw-mipi-dsi consolidation plan
>>>>>
>>>>> .../display/imx/fsl,mipi-dsi-imx6.yaml | 112 +++
>>>>> Documentation/gpu/todo.rst | 25 +
>>>>> arch/arm/boot/dts/imx6qdl.dtsi | 8 +
>>>>> drivers/gpu/drm/bridge/synopsys/Kconfig | 1 +
>>>>> drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 713 ++++++++++++------
>>>>> drivers/gpu/drm/imx/Kconfig | 8 +
>>>>> drivers/gpu/drm/imx/Makefile | 1 +
>>>>> drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 399 ++++++++++
>>>>> .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 7 +-
>>>>> drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 16 +-
>>>>> 10 files changed, 1059 insertions(+), 231 deletions(-)
>>>>> create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
>>>>> create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
>>>>>
>>
>
Hi Neil,
On Tue, 15 Sep 2020, Neil Armstrong <[email protected]>
wrote:
> Hi Adrian,
>
> Gentle ping.
>
> can you rebase on drm-misc-next so I can apply the IMX and STM
> patches ?
Sorry for the late reply, somehow missed this e-mail chain.
I have a rebase of the series but further investigation revealed
we might regress Rockchip with a partial integration, so I'm
getting a panel for RK to test to be sure and will re-submit.
>
> On 24/08/2020 11:47, Neil Armstrong wrote:
>> Hi,
>>
>>
>> On 15/08/2020 15:05, Ezequiel Garcia wrote:
>>> Hi Neil,
>>>
>>> On Wed, 2020-07-01 at 09:35 +0300, Adrian Ratiu wrote:
>>>> Hi Neil,
>>>>
>>>> On Mon, 29 Jun 2020, Neil Armstrong <[email protected]>
>>>> wrote:
>>>>> Hi Adrian,
>>>>>
>>>>> On 09/06/2020 19:49, Adrian Ratiu wrote:
>> [...]
>>>>
>>>
>>> It's been a month so I think it's a good idea to go forward
>>> applying IMX and STM patches (probably with the usual
>>> rebase dance).
>>>
>>> As for Rockchip...
>>>
>>>> The binding API removal change which directly touches RK can also
>>>> be applied separately, but unfortunately I do not have access to a
>>>> RK board with a DSI display to test it (or the bridge regmap logic
>>>> on RK btw...), I just "eye-balled" the RK code based on the public
>>>> docs and it LGTM.
>>>>
>>>
>>> ... I'll be getting some DSI hardware to help with the pending
>>> Rockchip issues, so we can tackle Rockchip as well. I'm quite sure
>>> we'll loop Heiko as well if needed :-)
>>
>> Sure, Adrian, can you rebase on drm-misc-next so I can apply the IMX and STM patches ?
>>
>>>
>>> Cheers,
>>> Ezequiel
>>>
>>>>> Neil
>>>>>
>>>>>> Big thank you to everyone who has contributed to this up to now,
>>>>>> Adrian
>>>>>>
>>>>>> Adrian Ratiu (11):
>>>>>> drm: bridge: dw_mipi_dsi: add initial regmap infrastructure
>>>>>> drm: bridge: dw_mipi_dsi: abstract register access using reg_fields
>>>>>> drm: bridge: dw_mipi_dsi: add dsi v1.01 support
>>>>>> drm: bridge: dw_mipi_dsi: remove bind/unbind API
>>>>>> dt-bindings: display: add i.MX6 MIPI DSI host controller doc
>>>>>> ARM: dts: imx6qdl: add missing mipi dsi properties
>>>>>> drm: imx: Add i.MX 6 MIPI DSI host platform driver
>>>>>> drm: stm: dw-mipi-dsi: let the bridge handle the HW version check
>>>>>> drm: bridge: dw-mipi-dsi: split low power cfg register into fields
>>>>>> drm: bridge: dw-mipi-dsi: fix bad register field offsets
>>>>>> Documentation: gpu: todo: Add dw-mipi-dsi consolidation plan
>>>>>>
>>>>>> .../display/imx/fsl,mipi-dsi-imx6.yaml | 112 +++
>>>>>> Documentation/gpu/todo.rst | 25 +
>>>>>> arch/arm/boot/dts/imx6qdl.dtsi | 8 +
>>>>>> drivers/gpu/drm/bridge/synopsys/Kconfig | 1 +
>>>>>> drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 713 ++++++++++++------
>>>>>> drivers/gpu/drm/imx/Kconfig | 8 +
>>>>>> drivers/gpu/drm/imx/Makefile | 1 +
>>>>>> drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c | 399 ++++++++++
>>>>>> .../gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 7 +-
>>>>>> drivers/gpu/drm/stm/dw_mipi_dsi-stm.c | 16 +-
>>>>>> 10 files changed, 1059 insertions(+), 231 deletions(-)
>>>>>> create mode 100644 Documentation/devicetree/bindings/display/imx/fsl,mipi-dsi-imx6.yaml
>>>>>> create mode 100644 drivers/gpu/drm/imx/dw_mipi_dsi-imx6.c
>>>>>>
>>>
>>