The Cortex-A55/A75/A76 use some implementation defined perf events.
Add the support.
Jisheng Zhang (3):
arm64: perf: add support for Cortex-A55
arm64: perf: add support for Cortex-A75
arm64: perf: add support for Cortex-A76
arch/arm64/kernel/perf_event.c | 49 +++++++++++++++++++++++++++++++---
1 file changed, 45 insertions(+), 4 deletions(-)
--
2.27.0
The Cortex-A55 uses some implementation defined perf events. This
patch sets up the necessary mapping for Cortex-A55.
Mappings are based on Cortex-A55 TRM r2p0, section C2.4 PMU Events
(pages C2-567 to C2-582).
Signed-off-by: Jisheng Zhang <[email protected]>
---
arch/arm64/kernel/perf_event.c | 25 +++++++++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 4d7879484cec..743affbe0cca 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -21,7 +21,7 @@
#include <linux/platform_device.h>
#include <linux/smp.h>
-/* ARMv8 Cortex-A53 specific event types. */
+/* ARMv8 Cortex-A53/A55 specific event types. */
#define ARMV8_A53_PERFCTR_PREF_LINEFILL 0xC2
/* ARMv8 Cavium ThunderX specific event types. */
@@ -81,6 +81,22 @@ static const unsigned armv8_a53_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
};
+static const unsigned armv8_a55_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+ [PERF_COUNT_HW_CACHE_OP_MAX]
+ [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+ PERF_CACHE_MAP_ALL_UNSUPPORTED,
+
+ [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
+ [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
+ [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
+ [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
+ [C(L1D)][C(OP_PREFETCH)][C(RESULT_MISS)] = ARMV8_A53_PERFCTR_PREF_LINEFILL,
+
+
+ [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
+ [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
+};
+
static const unsigned armv8_a57_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[PERF_COUNT_HW_CACHE_OP_MAX]
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
@@ -909,6 +925,11 @@ static int armv8_a53_map_event(struct perf_event *event)
return __armv8_pmuv3_map_event(event, NULL, &armv8_a53_perf_cache_map);
}
+static int armv8_a55_map_event(struct perf_event *event)
+{
+ return __armv8_pmuv3_map_event(event, NULL, &armv8_a55_perf_cache_map);
+}
+
static int armv8_a57_map_event(struct perf_event *event)
{
return __armv8_pmuv3_map_event(event, NULL, &armv8_a57_perf_cache_map);
@@ -1050,7 +1071,7 @@ static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
static int armv8_a55_pmu_init(struct arm_pmu *cpu_pmu)
{
return armv8_pmu_init(cpu_pmu, "armv8_cortex_a55",
- armv8_pmuv3_map_event, NULL, NULL);
+ armv8_a55_map_event, NULL, NULL);
}
static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
--
2.27.0
The Cortex-A75 uses some implementation defined perf events. This
patch sets up the necessary mapping for Cortex-A75.
Mappings are based on Cortex-A75 TRM r3p1, section C2.3 PMU Events
(pages C2-578 to C2-586).
Signed-off-by: Jisheng Zhang <[email protected]>
---
arch/arm64/kernel/perf_event.c | 22 +++++++++++++++++++++-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 743affbe0cca..55e1d75af708 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -123,6 +123,21 @@ static const unsigned armv8_a73_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
};
+static const unsigned armv8_a75_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
+ [PERF_COUNT_HW_CACHE_OP_MAX]
+ [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
+ PERF_CACHE_MAP_ALL_UNSUPPORTED,
+
+ [C(L1D)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_RD,
+ [C(L1D)][C(OP_READ)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_RD,
+ [C(L1D)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_WR,
+ [C(L1D)][C(OP_WRITE)][C(RESULT_MISS)] = ARMV8_IMPDEF_PERFCTR_L1D_CACHE_REFILL_WR,
+
+
+ [C(NODE)][C(OP_READ)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_RD,
+ [C(NODE)][C(OP_WRITE)][C(RESULT_ACCESS)] = ARMV8_IMPDEF_PERFCTR_BUS_ACCESS_WR,
+};
+
static const unsigned armv8_thunder_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
[PERF_COUNT_HW_CACHE_OP_MAX]
[PERF_COUNT_HW_CACHE_RESULT_MAX] = {
@@ -940,6 +955,11 @@ static int armv8_a73_map_event(struct perf_event *event)
return __armv8_pmuv3_map_event(event, NULL, &armv8_a73_perf_cache_map);
}
+static int armv8_a75_map_event(struct perf_event *event)
+{
+ return __armv8_pmuv3_map_event(event, NULL, &armv8_a75_perf_cache_map);
+}
+
static int armv8_thunder_map_event(struct perf_event *event)
{
return __armv8_pmuv3_map_event(event, NULL,
@@ -1101,7 +1121,7 @@ static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
static int armv8_a75_pmu_init(struct arm_pmu *cpu_pmu)
{
return armv8_pmu_init(cpu_pmu, "armv8_cortex_a75",
- armv8_pmuv3_map_event, NULL, NULL);
+ armv8_a75_map_event, NULL, NULL);
}
static int armv8_a76_pmu_init(struct arm_pmu *cpu_pmu)
--
2.27.0
The Cortex-A76 uses some implementation defined perf events. Per
Cortex-A76 TRM r4p0, section C2.3 PMU Events (pages C2-386 to C2-394),
we can reuse Cortex-A57's perf events mapping currently.
Signed-off-by: Jisheng Zhang <[email protected]>
---
arch/arm64/kernel/perf_event.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 55e1d75af708..4fb13fbdc2df 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -1127,7 +1127,7 @@ static int armv8_a75_pmu_init(struct arm_pmu *cpu_pmu)
static int armv8_a76_pmu_init(struct arm_pmu *cpu_pmu)
{
return armv8_pmu_init(cpu_pmu, "armv8_cortex_a76",
- armv8_pmuv3_map_event, NULL, NULL);
+ armv8_a57_map_event, NULL, NULL);
}
static int armv8_a77_pmu_init(struct arm_pmu *cpu_pmu)
--
2.27.0
On Fri, Jun 19, 2020 at 06:44:37PM +0800, Jisheng Zhang wrote:
> The Cortex-A55/A75/A76 use some implementation defined perf events.
> Add the support.
>
> Jisheng Zhang (3):
> arm64: perf: add support for Cortex-A55
> arm64: perf: add support for Cortex-A75
> arm64: perf: add support for Cortex-A76
>
> arch/arm64/kernel/perf_event.c | 49 +++++++++++++++++++++++++++++++---
> 1 file changed, 45 insertions(+), 4 deletions(-)
Do we really need this? I'd prefer for this stuff to live in userspace
now that the perf tool has supported JSON event descriptions for a while,
and the in-kernel driver advertises the architected events advertised
by PMCEID*.
Will
Hi Will,
On Fri, 3 Jul 2020 13:33:47 +0100 Will Deacon wrote:
>
>
> On Fri, Jun 19, 2020 at 06:44:37PM +0800, Jisheng Zhang wrote:
> > The Cortex-A55/A75/A76 use some implementation defined perf events.
> > Add the support.
> >
> > Jisheng Zhang (3):
> > arm64: perf: add support for Cortex-A55
> > arm64: perf: add support for Cortex-A75
> > arm64: perf: add support for Cortex-A76
> >
> > arch/arm64/kernel/perf_event.c | 49 +++++++++++++++++++++++++++++++---
> > 1 file changed, 45 insertions(+), 4 deletions(-)
>
> Do we really need this? I'd prefer for this stuff to live in userspace
IMHO, this stuff is to add a relationship between linux standard
HW events and ARM PMU events, take CA55 for example:
w/o the stuff, perf -e PREFETCH_LINEFILL
w/ the stuff, perf -e L1-dcache-prefetch-misses
But indeed, we also need to add json descriptions in perf tool, I'll submit
patches.
Thanks
> now that the perf tool has supported JSON event descriptions for a while,
> and the in-kernel driver advertises the architected events advertised
> by PMCEID*.
>
> Will