Hi,
This is a v2 of my second batch of i.MX8 DTS and bindings cleanup. It's
rebased on top of first batch [1] although it is independent.
1. For arm64/dts patches: to avoid any conflicts, better to apply
on top of [1].
2. dt-bindings patches: independend, can be applied by Rob or subsystem
maintainers.
Changes since v1:
=================
1. Address few comments - see individual patches.
[1] https://lore.kernel.org/lkml/[email protected]/
Best regards,
Krzysztof
Krzysztof Kozlowski (19):
dt-bindings: mfd: rohm,bd71847-pmic: Correct clock properties
requirements
dt-bindings: mtd: gpmi-nand: Fix matching of clocks on different SoCs
arm64: dts: imx8mm-beacon-kit: Add missing build through Makefile
arm64: dts: imx8mm-beacon-som: Align regulator names with schema
arm64: dts: imx8mm-beacon-som: Fix atmel,24c64 EEPROM compatible
arm64: dts: imx8mm-beacon: Align pin configuration group names with
schema
arm64: dts: imx8mm-evk: Align regulator names with schema
arm64: dts: imx8mm-evk: Add 32.768 kHz clock to PMIC
arm64: dts: imx8mm-evk: Align pin configuration group names with
schema
arm64: dts: imx8mm-ddr4-evk: Align pin configuration group names with
schema
arm64: dts: imx8mn-ddr4-evk: Align regulator names with schema
arm64: dts: imx8mn-evk: Align pin configuration group names with
schema
arm64: dts: imx8mq-evk: Align pin configuration group names with
schema
arm64: dts: imx8mq-librem5-devkit: Align pin configuration group names
with schema
arm64: dts: imx8mq-phanbell: Align pin configuration group names with
schema
arm64: dts: imx8mq-pico-pi: Align pin configuration group names with
schema
arm64: dts: imx8mq-sr-som: Align pin configuration group names with
schema
arm64: dts: imx8mq-hummingboard-pulse: Align pin configuration group
names with schema
arm64: dts: imx8qxp-colibri: Align pin configuration group names with
schema
.../bindings/mfd/rohm,bd71847-pmic.yaml | 9 ++-
.../devicetree/bindings/mtd/gpmi-nand.yaml | 76 +++++++++++++++----
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../freescale/imx8mm-beacon-baseboard.dtsi | 8 +-
.../boot/dts/freescale/imx8mm-beacon-som.dtsi | 36 ++++-----
arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 40 +++++-----
.../boot/dts/freescale/imx8mn-ddr4-evk.dts | 24 +++---
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 14 ++--
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 2 +-
.../freescale/imx8mq-hummingboard-pulse.dts | 8 +-
.../dts/freescale/imx8mq-librem5-devkit.dts | 12 +--
.../boot/dts/freescale/imx8mq-phanbell.dts | 12 +--
.../boot/dts/freescale/imx8mq-pico-pi.dts | 12 +--
.../boot/dts/freescale/imx8mq-sr-som.dtsi | 4 +-
.../boot/dts/freescale/imx8qxp-colibri.dtsi | 8 +-
15 files changed, 161 insertions(+), 105 deletions(-)
--
2.17.1
The input clock and number of clock provider cells are not required for
the PMIC to operate. They are needed only for the optional bd718x7
clock driver.
Add also clock-output-names as driver takes use of it.
This fixes dtbs_check warnings like:
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dt.yaml: pmic@4b: 'clocks' is a required property
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dt.yaml: pmic@4b: '#clock-cells' is a required property
Signed-off-by: Krzysztof Kozlowski <[email protected]>
Acked-by: Matti Vaittinen <[email protected]>
---
.../devicetree/bindings/mfd/rohm,bd71847-pmic.yaml | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/mfd/rohm,bd71847-pmic.yaml b/Documentation/devicetree/bindings/mfd/rohm,bd71847-pmic.yaml
index 77bcca2d414f..5d531051a153 100644
--- a/Documentation/devicetree/bindings/mfd/rohm,bd71847-pmic.yaml
+++ b/Documentation/devicetree/bindings/mfd/rohm,bd71847-pmic.yaml
@@ -38,6 +38,9 @@ properties:
"#clock-cells":
const: 0
+ clock-output-names:
+ maxItems: 1
+
# The BD71847 abd BD71850 support two different HW states as reset target
# states. States are called as SNVS and READY. At READY state all the PMIC
# power outputs go down and OTP is reload. At the SNVS state all other logic
@@ -116,12 +119,14 @@ required:
- compatible
- reg
- interrupts
- - clocks
- - "#clock-cells"
- regulators
additionalProperties: false
+dependencies:
+ '#clock-cells': [clocks]
+ clocks: ['#clock-cells']
+
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
--
2.17.1
Add missing imx8mm-beacon-kit.dts object in Makefile so it will be build
when building dtbs.
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index a39f0a1723e0..903c0eb61290 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -28,6 +28,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
--
2.17.1
Device tree schema expects regulator names to be lowercase. Changing to
lowercase has multiple effects:
1. LDO6 supply is now properly configured, because regulator driver
looks for supplies by lowercase name,
2. User-visible names via sysfs or debugfs are now lowercase,
2. dtbs_check warnings are fixed:
pmic@4b: regulators:LDO1:regulator-name:0: 'LDO1' does not match '^ldo[1-6]$'
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../boot/dts/freescale/imx8mm-beacon-som.dtsi | 22 +++++++++----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
index 94911b1707ef..f627e82ad929 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
@@ -79,7 +79,7 @@
regulators {
buck1_reg: BUCK1 {
- regulator-name = "BUCK1";
+ regulator-name = "buck1";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
@@ -88,7 +88,7 @@
};
buck2_reg: BUCK2 {
- regulator-name = "BUCK2";
+ regulator-name = "buck2";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
@@ -100,7 +100,7 @@
buck3_reg: BUCK3 {
// BUCK5 in datasheet
- regulator-name = "BUCK3";
+ regulator-name = "buck3";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
@@ -109,7 +109,7 @@
buck4_reg: BUCK4 {
// BUCK6 in datasheet
- regulator-name = "BUCK4";
+ regulator-name = "buck4";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
@@ -118,7 +118,7 @@
buck5_reg: BUCK5 {
// BUCK7 in datasheet
- regulator-name = "BUCK5";
+ regulator-name = "buck5";
regulator-min-microvolt = <1605000>;
regulator-max-microvolt = <1995000>;
regulator-boot-on;
@@ -127,7 +127,7 @@
buck6_reg: BUCK6 {
// BUCK8 in datasheet
- regulator-name = "BUCK6";
+ regulator-name = "buck6";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
@@ -135,7 +135,7 @@
};
ldo1_reg: LDO1 {
- regulator-name = "LDO1";
+ regulator-name = "ldo1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
@@ -143,7 +143,7 @@
};
ldo2_reg: LDO2 {
- regulator-name = "LDO2";
+ regulator-name = "ldo2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
@@ -151,7 +151,7 @@
};
ldo3_reg: LDO3 {
- regulator-name = "LDO3";
+ regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
@@ -159,7 +159,7 @@
};
ldo4_reg: LDO4 {
- regulator-name = "LDO4";
+ regulator-name = "ldo4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
@@ -167,7 +167,7 @@
};
ldo6_reg: LDO6 {
- regulator-name = "LDO6";
+ regulator-name = "ldo6";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
--
2.17.1
Correct the EEPROM node compatible to match device tree schema (invalid
space, unknown ID) to fix dtbs_check warnings:
arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dt.yaml: eeprom@50:
compatible: ['microchip, at24c64d', 'atmel,24c64'] is not valid under any of the given schemas
arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dt.yaml: eeprom@50:
compatible:0: 'microchip, at24c64d' does not match '^[a-zA-Z][a-zA-Z0-9,+\\-._]+$'
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
index f627e82ad929..620a124dfb5f 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
@@ -184,7 +184,7 @@
status = "okay";
eeprom@50 {
- compatible = "microchip, at24c64d", "atmel,24c64";
+ compatible = "microchip,24c64", "atmel,24c64";
pagesize = <32>;
read-only; /* Manufacturing EEPROM programmed at factory */
reg = <0x50>;
--
2.17.1
Device tree schema expects pin configuration groups to end with 'grp'
suffix. This fixes dtbs_check warnings like:
pinctrl@30330000: 'pcal6414-gpio', 'pmicirq', 'usdhc1grp100mhz', 'usdhc1grp200mhz', 'usdhc1grpgpio',
'usdhc2grp100mhz', 'usdhc2grp200mhz', 'usdhc2grpgpio', 'usdhc3grp100mhz', 'usdhc3grp200mhz'
do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../boot/dts/freescale/imx8mm-beacon-baseboard.dtsi | 8 ++++----
arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi | 12 ++++++------
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
index bf0859f1e1fa..16e4910aeb1e 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi
@@ -210,7 +210,7 @@
>;
};
- pinctrl_pcal6414: pcal6414-gpio {
+ pinctrl_pcal6414: pcal6414-gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x19
>;
@@ -240,7 +240,7 @@
>;
};
- pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 0x41
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
@@ -259,7 +259,7 @@
>;
};
- pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
@@ -271,7 +271,7 @@
>;
};
- pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
index 620a124dfb5f..502faf6144b0 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi
@@ -290,7 +290,7 @@
>;
};
- pinctrl_pmic: pmicirq {
+ pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>;
@@ -309,7 +309,7 @@
>;
};
- pinctrl_usdhc1_gpio: usdhc1grpgpio {
+ pinctrl_usdhc1_gpio: usdhc1gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
>;
@@ -326,7 +326,7 @@
>;
};
- pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
@@ -337,7 +337,7 @@
>;
};
- pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
@@ -364,7 +364,7 @@
>;
};
- pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
@@ -380,7 +380,7 @@
>;
};
- pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
--
2.17.1
Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:
... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
index a1e5483dbbbe..3ac8f9d3c372 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
@@ -155,7 +155,7 @@
};
&iomuxc {
- pinctrl_pmic: pmicirq {
+ pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>;
--
2.17.1
Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:
... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
index 48892ed562b4..ed9b5241acc7 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi
@@ -221,13 +221,13 @@
>;
};
- pinctrl_pmic: pmicirq {
+ pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>;
};
- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
@@ -246,7 +246,7 @@
>;
};
- pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MN_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
>;
@@ -264,7 +264,7 @@
>;
};
- pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
@@ -276,7 +276,7 @@
>;
};
- pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
@@ -304,7 +304,7 @@
>;
};
- pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000194
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
@@ -320,7 +320,7 @@
>;
};
- pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK 0x40000196
MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
--
2.17.1
Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:
... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mq-evk.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
index a088831d2e24..7c6808814856 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-evk.dts
@@ -407,7 +407,7 @@
>;
};
- pinctrl_reg_usdhc2: regusdhc2grpgpio {
+ pinctrl_reg_usdhc2: regusdhc2gpiogrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
--
2.17.1
Device tree schema expects regulator names to be lowercase. Changing to
lowercase has multiple effects:
1. LDO6 supply is now properly configured, because regulator driver
looks for supplies by lowercase name,
2. User-visible names via sysfs or debugfs are now lowercase,
2. dtbs_check warnings are fixed:
pmic@4b: regulators:LDO1:regulator-name:0: 'LDO1' does not match '^ldo[1-6]$'
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../boot/dts/freescale/imx8mn-ddr4-evk.dts | 22 +++++++++----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
index 3ac8f9d3c372..8f7155716c84 100644
--- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
@@ -60,7 +60,7 @@
regulators {
buck1_reg: BUCK1 {
- regulator-name = "BUCK1";
+ regulator-name = "buck1";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
@@ -69,7 +69,7 @@
};
buck2_reg: BUCK2 {
- regulator-name = "BUCK2";
+ regulator-name = "buck2";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
@@ -79,14 +79,14 @@
buck3_reg: BUCK3 {
// BUCK5 in datasheet
- regulator-name = "BUCK3";
+ regulator-name = "buck3";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
};
buck4_reg: BUCK4 {
// BUCK6 in datasheet
- regulator-name = "BUCK4";
+ regulator-name = "buck4";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
@@ -95,7 +95,7 @@
buck5_reg: BUCK5 {
// BUCK7 in datasheet
- regulator-name = "BUCK5";
+ regulator-name = "buck5";
regulator-min-microvolt = <1605000>;
regulator-max-microvolt = <1995000>;
regulator-boot-on;
@@ -104,7 +104,7 @@
buck6_reg: BUCK6 {
// BUCK8 in datasheet
- regulator-name = "BUCK6";
+ regulator-name = "buck6";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
@@ -112,7 +112,7 @@
};
ldo1_reg: LDO1 {
- regulator-name = "LDO1";
+ regulator-name = "ldo1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
@@ -120,7 +120,7 @@
};
ldo2_reg: LDO2 {
- regulator-name = "LDO2";
+ regulator-name = "ldo2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
@@ -128,7 +128,7 @@
};
ldo3_reg: LDO3 {
- regulator-name = "LDO3";
+ regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
@@ -136,7 +136,7 @@
};
ldo4_reg: LDO4 {
- regulator-name = "LDO4";
+ regulator-name = "ldo4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
@@ -144,7 +144,7 @@
};
ldo6_reg: LDO6 {
- regulator-name = "LDO6";
+ regulator-name = "ldo6";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
--
2.17.1
Driver requires different amount of clocks for different SoCs. Describe
these requirements properly to fix dtbs_check warnings like:
arch/arm64/boot/dts/freescale/imx8mm-beacon-kit.dt.yaml: nand-controller@33002000: clock-names:1: 'gpmi_apb' was expected
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
Changes since v1:
1. Do not require order of clocks (use pattern).
---
.../devicetree/bindings/mtd/gpmi-nand.yaml | 76 +++++++++++++++----
1 file changed, 61 insertions(+), 15 deletions(-)
diff --git a/Documentation/devicetree/bindings/mtd/gpmi-nand.yaml b/Documentation/devicetree/bindings/mtd/gpmi-nand.yaml
index 28ff8c581837..e08e0a50929e 100644
--- a/Documentation/devicetree/bindings/mtd/gpmi-nand.yaml
+++ b/Documentation/devicetree/bindings/mtd/gpmi-nand.yaml
@@ -9,9 +9,6 @@ title: Freescale General-Purpose Media Interface (GPMI) binding
maintainers:
- Han Xu <[email protected]>
-allOf:
- - $ref: "nand-controller.yaml"
-
description: |
The GPMI nand controller provides an interface to control the NAND
flash chips. The device tree may optionally contain sub-nodes
@@ -58,22 +55,10 @@ properties:
clocks:
minItems: 1
maxItems: 5
- items:
- - description: SoC gpmi io clock
- - description: SoC gpmi apb clock
- - description: SoC gpmi bch clock
- - description: SoC gpmi bch apb clock
- - description: SoC per1 bch clock
clock-names:
minItems: 1
maxItems: 5
- items:
- - const: gpmi_io
- - const: gpmi_apb
- - const: gpmi_bch
- - const: gpmi_bch_apb
- - const: per1_bch
fsl,use-minimum-ecc:
type: boolean
@@ -107,6 +92,67 @@ required:
unevaluatedProperties: false
+allOf:
+ - $ref: "nand-controller.yaml"
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx23-gpmi-nand
+ - fsl,imx28-gpmi-nand
+ then:
+ properties:
+ clocks:
+ items:
+ - description: SoC gpmi io clock
+ clock-names:
+ items:
+ - const: gpmi_io
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx6q-gpmi-nand
+ - fsl,imx6sx-gpmi-nand
+ then:
+ properties:
+ clocks:
+ items:
+ - description: SoC gpmi io clock
+ - description: SoC gpmi apb clock
+ - description: SoC gpmi bch clock
+ - description: SoC gpmi bch apb clock
+ - description: SoC per1 bch clock
+ clock-names:
+ items:
+ - pattern: "^(gpmi_(io|apb|bch|bch_apb)|per1_bch)$"
+ - pattern: "^(gpmi_(io|apb|bch|bch_apb)|per1_bch)$"
+ - pattern: "^(gpmi_(io|apb|bch|bch_apb)|per1_bch)$"
+ - pattern: "^(gpmi_(io|apb|bch|bch_apb)|per1_bch)$"
+ - pattern: "^(gpmi_(io|apb|bch|bch_apb)|per1_bch)$"
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx7d-gpmi-nand
+ then:
+ properties:
+ clocks:
+ items:
+ - description: SoC gpmi io clock
+ - description: SoC gpmi bch apb clock
+ clock-names:
+ minItems: 2
+ maxItems: 2
+ items:
+ - pattern: "^gpmi_(io|bch_apb)$"
+ - pattern: "^gpmi_(io|bch_apb)$"
+
examples:
- |
nand-controller@8000c000 {
--
2.17.1
The ROHM BD71847 PMIC has a 32.768 kHz clock. Adding necessary parent
allows to probe the bd718x7 clock driver fixing boot errors:
bd718xx-clk bd71847-clk.1.auto: No parent clk found
bd718xx-clk: probe of bd71847-clk.1.auto failed with error -22
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
index 3cb8b6bcb657..0115f07bbc9d 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
@@ -149,6 +149,10 @@
interrupts = <3 GPIO_ACTIVE_LOW>;
rohm,reset-snvs-powered;
+ #clock-cells = <0>;
+ clocks = <&osc_32k 0>;
+ clock-output-names = "clk-32k-out";
+
regulators {
buck1_reg: BUCK1 {
regulator-name = "buck1";
--
2.17.1
Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:
... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
index 3f541ddf0768..d6d3a3d5abc3 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts
@@ -365,7 +365,7 @@
>;
};
- pinctrl_pmic: pmicirq {
+ pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>;
@@ -395,7 +395,7 @@
>;
};
- pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
@@ -412,7 +412,7 @@
>;
};
- pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
@@ -429,7 +429,7 @@
>;
};
- pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
@@ -448,7 +448,7 @@
>;
};
- pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
@@ -460,7 +460,7 @@
>;
};
- pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
--
2.17.1
Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:
... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts b/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts
index 59da96b7143f..f4d5748a7bd6 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts
@@ -297,7 +297,7 @@
>;
};
- pinctrl_pmic: pmicirq {
+ pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>;
@@ -335,7 +335,7 @@
>;
};
- pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x85
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc5
@@ -351,7 +351,7 @@
>;
};
- pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x87
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc7
@@ -367,7 +367,7 @@
>;
};
- pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
>;
@@ -385,7 +385,7 @@
>;
};
- pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x85
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc5
@@ -397,7 +397,7 @@
>;
};
- pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x87
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc7
--
2.17.1
Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:
... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../boot/dts/freescale/imx8mq-hummingboard-pulse.dts | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts b/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts
index bfd91c1ed6a5..366693f31992 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-hummingboard-pulse.dts
@@ -214,13 +214,13 @@
>;
};
- pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41
>;
};
- pinctrl_usdhc2_vmmc: usdhc2vmmcgpio {
+ pinctrl_usdhc2_vmmc: usdhc2vmmcgpiogrp {
fsl,pins = <
MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x41
>;
@@ -238,7 +238,7 @@
>;
};
- pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
@@ -250,7 +250,7 @@
>;
};
- pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf
--
2.17.1
Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:
... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
index 0115f07bbc9d..207dc8de3145 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
@@ -423,13 +423,13 @@
>;
};
- pinctrl_pmic: pmicirq {
+ pinctrl_pmic: pmicirqgrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
>;
};
- pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
+ pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
@@ -457,7 +457,7 @@
>;
};
- pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x1c4
>;
@@ -475,7 +475,7 @@
>;
};
- pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
@@ -487,7 +487,7 @@
>;
};
- pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
@@ -515,7 +515,7 @@
>;
};
- pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
+ pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
@@ -531,7 +531,7 @@
>;
};
- pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
+ pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = <
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
--
2.17.1
Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:
... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
.../boot/dts/freescale/imx8mq-librem5-devkit.dts | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
index 6900ac274f5b..377591a0e6e9 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5-devkit.dts
@@ -734,7 +734,7 @@
>;
};
- pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
@@ -751,7 +751,7 @@
>;
};
- pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
@@ -768,13 +768,13 @@
>;
};
- pinctrl_usdhc2_pwr: usdhc2grppwr {
+ pinctrl_usdhc2_pwr: usdhc2pwrgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
>;
};
- pinctrl_usdhc2_gpio: usdhc2grpgpio {
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20 0x80 /* WIFI_WAKE */
>;
@@ -791,7 +791,7 @@
>;
};
- pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd
@@ -802,7 +802,7 @@
>;
};
- pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f
MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcf
--
2.17.1
Device tree schema expects regulator names to be lowercase. Changing to
lowercase has multiple effects:
1. LDO6 supply is now properly configured, because regulator driver
looks for supplies by lowercase name,
2. User-visible names via sysfs or debugfs are now lowercase,
2. dtbs_check warnings are fixed:
pmic@4b: regulators:LDO1:regulator-name:0: 'LDO1' does not match '^ldo[1-6]$'
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 22 ++++++++++----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
index c1f7d44651df..3cb8b6bcb657 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
@@ -151,7 +151,7 @@
regulators {
buck1_reg: BUCK1 {
- regulator-name = "BUCK1";
+ regulator-name = "buck1";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
@@ -160,7 +160,7 @@
};
buck2_reg: BUCK2 {
- regulator-name = "BUCK2";
+ regulator-name = "buck2";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1300000>;
regulator-boot-on;
@@ -172,7 +172,7 @@
buck3_reg: BUCK3 {
// BUCK5 in datasheet
- regulator-name = "BUCK3";
+ regulator-name = "buck3";
regulator-min-microvolt = <700000>;
regulator-max-microvolt = <1350000>;
regulator-boot-on;
@@ -181,7 +181,7 @@
buck4_reg: BUCK4 {
// BUCK6 in datasheet
- regulator-name = "BUCK4";
+ regulator-name = "buck4";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
@@ -190,7 +190,7 @@
buck5_reg: BUCK5 {
// BUCK7 in datasheet
- regulator-name = "BUCK5";
+ regulator-name = "buck5";
regulator-min-microvolt = <1605000>;
regulator-max-microvolt = <1995000>;
regulator-boot-on;
@@ -199,7 +199,7 @@
buck6_reg: BUCK6 {
// BUCK8 in datasheet
- regulator-name = "BUCK6";
+ regulator-name = "buck6";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1400000>;
regulator-boot-on;
@@ -207,7 +207,7 @@
};
ldo1_reg: LDO1 {
- regulator-name = "LDO1";
+ regulator-name = "ldo1";
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
@@ -215,7 +215,7 @@
};
ldo2_reg: LDO2 {
- regulator-name = "LDO2";
+ regulator-name = "ldo2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <900000>;
regulator-boot-on;
@@ -223,7 +223,7 @@
};
ldo3_reg: LDO3 {
- regulator-name = "LDO3";
+ regulator-name = "ldo3";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
@@ -231,7 +231,7 @@
};
ldo4_reg: LDO4 {
- regulator-name = "LDO4";
+ regulator-name = "ldo4";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
@@ -239,7 +239,7 @@
};
ldo6_reg: LDO6 {
- regulator-name = "LDO6";
+ regulator-name = "ldo6";
regulator-min-microvolt = <900000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
--
2.17.1
Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:
... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi
index 404c46671b96..0187890a90c5 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mq-sr-som.dtsi
@@ -275,7 +275,7 @@
>;
};
- pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd
@@ -292,7 +292,7 @@
>;
};
- pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f
MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf
--
2.17.1
Device tree schema expects pin configuration groups to end with 'grp'
suffix, otherwise dtbs_check complain with a warning like:
... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi
index 75f17a29f81e..f38acff0d25c 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi
@@ -494,7 +494,7 @@
>;
};
- pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
fsl,pins = <
IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21
@@ -511,7 +511,7 @@
>;
};
- pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
fsl,pins = <
IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21
@@ -554,7 +554,7 @@
>;
};
- pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
fsl,pins = <
IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */
IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */
@@ -566,7 +566,7 @@
>;
};
- pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
fsl,pins = <
IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */
IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */
--
2.17.1
On Fri, 2020-08-28 at 18:47 +0200, Krzysztof Kozlowski wrote:
> Device tree schema expects regulator names to be lowercase. Changing
> to
> lowercase has multiple effects:
> 1. LDO6 supply is now properly configured, because regulator driver
> looks for supplies by lowercase name,
> 2. User-visible names via sysfs or debugfs are now lowercase,
> 2. dtbs_check warnings are fixed:
>
> pmic@4b: regulators:LDO1:regulator-name:0: 'LDO1' does not match
> '^ldo[1-6]$'
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
FWIW:
Acked-By: Matti Vaittinen <[email protected]>
> ---
> .../boot/dts/freescale/imx8mn-ddr4-evk.dts | 22 +++++++++------
> ----
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
> b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
> index 3ac8f9d3c372..8f7155716c84 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts
> @@ -60,7 +60,7 @@
>
> regulators {
> buck1_reg: BUCK1 {
> - regulator-name = "BUCK1";
> + regulator-name = "buck1";
> regulator-min-microvolt = <700000>;
> regulator-max-microvolt = <1300000>;
> regulator-boot-on;
> @@ -69,7 +69,7 @@
> };
>
> buck2_reg: BUCK2 {
> - regulator-name = "BUCK2";
> + regulator-name = "buck2";
> regulator-min-microvolt = <700000>;
> regulator-max-microvolt = <1300000>;
> regulator-boot-on;
> @@ -79,14 +79,14 @@
>
> buck3_reg: BUCK3 {
> // BUCK5 in datasheet
> - regulator-name = "BUCK3";
> + regulator-name = "buck3";
> regulator-min-microvolt = <700000>;
> regulator-max-microvolt = <1350000>;
> };
>
> buck4_reg: BUCK4 {
> // BUCK6 in datasheet
> - regulator-name = "BUCK4";
> + regulator-name = "buck4";
> regulator-min-microvolt = <3000000>;
> regulator-max-microvolt = <3300000>;
> regulator-boot-on;
> @@ -95,7 +95,7 @@
>
> buck5_reg: BUCK5 {
> // BUCK7 in datasheet
> - regulator-name = "BUCK5";
> + regulator-name = "buck5";
> regulator-min-microvolt = <1605000>;
> regulator-max-microvolt = <1995000>;
> regulator-boot-on;
> @@ -104,7 +104,7 @@
>
> buck6_reg: BUCK6 {
> // BUCK8 in datasheet
> - regulator-name = "BUCK6";
> + regulator-name = "buck6";
> regulator-min-microvolt = <800000>;
> regulator-max-microvolt = <1400000>;
> regulator-boot-on;
> @@ -112,7 +112,7 @@
> };
>
> ldo1_reg: LDO1 {
> - regulator-name = "LDO1";
> + regulator-name = "ldo1";
> regulator-min-microvolt = <1600000>;
> regulator-max-microvolt = <3300000>;
> regulator-boot-on;
> @@ -120,7 +120,7 @@
> };
>
> ldo2_reg: LDO2 {
> - regulator-name = "LDO2";
> + regulator-name = "ldo2";
> regulator-min-microvolt = <800000>;
> regulator-max-microvolt = <900000>;
> regulator-boot-on;
> @@ -128,7 +128,7 @@
> };
>
> ldo3_reg: LDO3 {
> - regulator-name = "LDO3";
> + regulator-name = "ldo3";
> regulator-min-microvolt = <1800000>;
> regulator-max-microvolt = <3300000>;
> regulator-boot-on;
> @@ -136,7 +136,7 @@
> };
>
> ldo4_reg: LDO4 {
> - regulator-name = "LDO4";
> + regulator-name = "ldo4";
> regulator-min-microvolt = <900000>;
> regulator-max-microvolt = <1800000>;
> regulator-boot-on;
> @@ -144,7 +144,7 @@
> };
>
> ldo6_reg: LDO6 {
> - regulator-name = "LDO6";
> + regulator-name = "ldo6";
> regulator-min-microvolt = <900000>;
> regulator-max-microvolt = <1800000>;
> regulator-boot-on;
On Fri, 2020-08-28 at 18:47 +0200, Krzysztof Kozlowski wrote:
> The ROHM BD71847 PMIC has a 32.768 kHz clock. Adding necessary
> parent
> allows to probe the bd718x7 clock driver fixing boot errors:
>
> bd718xx-clk bd71847-clk.1.auto: No parent clk found
> bd718xx-clk: probe of bd71847-clk.1.auto failed with error -22
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
FWIW:
Acked-By: Matti Vaittinen <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8mm-evk.dts | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> index 3cb8b6bcb657..0115f07bbc9d 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dts
> @@ -149,6 +149,10 @@
> interrupts = <3 GPIO_ACTIVE_LOW>;
> rohm,reset-snvs-powered;
>
> + #clock-cells = <0>;
> + clocks = <&osc_32k 0>;
> + clock-output-names = "clk-32k-out";
> +
> regulators {
> buck1_reg: BUCK1 {
> regulator-name = "buck1";
On Fri, Aug 28, 2020 at 06:47:37PM +0200, Krzysztof Kozlowski wrote:
> Device tree schema expects pin configuration groups to end with 'grp'
> suffix. This fixes dtbs_check warnings like:
>
> pinctrl@30330000: 'pcal6414-gpio', 'pmicirq', 'usdhc1grp100mhz', 'usdhc1grp200mhz', 'usdhc1grpgpio',
> 'usdhc2grp100mhz', 'usdhc2grp200mhz', 'usdhc2grpgpio', 'usdhc3grp100mhz', 'usdhc3grp200mhz'
> do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
Applied, thanks.
On Fri, Aug 28, 2020 at 06:47:39PM +0200, Krzysztof Kozlowski wrote:
> The ROHM BD71847 PMIC has a 32.768 kHz clock. Adding necessary parent
> allows to probe the bd718x7 clock driver fixing boot errors:
>
> bd718xx-clk bd71847-clk.1.auto: No parent clk found
> bd718xx-clk: probe of bd71847-clk.1.auto failed with error -22
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
Applied, thanks.
On Fri, Aug 28, 2020 at 06:47:40PM +0200, Krzysztof Kozlowski wrote:
> Device tree schema expects pin configuration groups to end with 'grp'
> suffix, otherwise dtbs_check complain with a warning like:
>
> ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
>
> Signed-off-by: Krzysztof Kozlowski <[email protected]>
Applied #9 ~ #19, thanks.