Incorrect mask for the "bus_prot_clr" field meant that imgtec
gpu power domain (mfg_async) was not powered up correctly, causing
failure in driver booting. Fixing this and also adding "domain_suuply"
capability to "mfg_async" power domain (for mt8173) as imgtec gpu
needs da9211 regulator to be enabled before enabling this subdomain.
Tested with mt8173 elm chromebook.
Bilal Wasim (2):
soc: mediatek: pm-domains: Use correct mask for bus_prot_clr
soc: mediatek: pm-domains: Add domain_supply cap for mfg_async PD
drivers/soc/mediatek/mt8173-pm-domains.h | 1 +
drivers/soc/mediatek/mtk-pm-domains.h | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
--
2.25.1
When "bus_prot_reg_update" is false, the driver should use
INFRA_TOPAXI_PROTECTEN for both setting and clearing the bus
protection. However, the driver does not use this mask for
clearing bus protection which causes failure when booting
the imgtec gpu.
Corrected and tested with mt8173 chromebook.
Signed-off-by: Bilal Wasim <[email protected]>
---
drivers/soc/mediatek/mtk-pm-domains.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
index 141dc76054e6..7454c0b4f768 100644
--- a/drivers/soc/mediatek/mtk-pm-domains.h
+++ b/drivers/soc/mediatek/mtk-pm-domains.h
@@ -60,7 +60,7 @@
#define BUS_PROT_UPDATE_TOPAXI(_mask) \
BUS_PROT_UPDATE(_mask, \
INFRA_TOPAXI_PROTECTEN, \
- INFRA_TOPAXI_PROTECTEN_CLR, \
+ INFRA_TOPAXI_PROTECTEN, \
INFRA_TOPAXI_PROTECTSTA1)
struct scpsys_bus_prot_data {
--
2.25.1
The mfg_async power domain in mt8173 is used to power up imgtec
gpu. This domain requires the da9211 regulator to be enabled before
the power domain can be enabled successfully.
Signed-off-by: Bilal Wasim <[email protected]>
---
drivers/soc/mediatek/mt8173-pm-domains.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/soc/mediatek/mt8173-pm-domains.h b/drivers/soc/mediatek/mt8173-pm-domains.h
index 3e8ee5dabb43..065b8195e7d6 100644
--- a/drivers/soc/mediatek/mt8173-pm-domains.h
+++ b/drivers/soc/mediatek/mt8173-pm-domains.h
@@ -63,6 +63,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
.ctl_offs = SPM_MFG_ASYNC_PWR_CON,
.sram_pdn_bits = GENMASK(11, 8),
.sram_pdn_ack_bits = 0,
+ .caps = MTK_SCPD_DOMAIN_SUPPLY,
},
[MT8173_POWER_DOMAIN_MFG_2D] = {
.sta_mask = PWR_STATUS_MFG_2D,
--
2.25.1
On Mon, Feb 1, 2021 at 1:45 PM Bilal Wasim <[email protected]> wrote:
>
> When "bus_prot_reg_update" is false, the driver should use
> INFRA_TOPAXI_PROTECTEN for both setting and clearing the bus
> protection. However, the driver does not use this mask for
> clearing bus protection which causes failure when booting
> the imgtec gpu.
>
> Corrected and tested with mt8173 chromebook.
>
> Signed-off-by: Bilal Wasim <[email protected]>
Reviewed-by: Hsin-Yi Wang <[email protected]>
> ---
> drivers/soc/mediatek/mtk-pm-domains.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
> index 141dc76054e6..7454c0b4f768 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.h
> +++ b/drivers/soc/mediatek/mtk-pm-domains.h
> @@ -60,7 +60,7 @@
> #define BUS_PROT_UPDATE_TOPAXI(_mask) \
> BUS_PROT_UPDATE(_mask, \
> INFRA_TOPAXI_PROTECTEN, \
> - INFRA_TOPAXI_PROTECTEN_CLR, \
> + INFRA_TOPAXI_PROTECTEN, \
> INFRA_TOPAXI_PROTECTSTA1)
>
> struct scpsys_bus_prot_data {
> --
> 2.25.1
>
On Mon, Feb 1, 2021 at 1:45 PM Bilal Wasim <[email protected]> wrote:
>
> The mfg_async power domain in mt8173 is used to power up imgtec
> gpu. This domain requires the da9211 regulator to be enabled before
> the power domain can be enabled successfully.
>
> Signed-off-by: Bilal Wasim <[email protected]>
Reviewed-by: Hsin-Yi Wang <[email protected]>
> ---
> drivers/soc/mediatek/mt8173-pm-domains.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/soc/mediatek/mt8173-pm-domains.h b/drivers/soc/mediatek/mt8173-pm-domains.h
> index 3e8ee5dabb43..065b8195e7d6 100644
> --- a/drivers/soc/mediatek/mt8173-pm-domains.h
> +++ b/drivers/soc/mediatek/mt8173-pm-domains.h
> @@ -63,6 +63,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
> .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = 0,
> + .caps = MTK_SCPD_DOMAIN_SUPPLY,
> },
> [MT8173_POWER_DOMAIN_MFG_2D] = {
> .sta_mask = PWR_STATUS_MFG_2D,
> --
> 2.25.1
>
Hi Bilal,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on soc/for-next]
[also build test ERROR on clk/clk-next linux/master next-20210125]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Bilal-Wasim/Misc-bug-fixes-in-mtk-power-domain-driver/20210201-135519
base: https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git for-next
config: arc-randconfig-r006-20210201 (attached as .config)
compiler: arceb-elf-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/75afc46e31ee3d523fd11e48a5b9127b8d6a3718
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Bilal-Wasim/Misc-bug-fixes-in-mtk-power-domain-driver/20210201-135519
git checkout 75afc46e31ee3d523fd11e48a5b9127b8d6a3718
# save the attached .config to linux build tree
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=arc
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <[email protected]>
All errors (new ones prefixed by >>):
In file included from drivers/soc/mediatek/mtk-pm-domains.c:18:
>> drivers/soc/mediatek/mt8173-pm-domains.h:66:11: error: 'MTK_SCPD_DOMAIN_SUPPLY' undeclared here (not in a function)
66 | .caps = MTK_SCPD_DOMAIN_SUPPLY,
| ^~~~~~~~~~~~~~~~~~~~~~
vim +/MTK_SCPD_DOMAIN_SUPPLY +66 drivers/soc/mediatek/mt8173-pm-domains.h
8
9 /*
10 * MT8173 power domain support
11 */
12
13 static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
14 [MT8173_POWER_DOMAIN_VDEC] = {
15 .sta_mask = PWR_STATUS_VDEC,
16 .ctl_offs = SPM_VDE_PWR_CON,
17 .sram_pdn_bits = GENMASK(11, 8),
18 .sram_pdn_ack_bits = GENMASK(12, 12),
19 },
20 [MT8173_POWER_DOMAIN_VENC] = {
21 .sta_mask = PWR_STATUS_VENC,
22 .ctl_offs = SPM_VEN_PWR_CON,
23 .sram_pdn_bits = GENMASK(11, 8),
24 .sram_pdn_ack_bits = GENMASK(15, 12),
25 },
26 [MT8173_POWER_DOMAIN_ISP] = {
27 .sta_mask = PWR_STATUS_ISP,
28 .ctl_offs = SPM_ISP_PWR_CON,
29 .sram_pdn_bits = GENMASK(11, 8),
30 .sram_pdn_ack_bits = GENMASK(13, 12),
31 },
32 [MT8173_POWER_DOMAIN_MM] = {
33 .sta_mask = PWR_STATUS_DISP,
34 .ctl_offs = SPM_DIS_PWR_CON,
35 .sram_pdn_bits = GENMASK(11, 8),
36 .sram_pdn_ack_bits = GENMASK(12, 12),
37 .bp_infracfg = {
38 BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MM_M0 |
39 MT8173_TOP_AXI_PROT_EN_MM_M1),
40 },
41 },
42 [MT8173_POWER_DOMAIN_VENC_LT] = {
43 .sta_mask = PWR_STATUS_VENC_LT,
44 .ctl_offs = SPM_VEN2_PWR_CON,
45 .sram_pdn_bits = GENMASK(11, 8),
46 .sram_pdn_ack_bits = GENMASK(15, 12),
47 },
48 [MT8173_POWER_DOMAIN_AUDIO] = {
49 .sta_mask = PWR_STATUS_AUDIO,
50 .ctl_offs = SPM_AUDIO_PWR_CON,
51 .sram_pdn_bits = GENMASK(11, 8),
52 .sram_pdn_ack_bits = GENMASK(15, 12),
53 },
54 [MT8173_POWER_DOMAIN_USB] = {
55 .sta_mask = PWR_STATUS_USB,
56 .ctl_offs = SPM_USB_PWR_CON,
57 .sram_pdn_bits = GENMASK(11, 8),
58 .sram_pdn_ack_bits = GENMASK(15, 12),
59 .caps = MTK_SCPD_ACTIVE_WAKEUP,
60 },
61 [MT8173_POWER_DOMAIN_MFG_ASYNC] = {
62 .sta_mask = PWR_STATUS_MFG_ASYNC,
63 .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
64 .sram_pdn_bits = GENMASK(11, 8),
65 .sram_pdn_ack_bits = 0,
> 66 .caps = MTK_SCPD_DOMAIN_SUPPLY,
67 },
68 [MT8173_POWER_DOMAIN_MFG_2D] = {
69 .sta_mask = PWR_STATUS_MFG_2D,
70 .ctl_offs = SPM_MFG_2D_PWR_CON,
71 .sram_pdn_bits = GENMASK(11, 8),
72 .sram_pdn_ack_bits = GENMASK(13, 12),
73 },
74 [MT8173_POWER_DOMAIN_MFG] = {
75 .sta_mask = PWR_STATUS_MFG,
76 .ctl_offs = SPM_MFG_PWR_CON,
77 .sram_pdn_bits = GENMASK(13, 8),
78 .sram_pdn_ack_bits = GENMASK(21, 16),
79 .bp_infracfg = {
80 BUS_PROT_UPDATE_TOPAXI(MT8173_TOP_AXI_PROT_EN_MFG_S |
81 MT8173_TOP_AXI_PROT_EN_MFG_M0 |
82 MT8173_TOP_AXI_PROT_EN_MFG_M1 |
83 MT8173_TOP_AXI_PROT_EN_MFG_SNOOP_OUT),
84 },
85 },
86 };
87
---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/[email protected]
On 01/02/2021 06:45, Bilal Wasim wrote:
> When "bus_prot_reg_update" is false, the driver should use
> INFRA_TOPAXI_PROTECTEN for both setting and clearing the bus
> protection. However, the driver does not use this mask for
> clearing bus protection which causes failure when booting
> the imgtec gpu.
>
> Corrected and tested with mt8173 chromebook.
>
> Signed-off-by: Bilal Wasim <[email protected]>
> ---
> drivers/soc/mediatek/mtk-pm-domains.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/soc/mediatek/mtk-pm-domains.h b/drivers/soc/mediatek/mtk-pm-domains.h
> index 141dc76054e6..7454c0b4f768 100644
> --- a/drivers/soc/mediatek/mtk-pm-domains.h
> +++ b/drivers/soc/mediatek/mtk-pm-domains.h
> @@ -60,7 +60,7 @@
> #define BUS_PROT_UPDATE_TOPAXI(_mask) \
> BUS_PROT_UPDATE(_mask, \
> INFRA_TOPAXI_PROTECTEN, \
> - INFRA_TOPAXI_PROTECTEN_CLR, \
> + INFRA_TOPAXI_PROTECTEN, \
BUS_PROT_UPDATE sets bus_prot_reg_update to true, which contradicts what you say
in the commit message.
Please clarify.
Regards,
Matthias
> INFRA_TOPAXI_PROTECTSTA1)
>
> struct scpsys_bus_prot_data {
>
On 01/02/2021 06:45, Bilal Wasim wrote:
> The mfg_async power domain in mt8173 is used to power up imgtec
> gpu. This domain requires the da9211 regulator to be enabled before
> the power domain can be enabled successfully.
>
> Signed-off-by: Bilal Wasim <[email protected]>
> ---
> drivers/soc/mediatek/mt8173-pm-domains.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/soc/mediatek/mt8173-pm-domains.h b/drivers/soc/mediatek/mt8173-pm-domains.h
> index 3e8ee5dabb43..065b8195e7d6 100644
> --- a/drivers/soc/mediatek/mt8173-pm-domains.h
> +++ b/drivers/soc/mediatek/mt8173-pm-domains.h
> @@ -63,6 +63,7 @@ static const struct scpsys_domain_data scpsys_domain_data_mt8173[] = {
> .ctl_offs = SPM_MFG_ASYNC_PWR_CON,
> .sram_pdn_bits = GENMASK(11, 8),
> .sram_pdn_ack_bits = 0,
> + .caps = MTK_SCPD_DOMAIN_SUPPLY,
> },
> [MT8173_POWER_DOMAIN_MFG_2D] = {
> .sta_mask = PWR_STATUS_MFG_2D,
>
We are missing a third patch for the DTS to actually add the regulator. Please
provide them for both, mt8173-evb.dts and mt8173-elm.dts
Thanks a lot and I'm very happy to see you starting to contribute!
Regards,
Matthias
On Mon, 1 Feb 2021 09:59:47 +0100
Matthias Brugger <[email protected]> wrote:
> On 01/02/2021 06:45, Bilal Wasim wrote:
> > When "bus_prot_reg_update" is false, the driver should use
> > INFRA_TOPAXI_PROTECTEN for both setting and clearing the bus
> > protection. However, the driver does not use this mask for
> > clearing bus protection which causes failure when booting
> > the imgtec gpu.
> >
> > Corrected and tested with mt8173 chromebook.
> >
> > Signed-off-by: Bilal Wasim <[email protected]>
> > ---
> > drivers/soc/mediatek/mtk-pm-domains.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/soc/mediatek/mtk-pm-domains.h
> > b/drivers/soc/mediatek/mtk-pm-domains.h index
> > 141dc76054e6..7454c0b4f768 100644 ---
> > a/drivers/soc/mediatek/mtk-pm-domains.h +++
> > b/drivers/soc/mediatek/mtk-pm-domains.h @@ -60,7 +60,7 @@
> > #define BUS_PROT_UPDATE_TOPAXI(_mask)
> > \ BUS_PROT_UPDATE(_mask, \
> > INFRA_TOPAXI_PROTECTEN,
> > \
> > - INFRA_TOPAXI_PROTECTEN_CLR,
> > \
> > + INFRA_TOPAXI_PROTECTEN,
> > \
>
> BUS_PROT_UPDATE sets bus_prot_reg_update to true, which contradicts
> what you say in the commit message.
>
> Please clarify.
>
Yes, that's a problem in the commit message - Will fix and send out a
v2.
Thanks,
Bilal
> Regards,
> Matthias
>
> > INFRA_TOPAXI_PROTECTSTA1)
> >
> > struct scpsys_bus_prot_data {
> >