Hi Oliver,
On Tue, Mar 23, 2021 at 5:15 PM Oliver Stäbler
<[email protected]> wrote:
>
> Fix address of the pad control register
> (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0) for SD1_DATA0_GPIO2_IO2. This seems
> to be a typo but it leads to an exception when pinctrl is applied due to
> wrong memory address access.
>
> Signed-off-by: Oliver Stäbler <[email protected]>
I checked in the RM and your patch is correct, thanks:
Reviewed-by: Fabio Estevam <[email protected]>
I will send a patch fixing imx8mq-pinfunc.h as it has the same error.
Fix address of the pad control register
(IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0) for SD1_DATA0_GPIO2_IO2. This seems
to be a typo but it leads to an exception when pinctrl is applied due to
wrong memory address access.
Signed-off-by: Oliver Stäbler <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h | 2 +-
arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h
index 5ccc4cc91959d..a003e6af33533 100644
--- a/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h
+++ b/arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h
@@ -124,7 +124,7 @@
#define MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
-#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0
+#define MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
#define MX8MM_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
#define MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0
diff --git a/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h b/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h
index b94b02080a344..68e8fa1729741 100644
--- a/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h
+++ b/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h
@@ -130,7 +130,7 @@
#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0x0A4 0x30C 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1 0x0A4 0x30C 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x0A8 0x310 0x000 0x0 0x0
-#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x31 0x000 0x5 0x0
+#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2 0x0A8 0x310 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x0AC 0x314 0x000 0x0 0x0
#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3 0x0AC 0x314 0x000 0x5 0x0
#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x0B0 0x318 0x000 0x0 0x0
--
2.26.2
Hi Oliver,
On Wed, Mar 24, 2021 at 10:28 AM Oliver Stäbler
<[email protected]> wrote:
>
> Fix address of the pad control register
> (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0) for SD1_DATA0_GPIO2_IO2. This seems
> to be a typo but it leads to an exception when pinctrl is applied due to
> wrong memory address access.
>
> Signed-off-by: Oliver Stäbler <[email protected]>
Thanks for the fix:
Reviewed-by: Fabio Estevam <[email protected]>
On Wed, 24 Mar 2021 14:28:41 +0100, Oliver St?bler wrote:
> Fix address of the pad control register
> (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0) for SD1_DATA0_GPIO2_IO2. This seems
> to be a typo but it leads to an exception when pinctrl is applied due to
> wrong memory address access.
>
> Signed-off-by: Oliver St?bler <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h | 2 +-
> arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
>
Acked-by: Rob Herring <[email protected]>
On Wed, Mar 24, 2021 at 02:28:41PM +0100, Oliver St?bler wrote:
> Fix address of the pad control register
> (IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0) for SD1_DATA0_GPIO2_IO2. This seems
> to be a typo but it leads to an exception when pinctrl is applied due to
> wrong memory address access.
>
> Signed-off-by: Oliver St?bler <[email protected]>
Applied, thanks.