2021-07-14 12:13:44

by Oliver Graute

Subject: [PATCH v1] arm64: dts: imx8qm: added System MMU

added node for System MMU

Cc: Rob Herring <[email protected]>
Cc: Sascha Hauer <[email protected]>
Cc: Fabio Estevam <[email protected]>
Cc: Dong Aisheng <[email protected]>

Signed-off-by: Oliver Graute <[email protected]>
---
arch/arm64/boot/dts/freescale/imx8qm.dtsi | 17 +++++++++++++++++
1 file changed, 17 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index 7efc0add74ea..fa827ed04e09 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -140,6 +140,23 @@
method = "smc";
};

+ smmu: iommu@51400000 {
+ compatible = "arm,mmu-500";
+ interrupt-parent = <&gic>;
+ reg = <0 0x51400000 0 0x40000>;
+ #global-interrupts = <1>;
+ #iommu-cells = <2>;
+ interrupts = <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
+ <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
--
2.17.1

2021-07-14 14:38:48

by Robin Murphy

Subject: Re: [PATCH v1] arm64: dts: imx8qm: added System MMU

On 2021-07-14 13:09, Oliver Graute wrote:
> added node for System MMU

Note that it's a bit of a dangerous game to enable an SMMU without the
complete Stream ID topology for *all* its upstream devices also
described, since CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT will ruin
peoples' day. It might be more polite to add it in a disabled state
until every "iommus" property has been filled in, so that people who do
want to play with it for specific devices in the meantime can easily
just flip the status (while taking the necessary precautions), but
people who don't care won't be inadvertently affected regardless of
their kernel config. I'm assuming an SMMU with 32 contexts has more than
a single USB controller behind it...

Robin.

> Cc: Rob Herring <[email protected]>
> Cc: Sascha Hauer <[email protected]>
> Cc: Fabio Estevam <[email protected]>
> Cc: Dong Aisheng <[email protected]>
>
> Signed-off-by: Oliver Graute <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/imx8qm.dtsi | 17 +++++++++++++++++
> 1 file changed, 17 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> index 7efc0add74ea..fa827ed04e09 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
> @@ -140,6 +140,23 @@
> method = "smc";
> };
>
> + smmu: iommu@51400000 {
> + compatible = "arm,mmu-500";
> + interrupt-parent = <&gic>;
> + reg = <0 0x51400000 0 0x40000>;
> + #global-interrupts = <1>;
> + #iommu-cells = <2>;
> + interrupts = <0 32 4>,
> + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>;
> + };
> +
> timer {
> compatible = "arm,armv8-timer";
> interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Physical Secure */
>

2021-07-15 09:10:35

by Oliver Graute

Subject: Re: [PATCH v1] arm64: dts: imx8qm: added System MMU

On 14/07/21, Robin Murphy wrote:
> On 2021-07-14 13:09, Oliver Graute wrote:
> > added node for System MMU
>
> Note that it's a bit of a dangerous game to enable an SMMU without the
> complete Stream ID topology for *all* its upstream devices also described,
> since CONFIG_ARM_SMMU_DISABLE_BYPASS_BY_DEFAULT will ruin peoples' day. It
> might be more polite to add it in a disabled state until every "iommus"
> property has been filled in, so that people who do want to play with it for
> specific devices in the meantime can easily just flip the status (while
> taking the necessary precautions), but people who don't care won't be
> inadvertently affected regardless of their kernel config. I'm assuming an
> SMMU with 32 contexts has more than a single USB controller behind it...

thx for the explanation. So I will set this node to disabled state in
next version of this patch.
>
> > };
> > + smmu: iommu@51400000 {
> > + compatible = "arm,mmu-500";
> > + interrupt-parent = <&gic>;
> > + reg = <0 0x51400000 0 0x40000>;
> > + #global-interrupts = <1>;
> > + #iommu-cells = <2>;
> > + interrupts = <0 32 4>,
> > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>,
> > + <0 32 4>, <0 32 4>, <0 32 4>, <0 32 4>;
status = "disabled";
> > + };

Best regards,

Oliver