From: Manivannan Sadhasivam <[email protected]>
Add DTS bindings for the HiKey 970 board's PCIe hardware.
Co-developed-by: Mauro Carvalho Chehab <[email protected]>
Signed-off-by: Manivannan Sadhasivam <[email protected]>
Signed-off-by: Mauro Carvalho Chehab <[email protected]>
---
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 71 +++++++++++++++++++
.../boot/dts/hisilicon/hikey970-pmic.dtsi | 1 -
drivers/pci/controller/dwc/pcie-kirin.c | 12 ----
3 files changed, 71 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 1f228612192c..6dfcfcfeedae 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -177,6 +177,12 @@ sctrl: sctrl@fff0a000 {
#clock-cells = <1>;
};
+ pmctrl: pmctrl@fff31000 {
+ compatible = "hisilicon,hi3670-pmctrl", "syscon";
+ reg = <0x0 0xfff31000 0x0 0x1000>;
+ #clock-cells = <1>;
+ };
+
iomcu: iomcu@ffd7e000 {
compatible = "hisilicon,hi3670-iomcu", "syscon";
reg = <0x0 0xffd7e000 0x0 0x1000>;
@@ -660,6 +666,71 @@ gpio28: gpio@fff1d000 {
clock-names = "apb_pclk";
};
+ its_pcie: interrupt-controller@f4000000 {
+ compatible = "arm,gic-v3-its";
+ msi-controller;
+ reg = <0x0 0xf5100000 0x0 0x100000>;
+ };
+
+ pcie_phy: pcie-phy@fc000000 {
+ compatible = "hisilicon,hi970-pcie-phy";
+ reg = <0x0 0xfc000000 0x0 0x80000>;
+
+ phy-supply = <&ldo33>;
+
+ clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>,
+ <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>,
+ <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3670_ACLK_GATE_PCIE>;
+ clock-names = "phy_ref", "aux",
+ "apb_phy", "apb_sys",
+ "aclk";
+
+ reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >,
+ <&gpio3 1 0 >, <&gpio27 4 0 >;
+
+ clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >,
+ <&gpio17 0 0 >;
+
+ /* vboost iboost pre post main */
+ hisilicon,eye-diagram-param = <0xFFFFFFFF 0xFFFFFFFF
+ 0xFFFFFFFF 0xFFFFFFFF
+ 0xFFFFFFFF>;
+
+ #phy-cells = <0>;
+ };
+
+ pcie@f4000000 {
+ compatible = "hisilicon,kirin970-pcie";
+ reg = <0x0 0xf4000000 0x0 0x1000000>,
+ <0x0 0xfc180000 0x0 0x1000>,
+ <0x0 0xf5000000 0x0 0x2000>;
+ reg-names = "dbi", "apb", "config";
+ bus-range = <0x0 0x1>;
+ msi-parent = <&its_pcie>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ phys = <&pcie_phy>;
+ ranges = <0x02000000 0x0 0x00000000
+ 0x0 0xf6000000
+ 0x0 0x02000000>;
+ num-lanes = <1>;
+ #interrupt-cells = <1>;
+ interrupts = <0 283 4>;
+ interrupt-names = "msi";
+ interrupt-map-mask = <0 0 0 7>;
+ interrupt-map = <0x0 0 0 1
+ &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 2
+ &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 3
+ &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
+ <0x0 0 0 4
+ &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
/* UFS */
ufs: ufs@ff3c0000 {
compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi
index 48c739eacba0..03452e627641 100644
--- a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi
@@ -73,7 +73,6 @@ ldo33: LDO33 { /* PEX8606 */
regulator-name = "ldo33";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3300000>;
- regulator-boot-on;
};
ldo34: LDO34 { /* GPS AUX IN VDD */
diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c
index bfc0513f7b15..9dad14929538 100644
--- a/drivers/pci/controller/dwc/pcie-kirin.c
+++ b/drivers/pci/controller/dwc/pcie-kirin.c
@@ -347,18 +347,6 @@ static const struct regmap_config pcie_kirin_regmap_conf = {
.reg_stride = 4,
};
-/* Registers in PCIeCTRL */
-static inline void kirin_apb_ctrl_writel(struct kirin_pcie *kirin_pcie,
- u32 val, u32 reg)
-{
- writel(val, kirin_pcie->apb_base + reg);
-}
-
-static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie, u32 reg)
-{
- return readl(kirin_pcie->apb_base + reg);
-}
-
static long kirin_pcie_get_resource(struct kirin_pcie *kirin_pcie,
struct platform_device *pdev)
{
--
2.31.1
On Wed, Jul 21, 2021 at 10:39:10AM +0200, Mauro Carvalho Chehab wrote:
> From: Manivannan Sadhasivam <[email protected]>
>
> Add DTS bindings for the HiKey 970 board's PCIe hardware.
>
> Co-developed-by: Mauro Carvalho Chehab <[email protected]>
> Signed-off-by: Manivannan Sadhasivam <[email protected]>
> Signed-off-by: Mauro Carvalho Chehab <[email protected]>
> ---
> arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 71 +++++++++++++++++++
> .../boot/dts/hisilicon/hikey970-pmic.dtsi | 1 -
> drivers/pci/controller/dwc/pcie-kirin.c | 12 ----
> 3 files changed, 71 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> index 1f228612192c..6dfcfcfeedae 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> @@ -177,6 +177,12 @@ sctrl: sctrl@fff0a000 {
> #clock-cells = <1>;
> };
>
> + pmctrl: pmctrl@fff31000 {
> + compatible = "hisilicon,hi3670-pmctrl", "syscon";
> + reg = <0x0 0xfff31000 0x0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
Irrelevant change to this patch.
> iomcu: iomcu@ffd7e000 {
> compatible = "hisilicon,hi3670-iomcu", "syscon";
> reg = <0x0 0xffd7e000 0x0 0x1000>;
> @@ -660,6 +666,71 @@ gpio28: gpio@fff1d000 {
> clock-names = "apb_pclk";
> };
>
[...]
> + #interrupt-cells = <1>;
> + interrupts = <0 283 4>;
Use the DT flag for interrupts instead of hardcoded value
> + interrupt-names = "msi";
> + interrupt-map-mask = <0 0 0 7>;
> + interrupt-map = <0x0 0 0 1
> + &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
> + <0x0 0 0 2
> + &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> + <0x0 0 0 3
> + &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
> + <0x0 0 0 4
> + &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> /* UFS */
> ufs: ufs@ff3c0000 {
> compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
> diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi
> index 48c739eacba0..03452e627641 100644
> --- a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi
> @@ -73,7 +73,6 @@ ldo33: LDO33 { /* PEX8606 */
> regulator-name = "ldo33";
> regulator-min-microvolt = <2500000>;
> regulator-max-microvolt = <3300000>;
> - regulator-boot-on;
Again, irrelevant.
> };
>
> ldo34: LDO34 { /* GPS AUX IN VDD */
> diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c
> index bfc0513f7b15..9dad14929538 100644
> --- a/drivers/pci/controller/dwc/pcie-kirin.c
> +++ b/drivers/pci/controller/dwc/pcie-kirin.c
> @@ -347,18 +347,6 @@ static const struct regmap_config pcie_kirin_regmap_conf = {
> .reg_stride = 4,
> };
>
> -/* Registers in PCIeCTRL */
> -static inline void kirin_apb_ctrl_writel(struct kirin_pcie *kirin_pcie,
> - u32 val, u32 reg)
> -{
> - writel(val, kirin_pcie->apb_base + reg);
> -}
> -
> -static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie, u32 reg)
> -{
> - return readl(kirin_pcie->apb_base + reg);
> -}
> -
Same here...
Thanks,
Mani
Em Thu, 22 Jul 2021 19:06:28 +0530
Manivannan Sadhasivam <[email protected]> escreveu:
> On Wed, Jul 21, 2021 at 10:39:10AM +0200, Mauro Carvalho Chehab wrote:
> > From: Manivannan Sadhasivam <[email protected]>
> >
> > Add DTS bindings for the HiKey 970 board's PCIe hardware.
> >
> > Co-developed-by: Mauro Carvalho Chehab <[email protected]>
> > Signed-off-by: Manivannan Sadhasivam <[email protected]>
> > Signed-off-by: Mauro Carvalho Chehab <[email protected]>
> > ---
> > arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 71 +++++++++++++++++++
> > .../boot/dts/hisilicon/hikey970-pmic.dtsi | 1 -
> > drivers/pci/controller/dwc/pcie-kirin.c | 12 ----
> > 3 files changed, 71 insertions(+), 13 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> > index 1f228612192c..6dfcfcfeedae 100644
> > --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> > +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> > @@ -177,6 +177,12 @@ sctrl: sctrl@fff0a000 {
> > #clock-cells = <1>;
> > };
> >
> > + pmctrl: pmctrl@fff31000 {
> > + compatible = "hisilicon,hi3670-pmctrl", "syscon";
> > + reg = <0x0 0xfff31000 0x0 0x1000>;
> > + #clock-cells = <1>;
> > + };
> > +
>
> Irrelevant change to this patch.
Huh?
This is used by PCIe PHY, as part of the power on procedures:
+static int hi3670_pcie_noc_power(struct hi3670_pcie_phy *phy, bool enable)
+{
+ struct device *dev = phy->dev;
+ u32 time = 100;
+ unsigned int val = NOC_PW_MASK;
+ int rst;
+
+ if (enable)
+ val = NOC_PW_MASK | NOC_PW_SET_BIT;
+ else
+ val = NOC_PW_MASK;
+ rst = enable ? 1 : 0;
+
+ regmap_write(phy->pmctrl, NOC_POWER_IDLEREQ_1, val);
>
> > iomcu: iomcu@ffd7e000 {
> > compatible = "hisilicon,hi3670-iomcu", "syscon";
> > reg = <0x0 0xffd7e000 0x0 0x1000>;
> > @@ -660,6 +666,71 @@ gpio28: gpio@fff1d000 {
> > clock-names = "apb_pclk";
> > };
> >
>
> [...]
>
> > + #interrupt-cells = <1>;
> > + interrupts = <0 283 4>;
>
> Use the DT flag for interrupts instead of hardcoded value
Do you mean like this?
interrupts = <0 283 IRQ_TYPE_LEVEL_HIGH>;
>
> > + interrupt-names = "msi";
> > + interrupt-map-mask = <0 0 0 7>;
> > + interrupt-map = <0x0 0 0 1
> > + &gic GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>,
> > + <0x0 0 0 2
> > + &gic GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>,
> > + <0x0 0 0 3
> > + &gic GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>,
> > + <0x0 0 0 4
> > + &gic GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>;
> > + };
> > +
> > /* UFS */
> > ufs: ufs@ff3c0000 {
> > compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
> > diff --git a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi
> > index 48c739eacba0..03452e627641 100644
> > --- a/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi
> > +++ b/arch/arm64/boot/dts/hisilicon/hikey970-pmic.dtsi
> > @@ -73,7 +73,6 @@ ldo33: LDO33 { /* PEX8606 */
> > regulator-name = "ldo33";
> > regulator-min-microvolt = <2500000>;
> > regulator-max-microvolt = <3300000>;
> > - regulator-boot-on;
>
> Again, irrelevant.
I'll move it to the USB patch series, where the PMIC is added.
>
> > };
> >
> > ldo34: LDO34 { /* GPS AUX IN VDD */
> > diff --git a/drivers/pci/controller/dwc/pcie-kirin.c b/drivers/pci/controller/dwc/pcie-kirin.c
> > index bfc0513f7b15..9dad14929538 100644
> > --- a/drivers/pci/controller/dwc/pcie-kirin.c
> > +++ b/drivers/pci/controller/dwc/pcie-kirin.c
> > @@ -347,18 +347,6 @@ static const struct regmap_config pcie_kirin_regmap_conf = {
> > .reg_stride = 4,
> > };
> >
> > -/* Registers in PCIeCTRL */
> > -static inline void kirin_apb_ctrl_writel(struct kirin_pcie *kirin_pcie,
> > - u32 val, u32 reg)
> > -{
> > - writel(val, kirin_pcie->apb_base + reg);
> > -}
> > -
> > -static inline u32 kirin_apb_ctrl_readl(struct kirin_pcie *kirin_pcie, u32 reg)
> > -{
> > - return readl(kirin_pcie->apb_base + reg);
> > -}
> > -
>
> Same here...
This hunk should be on patch 03/10. Probably some rebase added it here by
mistake. I'll fix it on v8.
Thanks,
Mauro
On Fri, Jul 23, 2021 at 08:53:18AM +0200, Mauro Carvalho Chehab wrote:
> Em Thu, 22 Jul 2021 19:06:28 +0530
> Manivannan Sadhasivam <[email protected]> escreveu:
>
> > On Wed, Jul 21, 2021 at 10:39:10AM +0200, Mauro Carvalho Chehab wrote:
> > > From: Manivannan Sadhasivam <[email protected]>
> > >
> > > Add DTS bindings for the HiKey 970 board's PCIe hardware.
> > >
> > > Co-developed-by: Mauro Carvalho Chehab <[email protected]>
> > > Signed-off-by: Manivannan Sadhasivam <[email protected]>
> > > Signed-off-by: Mauro Carvalho Chehab <[email protected]>
> > > ---
> > > arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 71 +++++++++++++++++++
> > > .../boot/dts/hisilicon/hikey970-pmic.dtsi | 1 -
> > > drivers/pci/controller/dwc/pcie-kirin.c | 12 ----
> > > 3 files changed, 71 insertions(+), 13 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> > > index 1f228612192c..6dfcfcfeedae 100644
> > > --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> > > +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> > > @@ -177,6 +177,12 @@ sctrl: sctrl@fff0a000 {
> > > #clock-cells = <1>;
> > > };
> > >
> > > + pmctrl: pmctrl@fff31000 {
> > > + compatible = "hisilicon,hi3670-pmctrl", "syscon";
> > > + reg = <0x0 0xfff31000 0x0 0x1000>;
> > > + #clock-cells = <1>;
> > > + };
> > > +
> >
> > Irrelevant change to this patch.
>
> Huh?
>
> This is used by PCIe PHY, as part of the power on procedures:
>
> +static int hi3670_pcie_noc_power(struct hi3670_pcie_phy *phy, bool enable)
> +{
> + struct device *dev = phy->dev;
> + u32 time = 100;
> + unsigned int val = NOC_PW_MASK;
> + int rst;
> +
> + if (enable)
> + val = NOC_PW_MASK | NOC_PW_SET_BIT;
> + else
> + val = NOC_PW_MASK;
> + rst = enable ? 1 : 0;
> +
> + regmap_write(phy->pmctrl, NOC_POWER_IDLEREQ_1, val);
>
>
Ah... you're hardcoding the syscon compatible in driver. Sorry missed that.
But if these syscon nodes are independent memory regions or belong to non
PCI/PHY memory map, you could've fetched the reference through a DT property
along with the offset then used it in driver.
Like,
pcie_phy: pcie-phy@fc000000 {
...
hisilicon,noc-power-regs = <&pmctrl 0x38c>;
hisilicon,sctrl-cmos-regs = <&sctrl 0x60>;
...
};
The benefit of doing this way is, if the pmctrl, sctrl register layout changes
in future, you can handle it without any issues.
>
> >
> > > iomcu: iomcu@ffd7e000 {
> > > compatible = "hisilicon,hi3670-iomcu", "syscon";
> > > reg = <0x0 0xffd7e000 0x0 0x1000>;
> > > @@ -660,6 +666,71 @@ gpio28: gpio@fff1d000 {
> > > clock-names = "apb_pclk";
> > > };
> > >
> >
> > [...]
> >
> > > + #interrupt-cells = <1>;
> > > + interrupts = <0 283 4>;
> >
> > Use the DT flag for interrupts instead of hardcoded value
>
> Do you mean like this?
>
> interrupts = <0 283 IRQ_TYPE_LEVEL_HIGH>;
>
yes but you could also use,
interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>;
Thanks,
Mani
Em Sat, 24 Jul 2021 09:41:50 +0530
Manivannan Sadhasivam <[email protected]> escreveu:
> On Fri, Jul 23, 2021 at 08:53:18AM +0200, Mauro Carvalho Chehab wrote:
> > Em Thu, 22 Jul 2021 19:06:28 +0530
> > Manivannan Sadhasivam <[email protected]> escreveu:
> >
> > > On Wed, Jul 21, 2021 at 10:39:10AM +0200, Mauro Carvalho Chehab wrote:
> > > > From: Manivannan Sadhasivam <[email protected]>
> > > >
> > > > Add DTS bindings for the HiKey 970 board's PCIe hardware.
> > > >
> > > > Co-developed-by: Mauro Carvalho Chehab <[email protected]>
> > > > Signed-off-by: Manivannan Sadhasivam <[email protected]>
> > > > Signed-off-by: Mauro Carvalho Chehab <[email protected]>
> > > > ---
> > > > arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 71 +++++++++++++++++++
> > > > .../boot/dts/hisilicon/hikey970-pmic.dtsi | 1 -
> > > > drivers/pci/controller/dwc/pcie-kirin.c | 12 ----
> > > > 3 files changed, 71 insertions(+), 13 deletions(-)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> > > > index 1f228612192c..6dfcfcfeedae 100644
> > > > --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> > > > +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> > > > @@ -177,6 +177,12 @@ sctrl: sctrl@fff0a000 {
> > > > #clock-cells = <1>;
> > > > };
> > > >
> > > > + pmctrl: pmctrl@fff31000 {
> > > > + compatible = "hisilicon,hi3670-pmctrl", "syscon";
> > > > + reg = <0x0 0xfff31000 0x0 0x1000>;
> > > > + #clock-cells = <1>;
> > > > + };
> > > > +
> > >
> > > Irrelevant change to this patch.
> >
> > Huh?
> >
> > This is used by PCIe PHY, as part of the power on procedures:
> >
> > +static int hi3670_pcie_noc_power(struct hi3670_pcie_phy *phy, bool enable)
> > +{
> > + struct device *dev = phy->dev;
> > + u32 time = 100;
> > + unsigned int val = NOC_PW_MASK;
> > + int rst;
> > +
> > + if (enable)
> > + val = NOC_PW_MASK | NOC_PW_SET_BIT;
> > + else
> > + val = NOC_PW_MASK;
> > + rst = enable ? 1 : 0;
> > +
> > + regmap_write(phy->pmctrl, NOC_POWER_IDLEREQ_1, val);
> >
> >
>
> Ah... you're hardcoding the syscon compatible in driver. Sorry missed that.
>
> But if these syscon nodes are independent memory regions or belong to non
> PCI/PHY memory map, you could've fetched the reference through a DT property
> along with the offset then used it in driver.
>
> Like,
>
> pcie_phy: pcie-phy@fc000000 {
> ...
> hisilicon,noc-power-regs = <&pmctrl 0x38c>;
> hisilicon,sctrl-cmos-regs = <&sctrl 0x60>;
> ...
> };
>
> The benefit of doing this way is, if the pmctrl, sctrl register layout changes
> in future, you can handle it without any issues.
Interesting approach, but probably overkill. I mean, the register mapping
here should be the same for all Kirin 970 PHY based devices. A PHY for a
different SoC will likely have other differences than just those two regs.
Regards,
Mauro
On Wed, Jul 21, 2021 at 3:39 AM Mauro Carvalho Chehab
<[email protected]> wrote:
>
> From: Manivannan Sadhasivam <[email protected]>
>
> Add DTS bindings for the HiKey 970 board's PCIe hardware.
>
> Co-developed-by: Mauro Carvalho Chehab <[email protected]>
> Signed-off-by: Manivannan Sadhasivam <[email protected]>
> Signed-off-by: Mauro Carvalho Chehab <[email protected]>
> ---
> arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 71 +++++++++++++++++++
> .../boot/dts/hisilicon/hikey970-pmic.dtsi | 1 -
> drivers/pci/controller/dwc/pcie-kirin.c | 12 ----
> 3 files changed, 71 insertions(+), 13 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> index 1f228612192c..6dfcfcfeedae 100644
> --- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> +++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
> @@ -177,6 +177,12 @@ sctrl: sctrl@fff0a000 {
> #clock-cells = <1>;
> };
>
> + pmctrl: pmctrl@fff31000 {
> + compatible = "hisilicon,hi3670-pmctrl", "syscon";
> + reg = <0x0 0xfff31000 0x0 0x1000>;
> + #clock-cells = <1>;
> + };
> +
> iomcu: iomcu@ffd7e000 {
> compatible = "hisilicon,hi3670-iomcu", "syscon";
> reg = <0x0 0xffd7e000 0x0 0x1000>;
> @@ -660,6 +666,71 @@ gpio28: gpio@fff1d000 {
> clock-names = "apb_pclk";
> };
>
> + its_pcie: interrupt-controller@f4000000 {
> + compatible = "arm,gic-v3-its";
> + msi-controller;
> + reg = <0x0 0xf5100000 0x0 0x100000>;
How does this h/w have a GIC-400 (which is GICv2) and then a GIC v3 ITS?
> + };
> +
> + pcie_phy: pcie-phy@fc000000 {
> + compatible = "hisilicon,hi970-pcie-phy";
> + reg = <0x0 0xfc000000 0x0 0x80000>;
> +
> + phy-supply = <&ldo33>;
> +
> + clocks = <&crg_ctrl HI3670_CLK_GATE_PCIEPHY_REF>,
> + <&crg_ctrl HI3670_CLK_GATE_PCIEAUX>,
> + <&crg_ctrl HI3670_PCLK_GATE_PCIE_PHY>,
> + <&crg_ctrl HI3670_PCLK_GATE_PCIE_SYS>,
> + <&crg_ctrl HI3670_ACLK_GATE_PCIE>;
> + clock-names = "phy_ref", "aux",
> + "apb_phy", "apb_sys",
> + "aclk";
> +
> + reset-gpios = <&gpio7 0 0 >, <&gpio25 2 0 >,
> + <&gpio3 1 0 >, <&gpio27 4 0 >;
> +
> + clkreq-gpios = <&gpio20 6 0 >, <&gpio27 3 0 >,
> + <&gpio17 0 0 >;
> +
> + /* vboost iboost pre post main */
> + hisilicon,eye-diagram-param = <0xFFFFFFFF 0xFFFFFFFF
> + 0xFFFFFFFF 0xFFFFFFFF
> + 0xFFFFFFFF>;
> +
> + #phy-cells = <0>;
> + };
> +
> + pcie@f4000000 {
> + compatible = "hisilicon,kirin970-pcie";
> + reg = <0x0 0xf4000000 0x0 0x1000000>,
> + <0x0 0xfc180000 0x0 0x1000>,
> + <0x0 0xf5000000 0x0 0x2000>;
> + reg-names = "dbi", "apb", "config";
> + bus-range = <0x0 0x1>;
> + msi-parent = <&its_pcie>;
This means the PCI host doesn't have a MSI controller...
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + phys = <&pcie_phy>;
> + ranges = <0x02000000 0x0 0x00000000
> + 0x0 0xf6000000
> + 0x0 0x02000000>;
> + num-lanes = <1>;
> + #interrupt-cells = <1>;
> + interrupts = <0 283 4>;
> + interrupt-names = "msi";
But then this says it does...