Some accumulated ls1028a dts changes from the SDK. Also included two
binding updates needed for these dts changes.
v2 updates:
- Rebased to v5.16-rc1
- Spinned off binding changes
- Removed optee enabling patch
- Dropped "arm64: dts: ls1028a-qds: enable optee node" as the board
doesn't support optee
Alex Marginean (1):
arm64: dts: ls1028a-qds: add overlays for various serdes protocols
Biwen Li (4):
arm64: dts: ls1028a: add ftm_alarm1 node to be used as wakeup source
arm64: dts: ls1028a: add flextimer based pwm nodes
arm64: dts: ls1028a-rdb: enable pwm0
arm64: dts: ls1028a-qds: move rtc node to the correct i2c bus
Li Yang (1):
arm64: dts: ls1028a-rdb: reorder nodes to be alphabetic
Vabhav Sharma (1):
arm64: dts: ls1028a-qds: enable lpuart1
Xiaowei Bao (1):
arm64: dts: ls1028a: Add PCIe EP nodes
arch/arm64/boot/dts/freescale/Makefile | 16 +++
.../dts/freescale/fsl-ls1028a-qds-13bb.dts | 113 +++++++++++++++
.../dts/freescale/fsl-ls1028a-qds-65bb.dts | 108 +++++++++++++++
.../dts/freescale/fsl-ls1028a-qds-7777.dts | 82 +++++++++++
.../dts/freescale/fsl-ls1028a-qds-85bb.dts | 107 ++++++++++++++
.../dts/freescale/fsl-ls1028a-qds-899b.dts | 75 ++++++++++
.../dts/freescale/fsl-ls1028a-qds-9999.dts | 79 +++++++++++
.../boot/dts/freescale/fsl-ls1028a-qds.dts | 39 ++++--
.../boot/dts/freescale/fsl-ls1028a-rdb.dts | 98 +++++++------
.../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 130 +++++++++++++++++-
10 files changed, 794 insertions(+), 53 deletions(-)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts
--
2.25.1
From: Biwen Li <[email protected]>
Add flextimer2 based ftm_alarm1 node and enable it to be the default rtc
wakeup source for rdb and qds boards instead of the original flextimer1
based ftm_alarm0. The ftm_alarm0 node hence is disabled by default.
Signed-off-by: Biwen Li <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 6 +++++-
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 6 +++++-
arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 9 +++++++++
3 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index 6e2a1da662fb..00d5b81bdef3 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -25,7 +25,7 @@ aliases {
serial1 = &duart1;
mmc0 = &esdhc;
mmc1 = &esdhc1;
- rtc1 = &ftm_alarm0;
+ rtc1 = &ftm_alarm1;
};
chosen {
@@ -234,6 +234,10 @@ mt35xu02g0: flash@0 {
};
};
+&ftm_alarm1 {
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index 7719f44bcaed..41900d351a92 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -21,7 +21,7 @@ aliases {
serial1 = &duart1;
mmc0 = &esdhc;
mmc1 = &esdhc1;
- rtc1 = &ftm_alarm0;
+ rtc1 = &ftm_alarm1;
};
chosen {
@@ -132,6 +132,10 @@ mt35xu02g0: flash@0 {
};
};
+&ftm_alarm1 {
+ status = "okay";
+};
+
&i2c0 {
status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 9efcaf68578c..ef9d17df2afa 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -1198,6 +1198,15 @@ ftm_alarm0: timer@2800000 {
reg = <0x0 0x2800000 0x0 0x10000>;
fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+
+ ftm_alarm1: timer@2810000 {
+ compatible = "fsl,ls1028a-ftm-alarm";
+ reg = <0x0 0x2810000 0x0 0x10000>;
+ fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
+ interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
};
--
2.25.1
Keep these overrides node in alphabetic order in order to prevent
unnoticed duplicated nodes.
Signed-off-by: Li Yang <[email protected]>
---
.../boot/dts/freescale/fsl-ls1028a-rdb.dts | 88 ++++++++++---------
1 file changed, 46 insertions(+), 42 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index 41900d351a92..7d87c90652d2 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -102,6 +102,52 @@ can-transceiver {
};
};
+&duart0 {
+ status = "okay";
+};
+
+&duart1 {
+ status = "okay";
+};
+
+&enetc_mdio_pf3 {
+ /* VSC8514 QSGMII quad PHY */
+ qsgmii_phy0: ethernet-phy@10 {
+ reg = <0x10>;
+ };
+
+ qsgmii_phy1: ethernet-phy@11 {
+ reg = <0x11>;
+ };
+
+ qsgmii_phy2: ethernet-phy@12 {
+ reg = <0x12>;
+ };
+
+ qsgmii_phy3: ethernet-phy@13 {
+ reg = <0x13>;
+ };
+};
+
+&enetc_port0 {
+ phy-handle = <&sgmii_phy0>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ sgmii_phy0: ethernet-phy@2 {
+ reg = <0x2>;
+ };
+ };
+};
+
+&enetc_port2 {
+ status = "okay";
+};
+
&esdhc {
sd-uhs-sdr104;
sd-uhs-sdr50;
@@ -192,48 +238,6 @@ rtc@51 {
};
};
-&duart0 {
- status = "okay";
-};
-
-&duart1 {
- status = "okay";
-};
-
-&enetc_mdio_pf3 {
- sgmii_phy0: ethernet-phy@2 {
- reg = <0x2>;
- };
-
- /* VSC8514 QSGMII quad PHY */
- qsgmii_phy0: ethernet-phy@10 {
- reg = <0x10>;
- };
-
- qsgmii_phy1: ethernet-phy@11 {
- reg = <0x11>;
- };
-
- qsgmii_phy2: ethernet-phy@12 {
- reg = <0x12>;
- };
-
- qsgmii_phy3: ethernet-phy@13 {
- reg = <0x13>;
- };
-};
-
-&enetc_port0 {
- phy-handle = <&sgmii_phy0>;
- phy-mode = "sgmii";
- managed = "in-band-status";
- status = "okay";
-};
-
-&enetc_port2 {
- status = "okay";
-};
-
&mscc_felix {
status = "okay";
};
--
2.25.1
From: Xiaowei Bao <[email protected]>
Add PCIe EP nodes for ls1028a to support EP mode.
Signed-off-by: Xiaowei Bao <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
.../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 24 +++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index fd3f3e8bb6ce..9efcaf68578c 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -637,6 +637,18 @@ pcie1: pcie@3400000 {
status = "disabled";
};
+ pcie_ep1: pcie_ep@3400000 {
+ compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep";
+ reg = <0x00 0x03400000 0x0 0x00100000
+ 0x80 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
+ interrupt-names = "pme";
+ num-ib-windows = <6>;
+ num-ob-windows = <8>;
+ status = "disabled";
+ };
+
pcie2: pcie@3500000 {
compatible = "fsl,ls1028a-pcie";
reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
@@ -664,6 +676,18 @@ pcie2: pcie@3500000 {
status = "disabled";
};
+ pcie_ep2: pcie_ep@3500000 {
+ compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep";
+ reg = <0x00 0x03500000 0x0 0x00100000
+ 0x88 0x00000000 0x8 0x00000000>;
+ reg-names = "regs", "addr_space";
+ interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
+ interrupt-names = "pme";
+ num-ib-windows = <6>;
+ num-ob-windows = <8>;
+ status = "disabled";
+ };
+
smmu: iommu@5000000 {
compatible = "arm,mmu-500";
reg = <0 0x5000000 0 0x800000>;
--
2.25.1
From: Biwen Li <[email protected]>
Add pwm nodes using flextimer controller.
Signed-off-by: Biwen Li <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
.../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 95 +++++++++++++++++++
1 file changed, 95 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index ef9d17df2afa..5c17dfaa50de 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -66,6 +66,13 @@ CPU_PW20: cpu-pw20 {
};
};
+ rtc_clk: rtc-clk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "rtc_clk";
+ };
+
sysclk: sysclk {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -1186,6 +1193,94 @@ ierb@1f0800000 {
reg = <0x01 0xf0800000 0x0 0x10000>;
};
+ pwm0: pwm@2800000 {
+ compatible = "fsl,vf610-ftm-pwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x2800000 0x0 0x10000>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ clocks = <&clockgen 4 1>, <&clockgen 4 1>,
+ <&rtc_clk>, <&clockgen 4 1>;
+ status = "disabled";
+ };
+
+ pwm1: pwm@2810000 {
+ compatible = "fsl,vf610-ftm-pwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x2810000 0x0 0x10000>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ clocks = <&clockgen 4 1>, <&clockgen 4 1>,
+ <&rtc_clk>, <&clockgen 4 1>;
+ status = "disabled";
+ };
+
+ pwm2: pwm@2820000 {
+ compatible = "fsl,vf610-ftm-pwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x2820000 0x0 0x10000>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ clocks = <&clockgen 4 1>, <&clockgen 4 1>,
+ <&rtc_clk>, <&clockgen 4 1>;
+ status = "disabled";
+ };
+
+ pwm3: pwm@2830000 {
+ compatible = "fsl,vf610-ftm-pwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x2830000 0x0 0x10000>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ clocks = <&clockgen 4 1>, <&clockgen 4 1>,
+ <&rtc_clk>, <&clockgen 4 1>;
+ status = "disabled";
+ };
+
+ pwm4: pwm@2840000 {
+ compatible = "fsl,vf610-ftm-pwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x2840000 0x0 0x10000>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ clocks = <&clockgen 4 1>, <&clockgen 4 1>,
+ <&rtc_clk>, <&clockgen 4 1>;
+ status = "disabled";
+ };
+
+ pwm5: pwm@2850000 {
+ compatible = "fsl,vf610-ftm-pwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x2850000 0x0 0x10000>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ clocks = <&clockgen 4 1>, <&clockgen 4 1>,
+ <&rtc_clk>, <&clockgen 4 1>;
+ status = "disabled";
+ };
+
+ pwm6: pwm@2860000 {
+ compatible = "fsl,vf610-ftm-pwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x2860000 0x0 0x10000>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ clocks = <&clockgen 4 1>, <&clockgen 4 1>,
+ <&rtc_clk>, <&clockgen 4 1>;
+ status = "disabled";
+ };
+
+ pwm7: pwm@2870000 {
+ compatible = "fsl,vf610-ftm-pwm";
+ #pwm-cells = <3>;
+ reg = <0x0 0x2870000 0x0 0x10000>;
+ clock-names = "ftm_sys", "ftm_ext",
+ "ftm_fix", "ftm_cnt_clk_en";
+ clocks = <&clockgen 4 1>, <&clockgen 4 1>,
+ <&rtc_clk>, <&clockgen 4 1>;
+ status = "disabled";
+ };
+
rcpm: power-controller@1e34040 {
compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+";
reg = <0x0 0x1e34040 0x0 0x1c>;
--
2.25.1
From: Biwen Li <[email protected]>
The i2c rtc is on i2c2 bus not i2c1 bus, so fix it in dts.
Signed-off-by: Biwen Li <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 14 +++++++++-----
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index 00d5b81bdef3..baa1cc9b9835 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -276,11 +276,6 @@ temperature-sensor@4c {
vcc-supply = <&sb_3v3>;
};
- rtc@51 {
- compatible = "nxp,pcf2129";
- reg = <0x51>;
- };
-
eeprom@56 {
compatible = "atmel,24c512";
reg = <0x56>;
@@ -322,6 +317,15 @@ mux: mux-controller {
};
+&i2c1 {
+ status = "okay";
+
+ rtc@51 {
+ compatible = "nxp,pcf2129";
+ reg = <0x51>;
+ };
+};
+
&enetc_port1 {
phy-handle = <&qds_phy1>;
phy-mode = "rgmii-id";
--
2.25.1
From: Biwen Li <[email protected]>
Enable pwm0 on ls1028a-rdb board which uses flextimer1.
Signed-off-by: Biwen Li <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
index 7d87c90652d2..dd75624d3e91 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
@@ -283,6 +283,10 @@ &optee {
status = "okay";
};
+&pwm0 {
+ status = "okay";
+};
+
&sai4 {
status = "okay";
};
--
2.25.1
From: Vabhav Sharma <[email protected]>
LPUART nodes by default are disabled in LS1028A device
tree, Enabling LPUART1 node.
Signed-off-by: Vabhav Sharma <[email protected]>
Acked-by: Fugang Duan <[email protected]>
Signed-off-by: Vladimir Oltean <[email protected]>
---
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index baa1cc9b9835..782853a449cc 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -336,6 +336,10 @@ &lpuart0 {
status = "okay";
};
+&lpuart1 {
+ status = "okay";
+};
+
&sai1 {
status = "okay";
};
--
2.25.1
From: Alex Marginean <[email protected]>
Add overlays for various serdes protocols on LS1028A QDS board using
different PHY cards. These should be applied at boot, based on serdes
configuration. If no overlay is applied, only the RGMII interface on
the QDS is available in Linux.
Building device tree fragments requires passing the "-@" argument to
dtc, which increases the base dtb size and might cause some platforms to
fail to store the new binary. To avoid that, it would be nice to only
pass "-@" for the platforms where fragments will be used, aka
LS1028A-QDS. One approach suggested by Rob Herring is used here:
https://lore.kernel.org/patchwork/patch/821645/
Also moved the enet* override nodes in dts file to be in alphabetic order.
Signed-off-by: Alex Marginean <[email protected]>
Signed-off-by: Ioana Ciornei <[email protected]>
Signed-off-by: Dong Aisheng <[email protected]>
Signed-off-by: Jason Liu <[email protected]>
Signed-off-by: Vladimir Oltean <[email protected]>
Signed-off-by: Li Yang <[email protected]>
---
arch/arm64/boot/dts/freescale/Makefile | 16 +++
.../dts/freescale/fsl-ls1028a-qds-13bb.dts | 113 ++++++++++++++++++
.../dts/freescale/fsl-ls1028a-qds-65bb.dts | 108 +++++++++++++++++
.../dts/freescale/fsl-ls1028a-qds-7777.dts | 82 +++++++++++++
.../dts/freescale/fsl-ls1028a-qds-85bb.dts | 107 +++++++++++++++++
.../dts/freescale/fsl-ls1028a-qds-899b.dts | 75 ++++++++++++
.../dts/freescale/fsl-ls1028a-qds-9999.dts | 79 ++++++++++++
.../boot/dts/freescale/fsl-ls1028a-qds.dts | 19 ++-
.../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +-
9 files changed, 595 insertions(+), 6 deletions(-)
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts
create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index a14a6173b765..f518eb1e1142 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -1,4 +1,14 @@
# SPDX-License-Identifier: GPL-2.0
+
+# required for overlay support
+DTC_FLAGS_fsl-ls1028a-qds := -@
+DTC_FLAGS_fsl-ls1028a-qds-13bb := -@
+DTC_FLAGS_fsl-ls1028a-qds-65bb := -@
+DTC_FLAGS_fsl-ls1028a-qds-7777 := -@
+DTC_FLAGS_fsl-ls1028a-qds-85bb := -@
+DTC_FLAGS_fsl-ls1028a-qds-899b := -@
+DTC_FLAGS_fsl-ls1028a-qds-9999 := -@
+
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb
@@ -11,6 +21,12 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var2.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3-ads2.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-13bb.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-65bb.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-7777.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-85bb.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb
+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts
new file mode 100644
index 000000000000..f748a2c12a70
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree fragment for LS1028A QDS board, serdes 13bb
+ *
+ * Copyright 2019-2021 NXP
+ *
+ * Requires a LS1028A QDS board with lane B rework.
+ * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C.
+ * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2.
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ fragment@0 {
+ target = <&mdio_slot1>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ slot1_sgmii: ethernet-phy@2 {
+ /* AQR112 */
+ reg = <0x2>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&enetc_port0>;
+
+ __overlay__ {
+ phy-handle = <&slot1_sgmii>;
+ phy-mode = "usxgmii";
+ managed = "in-band-status";
+ status = "okay";
+ };
+ };
+
+ fragment@2 {
+ target = <&mdio_slot2>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 4 ports on AQR412 */
+ slot2_qxgmii0: ethernet-phy@0 {
+ reg = <0x0>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+
+ slot2_qxgmii1: ethernet-phy@1 {
+ reg = <0x1>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+
+ slot2_qxgmii2: ethernet-phy@2 {
+ reg = <0x2>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+
+ slot2_qxgmii3: ethernet-phy@3 {
+ reg = <0x3>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+ };
+ };
+
+ fragment@3 {
+ target = <&mscc_felix_ports>;
+
+ __overlay__ {
+ port@0 {
+ status = "okay";
+ phy-handle = <&slot2_qxgmii0>;
+ phy-mode = "usxgmii";
+ managed = "in-band-status";
+ };
+
+ port@1 {
+ status = "okay";
+ phy-handle = <&slot2_qxgmii1>;
+ phy-mode = "usxgmii";
+ managed = "in-band-status";
+ };
+
+ port@2 {
+ status = "okay";
+ phy-handle = <&slot2_qxgmii2>;
+ phy-mode = "usxgmii";
+ managed = "in-band-status";
+ };
+
+ port@3 {
+ status = "okay";
+ phy-handle = <&slot2_qxgmii3>;
+ phy-mode = "usxgmii";
+ managed = "in-band-status";
+ };
+ };
+ };
+
+ fragment@4 {
+ target = <&mscc_felix>;
+
+ __overlay__ {
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts
new file mode 100644
index 000000000000..8ffb707a1576
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree fragment for LS1028A QDS board, serdes 69xx
+ *
+ * Copyright 2019-2021 NXP
+ *
+ * Requires a LS1028A QDS board with lane B rework.
+ * Requires a SCH-30842 card in slot 1 and a SCH-28021 card in slot 2.
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ fragment@0 {
+ target = <&mdio_slot1>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ slot1_sgmii: ethernet-phy@2 {
+ /* AQR112 */
+ reg = <0x2>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&enetc_port0>;
+
+ __overlay__ {
+ phy-handle = <&slot1_sgmii>;
+ phy-mode = "2500base-x";
+ managed = "in-band-status";
+ status = "okay";
+ };
+ };
+
+ fragment@2 {
+ target = <&mdio_slot2>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 4 ports on VSC8514 */
+ slot2_qsgmii0: ethernet-phy@8 {
+ reg = <0x8>;
+ };
+
+ slot2_qsgmii1: ethernet-phy@9 {
+ reg = <0x9>;
+ };
+
+ slot2_qsgmii2: ethernet-phy@a {
+ reg = <0xa>;
+ };
+
+ slot2_qsgmii3: ethernet-phy@b {
+ reg = <0xb>;
+ };
+ };
+ };
+
+ fragment@3 {
+ target = <&mscc_felix_ports>;
+
+ __overlay__ {
+ port@0 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii0>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+
+ port@1 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii1>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+
+ port@2 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii2>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+
+ port@3 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii3>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+ };
+ };
+
+ fragment@4 {
+ target = <&mscc_felix>;
+
+ __overlay__ {
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts
new file mode 100644
index 000000000000..eb6a1e674f10
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree fragment for LS1028A QDS board, serdes 7777
+ *
+ * Copyright 2019-2021 NXP
+ *
+ * Requires a LS1028A QDS board without lane B rework.
+ * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing
+ * disabled, plugged in slot 1.
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ fragment@0 {
+ target = <&mdio_slot1>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 4 ports on AQR412 */
+ slot1_sxgmii0: ethernet-phy@0 {
+ reg = <0x0>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+
+ slot1_sxgmii1: ethernet-phy@1 {
+ reg = <0x1>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+
+ slot1_sxgmii2: ethernet-phy@2 {
+ reg = <0x2>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+
+ slot1_sxgmii3: ethernet-phy@3 {
+ reg = <0x3>;
+ compatible = "ethernet-phy-ieee802.3-c45";
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&mscc_felix_ports>;
+
+ __overlay__ {
+ port@0 {
+ status = "okay";
+ phy-handle = <&slot1_sxgmii0>;
+ phy-mode = "2500base-x";
+ };
+
+ port@1 {
+ status = "okay";
+ phy-handle = <&slot1_sxgmii1>;
+ phy-mode = "2500base-x";
+ };
+
+ port@2 {
+ status = "okay";
+ phy-handle = <&slot1_sxgmii2>;
+ phy-mode = "2500base-x";
+ };
+
+ port@3 {
+ status = "okay";
+ phy-handle = <&slot1_sxgmii3>;
+ phy-mode = "2500base-x";
+ };
+ };
+ };
+
+ fragment@2 {
+ target = <&mscc_felix>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts
new file mode 100644
index 000000000000..8e90c3088ba1
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts
@@ -0,0 +1,107 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree fragment for LS1028A QDS board, serdes 85bb
+ *
+ * Copyright 2019-2021 NXP
+ *
+ * Requires a LS1028A QDS board with lane B rework.
+ * Requires a SCH-24801 card in slot 1 and a SCH-28021 card in slot 2.
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ fragment@0 {
+ target = <&mdio_slot1>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ slot1_sgmii: ethernet-phy@1c {
+ /* 1st port on VSC8234 */
+ reg = <0x1c>;
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&enetc_port0>;
+
+ __overlay__ {
+ phy-handle = <&slot1_sgmii>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ status = "okay";
+ };
+ };
+
+ fragment@2 {
+ target = <&mdio_slot2>;
+
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* 4 ports on VSC8514 */
+ slot2_qsgmii0: ethernet-phy@8 {
+ reg = <0x8>;
+ };
+
+ slot2_qsgmii1: ethernet-phy@9 {
+ reg = <0x9>;
+ };
+
+ slot2_qsgmii2: ethernet-phy@a {
+ reg = <0xa>;
+ };
+
+ slot2_qsgmii3: ethernet-phy@b {
+ reg = <0xb>;
+ };
+ };
+ };
+
+ fragment@3 {
+ target = <&mscc_felix_ports>;
+
+ __overlay__ {
+ port@0 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii0>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+
+ port@1 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii1>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+
+ port@2 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii2>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+
+ port@3 {
+ status = "okay";
+ phy-handle = <&slot2_qsgmii3>;
+ phy-mode = "qsgmii";
+ managed = "in-band-status";
+ };
+ };
+ };
+
+ fragment@4 {
+ target = <&mscc_felix>;
+
+ __overlay__ {
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts
new file mode 100644
index 000000000000..5d0a094e6c44
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree fragment for LS1028A QDS board, serdes 85xx
+ *
+ * Copyright 2019-2021 NXP
+ *
+ * Requires a LS1028A QDS board without lane B rework.
+ * Requires a SCH-24801 card in slot 1.
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ fragment@0 {
+ target = <&mdio_slot1>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* VSC8234 */
+ slot1_sgmii0: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+
+ slot1_sgmii1: ethernet-phy@1d {
+ reg = <0x1d>;
+ };
+
+ slot1_sgmii2: ethernet-phy@1e {
+ reg = <0x1e>;
+ };
+
+ slot1_sgmii3: ethernet-phy@1f {
+ reg = <0x1f>;
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&enetc_port0>;
+ __overlay__ {
+ phy-handle = <&slot1_sgmii0>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ status = "okay";
+ };
+ };
+
+ fragment@2 {
+ target = <&mscc_felix_ports>;
+ __overlay__ {
+ port@1 {
+ status = "okay";
+ phy-handle = <&slot1_sgmii1>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ };
+
+ port@2 {
+ status = "okay";
+ phy-handle = <&slot1_sgmii2>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ };
+ };
+ };
+
+ fragment@3 {
+ target = <&mscc_felix>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts
new file mode 100644
index 000000000000..1ef743c48e84
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Device Tree fragment for LS1028A QDS board, serdes 85xx
+ *
+ * Copyright 2019-2021 NXP
+ *
+ * Requires a LS1028A QDS board without lane B rework.
+ * Requires a SCH-24801 card in slot 1.
+ */
+
+/dts-v1/;
+/plugin/;
+
+/ {
+ fragment@0 {
+ target = <&mdio_slot1>;
+ __overlay__ {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ /* VSC8234 */
+ slot1_sgmii0: ethernet-phy@1c {
+ reg = <0x1c>;
+ };
+
+ slot1_sgmii1: ethernet-phy@1d {
+ reg = <0x1d>;
+ };
+
+ slot1_sgmii2: ethernet-phy@1e {
+ reg = <0x1e>;
+ };
+
+ slot1_sgmii3: ethernet-phy@1f {
+ reg = <0x1f>;
+ };
+ };
+ };
+
+ fragment@1 {
+ target = <&mscc_felix_ports>;
+ __overlay__ {
+ port@0 {
+ status = "okay";
+ phy-handle = <&slot1_sgmii0>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ };
+
+ port@1 {
+ status = "okay";
+ phy-handle = <&slot1_sgmii1>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ };
+
+ port@2 {
+ status = "okay";
+ phy-handle = <&slot1_sgmii2>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ };
+
+ port@3 {
+ status = "okay";
+ phy-handle = <&slot1_sgmii3>;
+ phy-mode = "sgmii";
+ managed = "in-band-status";
+ };
+ };
+ };
+
+ fragment@2 {
+ target = <&mscc_felix>;
+ __overlay__ {
+ status = "okay";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
index 782853a449cc..177bc1405f0f 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
@@ -211,6 +211,16 @@ &duart1 {
status = "okay";
};
+&enetc_port1 {
+ phy-handle = <&qds_phy1>;
+ phy-mode = "rgmii-id";
+ status = "okay";
+};
+
+&enetc_port2 {
+ status = "okay";
+};
+
&esdhc {
status = "okay";
};
@@ -326,17 +336,16 @@ rtc@51 {
};
};
-&enetc_port1 {
- phy-handle = <&qds_phy1>;
- phy-mode = "rgmii-id";
+&lpuart0 {
status = "okay";
};
-&lpuart0 {
+&lpuart1 {
status = "okay";
};
-&lpuart1 {
+&mscc_felix_port4 {
+ ethernet = <&enetc_port2>;
status = "okay";
};
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 5c17dfaa50de..f305ac2906d8 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -1115,7 +1115,7 @@ mscc_felix: ethernet-switch@0,5 {
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
- ports {
+ mscc_felix_ports: ports {
#address-cells = <1>;
#size-cells = <0>;
--
2.25.1
On Fri, Dec 03, 2021 at 06:17:17PM -0600, Li Yang wrote:
> From: Vabhav Sharma <[email protected]>
>
> LPUART nodes by default are disabled in LS1028A device
> tree, Enabling LPUART1 node.
>
> Signed-off-by: Vabhav Sharma <[email protected]>
> Acked-by: Fugang Duan <[email protected]>
> Signed-off-by: Vladimir Oltean <[email protected]>
This needs your Signed-off-by tag too, since you're carrying the patch.
> ---
> arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> index baa1cc9b9835..782853a449cc 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> @@ -336,6 +336,10 @@ &lpuart0 {
> status = "okay";
> };
>
> +&lpuart1 {
> + status = "okay";
> +};
> +
> &sai1 {
> status = "okay";
> };
> --
> 2.25.1
>
On Fri, Dec 03, 2021 at 06:17:11PM -0600, Li Yang wrote:
> From: Xiaowei Bao <[email protected]>
>
> Add PCIe EP nodes for ls1028a to support EP mode.
>
> Signed-off-by: Xiaowei Bao <[email protected]>
> Signed-off-by: Li Yang <[email protected]>
> ---
> .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 24 +++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> index fd3f3e8bb6ce..9efcaf68578c 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> @@ -637,6 +637,18 @@ pcie1: pcie@3400000 {
> status = "disabled";
> };
>
> + pcie_ep1: pcie_ep@3400000 {
pcie-ep
Shawn
> + compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep";
> + reg = <0x00 0x03400000 0x0 0x00100000
> + 0x80 0x00000000 0x8 0x00000000>;
> + reg-names = "regs", "addr_space";
> + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
> + interrupt-names = "pme";
> + num-ib-windows = <6>;
> + num-ob-windows = <8>;
> + status = "disabled";
> + };
> +
> pcie2: pcie@3500000 {
> compatible = "fsl,ls1028a-pcie";
> reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */
> @@ -664,6 +676,18 @@ pcie2: pcie@3500000 {
> status = "disabled";
> };
>
> + pcie_ep2: pcie_ep@3500000 {
> + compatible = "fsl,ls1028a-pcie-ep","fsl,ls-pcie-ep";
> + reg = <0x00 0x03500000 0x0 0x00100000
> + 0x88 0x00000000 0x8 0x00000000>;
> + reg-names = "regs", "addr_space";
> + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; /* PME interrupt */
> + interrupt-names = "pme";
> + num-ib-windows = <6>;
> + num-ob-windows = <8>;
> + status = "disabled";
> + };
> +
> smmu: iommu@5000000 {
> compatible = "arm,mmu-500";
> reg = <0 0x5000000 0 0x800000>;
> --
> 2.25.1
>
On Fri, Dec 03, 2021 at 06:17:12PM -0600, Li Yang wrote:
> From: Biwen Li <[email protected]>
>
> Add flextimer2 based ftm_alarm1 node and enable it to be the default rtc
> wakeup source for rdb and qds boards instead of the original flextimer1
> based ftm_alarm0. The ftm_alarm0 node hence is disabled by default.
What's wrong with using ftm_alarm0?
Shawn
>
> Signed-off-by: Biwen Li <[email protected]>
> Signed-off-by: Li Yang <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 6 +++++-
> arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 6 +++++-
> arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 9 +++++++++
> 3 files changed, 19 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> index 6e2a1da662fb..00d5b81bdef3 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> @@ -25,7 +25,7 @@ aliases {
> serial1 = &duart1;
> mmc0 = &esdhc;
> mmc1 = &esdhc1;
> - rtc1 = &ftm_alarm0;
> + rtc1 = &ftm_alarm1;
> };
>
> chosen {
> @@ -234,6 +234,10 @@ mt35xu02g0: flash@0 {
> };
> };
>
> +&ftm_alarm1 {
> + status = "okay";
> +};
> +
> &i2c0 {
> status = "okay";
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> index 7719f44bcaed..41900d351a92 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> @@ -21,7 +21,7 @@ aliases {
> serial1 = &duart1;
> mmc0 = &esdhc;
> mmc1 = &esdhc1;
> - rtc1 = &ftm_alarm0;
> + rtc1 = &ftm_alarm1;
> };
>
> chosen {
> @@ -132,6 +132,10 @@ mt35xu02g0: flash@0 {
> };
> };
>
> +&ftm_alarm1 {
> + status = "okay";
> +};
> +
> &i2c0 {
> status = "okay";
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> index 9efcaf68578c..ef9d17df2afa 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> @@ -1198,6 +1198,15 @@ ftm_alarm0: timer@2800000 {
> reg = <0x0 0x2800000 0x0 0x10000>;
> fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
> interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> + ftm_alarm1: timer@2810000 {
> + compatible = "fsl,ls1028a-ftm-alarm";
> + reg = <0x0 0x2810000 0x0 0x10000>;
> + fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>;
> + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> };
> };
>
> --
> 2.25.1
>
On Fri, Dec 03, 2021 at 06:17:16PM -0600, Li Yang wrote:
> From: Biwen Li <[email protected]>
>
> The i2c rtc is on i2c2 bus not i2c1 bus, so fix it in dts.
>
> Signed-off-by: Biwen Li <[email protected]>
> Signed-off-by: Li Yang <[email protected]>
Do we need a Fixes tag?
Shawn
> ---
> arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 14 +++++++++-----
> 1 file changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> index 00d5b81bdef3..baa1cc9b9835 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> @@ -276,11 +276,6 @@ temperature-sensor@4c {
> vcc-supply = <&sb_3v3>;
> };
>
> - rtc@51 {
> - compatible = "nxp,pcf2129";
> - reg = <0x51>;
> - };
> -
> eeprom@56 {
> compatible = "atmel,24c512";
> reg = <0x56>;
> @@ -322,6 +317,15 @@ mux: mux-controller {
>
> };
>
> +&i2c1 {
> + status = "okay";
> +
> + rtc@51 {
> + compatible = "nxp,pcf2129";
> + reg = <0x51>;
> + };
> +};
> +
> &enetc_port1 {
> phy-handle = <&qds_phy1>;
> phy-mode = "rgmii-id";
> --
> 2.25.1
>
> -----Original Message-----
> From: Shawn Guo <[email protected]>
> Sent: Tuesday, December 14, 2021 1:46 PM
> To: Leo Li <[email protected]>
> Cc: [email protected]; [email protected];
> Biwen Li <[email protected]>
> Subject: Re: [PATCH v2 2/8] arm64: dts: ls1028a: add ftm_alarm1 node to be
> used as wakeup source
>
> On Fri, Dec 03, 2021 at 06:17:12PM -0600, Li Yang wrote:
> > From: Biwen Li <[email protected]>
> >
> > Add flextimer2 based ftm_alarm1 node and enable it to be the default
> > rtc wakeup source for rdb and qds boards instead of the original
> > flextimer1 based ftm_alarm0. The ftm_alarm0 node hence is disabled by
> default.
>
> What's wrong with using ftm_alarm0?
Not 100% sure, but probably because we need to use flextimer1 as PWM.
Biwen, Can you comment?
>
> Shawn
>
> >
> > Signed-off-by: Biwen Li <[email protected]>
> > Signed-off-by: Li Yang <[email protected]>
> > ---
> > arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 6 +++++-
> > arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 6 +++++-
> > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 9 +++++++++
> > 3 files changed, 19 insertions(+), 2 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > index 6e2a1da662fb..00d5b81bdef3 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > @@ -25,7 +25,7 @@ aliases {
> > serial1 = &duart1;
> > mmc0 = &esdhc;
> > mmc1 = &esdhc1;
> > - rtc1 = &ftm_alarm0;
> > + rtc1 = &ftm_alarm1;
> > };
> >
> > chosen {
> > @@ -234,6 +234,10 @@ mt35xu02g0: flash@0 {
> > };
> > };
> >
> > +&ftm_alarm1 {
> > + status = "okay";
> > +};
> > +
> > &i2c0 {
> > status = "okay";
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> > index 7719f44bcaed..41900d351a92 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> > @@ -21,7 +21,7 @@ aliases {
> > serial1 = &duart1;
> > mmc0 = &esdhc;
> > mmc1 = &esdhc1;
> > - rtc1 = &ftm_alarm0;
> > + rtc1 = &ftm_alarm1;
> > };
> >
> > chosen {
> > @@ -132,6 +132,10 @@ mt35xu02g0: flash@0 {
> > };
> > };
> >
> > +&ftm_alarm1 {
> > + status = "okay";
> > +};
> > +
> > &i2c0 {
> > status = "okay";
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > index 9efcaf68578c..ef9d17df2afa 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > @@ -1198,6 +1198,15 @@ ftm_alarm0: timer@2800000 {
> > reg = <0x0 0x2800000 0x0 0x10000>;
> > fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000
> 0x0 0x0>;
> > interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > + };
> > +
> > + ftm_alarm1: timer@2810000 {
> > + compatible = "fsl,ls1028a-ftm-alarm";
> > + reg = <0x0 0x2810000 0x0 0x10000>;
> > + fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000
> 0x0 0x0>;
> > + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> > + status = "disabled";
> > };
> > };
> >
> > --
> > 2.25.1
> >
> -----Original Message-----
> From: Leo Li <[email protected]>
> Sent: 2021??12??14?? 14:17
> To: Shawn Guo <[email protected]>
> Cc: [email protected]; [email protected]; Biwen
> Li <[email protected]>
> Subject: RE: [PATCH v2 2/8] arm64: dts: ls1028a: add ftm_alarm1 node to be
> used as wakeup source
>
>
>
> > -----Original Message-----
> > From: Shawn Guo <[email protected]>
> > Sent: Tuesday, December 14, 2021 1:46 PM
> > To: Leo Li <[email protected]>
> > Cc: [email protected];
> > [email protected]; Biwen Li <[email protected]>
> > Subject: Re: [PATCH v2 2/8] arm64: dts: ls1028a: add ftm_alarm1 node
> > to be used as wakeup source
> >
> > On Fri, Dec 03, 2021 at 06:17:12PM -0600, Li Yang wrote:
> > > From: Biwen Li <[email protected]>
> > >
> > > Add flextimer2 based ftm_alarm1 node and enable it to be the default
> > > rtc wakeup source for rdb and qds boards instead of the original
> > > flextimer1 based ftm_alarm0. The ftm_alarm0 node hence is disabled
> > > by
> > default.
> >
> > What's wrong with using ftm_alarm0?
>
> Not 100% sure, but probably because we need to use flextimer1 as PWM.
>>> Yes, flextime1 is used as PWM. So use flextimer2 as rtc.
>
> Biwen, Can you comment?
>
> >
> > Shawn
> >
> > >
> > > Signed-off-by: Biwen Li <[email protected]>
> > > Signed-off-by: Li Yang <[email protected]>
> > > ---
> > > arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 6 +++++-
> > > arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts | 6 +++++-
> > > arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 9 +++++++++
> > > 3 files changed, 19 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > > b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > > index 6e2a1da662fb..00d5b81bdef3 100644
> > > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> > > @@ -25,7 +25,7 @@ aliases {
> > > serial1 = &duart1;
> > > mmc0 = &esdhc;
> > > mmc1 = &esdhc1;
> > > - rtc1 = &ftm_alarm0;
> > > + rtc1 = &ftm_alarm1;
> > > };
> > >
> > > chosen {
> > > @@ -234,6 +234,10 @@ mt35xu02g0: flash@0 {
> > > };
> > > };
> > >
> > > +&ftm_alarm1 {
> > > + status = "okay";
> > > +};
> > > +
> > > &i2c0 {
> > > status = "okay";
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> > > b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> > > index 7719f44bcaed..41900d351a92 100644
> > > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> > > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dts
> > > @@ -21,7 +21,7 @@ aliases {
> > > serial1 = &duart1;
> > > mmc0 = &esdhc;
> > > mmc1 = &esdhc1;
> > > - rtc1 = &ftm_alarm0;
> > > + rtc1 = &ftm_alarm1;
> > > };
> > >
> > > chosen {
> > > @@ -132,6 +132,10 @@ mt35xu02g0: flash@0 {
> > > };
> > > };
> > >
> > > +&ftm_alarm1 {
> > > + status = "okay";
> > > +};
> > > +
> > > &i2c0 {
> > > status = "okay";
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > > b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > > index 9efcaf68578c..ef9d17df2afa 100644
> > > --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> > > @@ -1198,6 +1198,15 @@ ftm_alarm0: timer@2800000 {
> > > reg = <0x0 0x2800000 0x0 0x10000>;
> > > fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000
> > 0x0 0x0>;
> > > interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
> > > + status = "disabled";
> > > + };
> > > +
> > > + ftm_alarm1: timer@2810000 {
> > > + compatible = "fsl,ls1028a-ftm-alarm";
> > > + reg = <0x0 0x2810000 0x0 0x10000>;
> > > + fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000
> > 0x0 0x0>;
> > > + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
> > > + status = "disabled";
> > > };
> > > };
> > >
> > > --
> > > 2.25.1
> > >
On Fri, Dec 03, 2021 at 06:17:18PM -0600, Li Yang wrote:
> From: Alex Marginean <[email protected]>
>
> Add overlays for various serdes protocols on LS1028A QDS board using
> different PHY cards. These should be applied at boot, based on serdes
> configuration. If no overlay is applied, only the RGMII interface on
> the QDS is available in Linux.
>
> Building device tree fragments requires passing the "-@" argument to
> dtc, which increases the base dtb size and might cause some platforms to
> fail to store the new binary. To avoid that, it would be nice to only
> pass "-@" for the platforms where fragments will be used, aka
> LS1028A-QDS. One approach suggested by Rob Herring is used here:
>
> https://lore.kernel.org/patchwork/patch/821645/
>
> Also moved the enet* override nodes in dts file to be in alphabetic order.
>
> Signed-off-by: Alex Marginean <[email protected]>
> Signed-off-by: Ioana Ciornei <[email protected]>
> Signed-off-by: Dong Aisheng <[email protected]>
> Signed-off-by: Jason Liu <[email protected]>
> Signed-off-by: Vladimir Oltean <[email protected]>
> Signed-off-by: Li Yang <[email protected]>
> ---
> arch/arm64/boot/dts/freescale/Makefile | 16 +++
> .../dts/freescale/fsl-ls1028a-qds-13bb.dts | 113 ++++++++++++++++++
> .../dts/freescale/fsl-ls1028a-qds-65bb.dts | 108 +++++++++++++++++
> .../dts/freescale/fsl-ls1028a-qds-7777.dts | 82 +++++++++++++
> .../dts/freescale/fsl-ls1028a-qds-85bb.dts | 107 +++++++++++++++++
> .../dts/freescale/fsl-ls1028a-qds-899b.dts | 75 ++++++++++++
> .../dts/freescale/fsl-ls1028a-qds-9999.dts | 79 ++++++++++++
> .../boot/dts/freescale/fsl-ls1028a-qds.dts | 19 ++-
> .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 2 +-
> 9 files changed, 595 insertions(+), 6 deletions(-)
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts
> create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts
>
> diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
> index a14a6173b765..f518eb1e1142 100644
> --- a/arch/arm64/boot/dts/freescale/Makefile
> +++ b/arch/arm64/boot/dts/freescale/Makefile
> @@ -1,4 +1,14 @@
> # SPDX-License-Identifier: GPL-2.0
> +
> +# required for overlay support
> +DTC_FLAGS_fsl-ls1028a-qds := -@
> +DTC_FLAGS_fsl-ls1028a-qds-13bb := -@
> +DTC_FLAGS_fsl-ls1028a-qds-65bb := -@
> +DTC_FLAGS_fsl-ls1028a-qds-7777 := -@
> +DTC_FLAGS_fsl-ls1028a-qds-85bb := -@
> +DTC_FLAGS_fsl-ls1028a-qds-899b := -@
> +DTC_FLAGS_fsl-ls1028a-qds-9999 := -@
> +
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-oxalis.dtb
> @@ -11,6 +21,12 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var2.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var3-ads2.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-kontron-sl28-var4.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-13bb.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-65bb.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-7777.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-85bb.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb
> +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb
> dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts
> new file mode 100644
> index 000000000000..f748a2c12a70
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-13bb.dts
> @@ -0,0 +1,113 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree fragment for LS1028A QDS board, serdes 13bb
> + *
> + * Copyright 2019-2021 NXP
> + *
> + * Requires a LS1028A QDS board with lane B rework.
> + * Requires a SCH-30841 card with lane A of connector rewired to PHY lane C.
> + * Set-up is a SCH-30842 card in slot 1 and SCH-30841 in slot 2.
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +/ {
> + fragment@0 {
> + target = <&mdio_slot1>;
> +
> + __overlay__ {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + slot1_sgmii: ethernet-phy@2 {
> + /* AQR112 */
> + reg = <0x2>;
> + compatible = "ethernet-phy-ieee802.3-c45";
> + };
> + };
> + };
> +
> + fragment@1 {
> + target = <&enetc_port0>;
> +
> + __overlay__ {
> + phy-handle = <&slot1_sgmii>;
> + phy-mode = "usxgmii";
> + managed = "in-band-status";
> + status = "okay";
> + };
> + };
> +
> + fragment@2 {
> + target = <&mdio_slot2>;
> +
> + __overlay__ {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* 4 ports on AQR412 */
> + slot2_qxgmii0: ethernet-phy@0 {
> + reg = <0x0>;
> + compatible = "ethernet-phy-ieee802.3-c45";
> + };
> +
> + slot2_qxgmii1: ethernet-phy@1 {
> + reg = <0x1>;
> + compatible = "ethernet-phy-ieee802.3-c45";
> + };
> +
> + slot2_qxgmii2: ethernet-phy@2 {
> + reg = <0x2>;
> + compatible = "ethernet-phy-ieee802.3-c45";
> + };
> +
> + slot2_qxgmii3: ethernet-phy@3 {
> + reg = <0x3>;
> + compatible = "ethernet-phy-ieee802.3-c45";
> + };
> + };
> + };
> +
> + fragment@3 {
> + target = <&mscc_felix_ports>;
> +
> + __overlay__ {
> + port@0 {
> + status = "okay";
> + phy-handle = <&slot2_qxgmii0>;
> + phy-mode = "usxgmii";
> + managed = "in-band-status";
> + };
> +
> + port@1 {
> + status = "okay";
> + phy-handle = <&slot2_qxgmii1>;
> + phy-mode = "usxgmii";
> + managed = "in-band-status";
> + };
> +
> + port@2 {
> + status = "okay";
> + phy-handle = <&slot2_qxgmii2>;
> + phy-mode = "usxgmii";
> + managed = "in-band-status";
> + };
> +
> + port@3 {
> + status = "okay";
> + phy-handle = <&slot2_qxgmii3>;
> + phy-mode = "usxgmii";
> + managed = "in-band-status";
> + };
> + };
> + };
> +
> + fragment@4 {
> + target = <&mscc_felix>;
> +
> + __overlay__ {
> + status = "okay";
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts
> new file mode 100644
> index 000000000000..8ffb707a1576
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-65bb.dts
> @@ -0,0 +1,108 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree fragment for LS1028A QDS board, serdes 69xx
> + *
> + * Copyright 2019-2021 NXP
> + *
> + * Requires a LS1028A QDS board with lane B rework.
> + * Requires a SCH-30842 card in slot 1 and a SCH-28021 card in slot 2.
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +/ {
> + fragment@0 {
> + target = <&mdio_slot1>;
> +
> + __overlay__ {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + slot1_sgmii: ethernet-phy@2 {
> + /* AQR112 */
> + reg = <0x2>;
> + compatible = "ethernet-phy-ieee802.3-c45";
> + };
> + };
> + };
> +
> + fragment@1 {
> + target = <&enetc_port0>;
> +
> + __overlay__ {
> + phy-handle = <&slot1_sgmii>;
> + phy-mode = "2500base-x";
> + managed = "in-band-status";
> + status = "okay";
> + };
> + };
> +
> + fragment@2 {
> + target = <&mdio_slot2>;
> +
> + __overlay__ {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* 4 ports on VSC8514 */
> + slot2_qsgmii0: ethernet-phy@8 {
> + reg = <0x8>;
> + };
> +
> + slot2_qsgmii1: ethernet-phy@9 {
> + reg = <0x9>;
> + };
> +
> + slot2_qsgmii2: ethernet-phy@a {
> + reg = <0xa>;
> + };
> +
> + slot2_qsgmii3: ethernet-phy@b {
> + reg = <0xb>;
> + };
> + };
> + };
> +
> + fragment@3 {
> + target = <&mscc_felix_ports>;
> +
> + __overlay__ {
> + port@0 {
> + status = "okay";
> + phy-handle = <&slot2_qsgmii0>;
> + phy-mode = "qsgmii";
> + managed = "in-band-status";
> + };
> +
> + port@1 {
> + status = "okay";
> + phy-handle = <&slot2_qsgmii1>;
> + phy-mode = "qsgmii";
> + managed = "in-band-status";
> + };
> +
> + port@2 {
> + status = "okay";
> + phy-handle = <&slot2_qsgmii2>;
> + phy-mode = "qsgmii";
> + managed = "in-band-status";
> + };
> +
> + port@3 {
> + status = "okay";
> + phy-handle = <&slot2_qsgmii3>;
> + phy-mode = "qsgmii";
> + managed = "in-band-status";
> + };
> + };
> + };
> +
> + fragment@4 {
> + target = <&mscc_felix>;
> +
> + __overlay__ {
> + status = "okay";
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts
> new file mode 100644
> index 000000000000..eb6a1e674f10
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-7777.dts
> @@ -0,0 +1,82 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree fragment for LS1028A QDS board, serdes 7777
> + *
> + * Copyright 2019-2021 NXP
> + *
> + * Requires a LS1028A QDS board without lane B rework.
> + * Requires a SCH-30841 card without lane A/C rewire and with a FW with muxing
> + * disabled, plugged in slot 1.
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +/ {
> + fragment@0 {
> + target = <&mdio_slot1>;
> +
> + __overlay__ {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* 4 ports on AQR412 */
> + slot1_sxgmii0: ethernet-phy@0 {
> + reg = <0x0>;
> + compatible = "ethernet-phy-ieee802.3-c45";
> + };
> +
> + slot1_sxgmii1: ethernet-phy@1 {
> + reg = <0x1>;
> + compatible = "ethernet-phy-ieee802.3-c45";
> + };
> +
> + slot1_sxgmii2: ethernet-phy@2 {
> + reg = <0x2>;
> + compatible = "ethernet-phy-ieee802.3-c45";
> + };
> +
> + slot1_sxgmii3: ethernet-phy@3 {
> + reg = <0x3>;
> + compatible = "ethernet-phy-ieee802.3-c45";
> + };
> + };
> + };
> +
> + fragment@1 {
> + target = <&mscc_felix_ports>;
> +
> + __overlay__ {
> + port@0 {
> + status = "okay";
> + phy-handle = <&slot1_sxgmii0>;
> + phy-mode = "2500base-x";
> + };
> +
> + port@1 {
> + status = "okay";
> + phy-handle = <&slot1_sxgmii1>;
> + phy-mode = "2500base-x";
> + };
> +
> + port@2 {
> + status = "okay";
> + phy-handle = <&slot1_sxgmii2>;
> + phy-mode = "2500base-x";
> + };
> +
> + port@3 {
> + status = "okay";
> + phy-handle = <&slot1_sxgmii3>;
> + phy-mode = "2500base-x";
> + };
> + };
> + };
> +
> + fragment@2 {
> + target = <&mscc_felix>;
> + __overlay__ {
> + status = "okay";
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts
> new file mode 100644
> index 000000000000..8e90c3088ba1
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-85bb.dts
> @@ -0,0 +1,107 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree fragment for LS1028A QDS board, serdes 85bb
> + *
> + * Copyright 2019-2021 NXP
> + *
> + * Requires a LS1028A QDS board with lane B rework.
> + * Requires a SCH-24801 card in slot 1 and a SCH-28021 card in slot 2.
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +/ {
> + fragment@0 {
> + target = <&mdio_slot1>;
> +
> + __overlay__ {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + slot1_sgmii: ethernet-phy@1c {
> + /* 1st port on VSC8234 */
> + reg = <0x1c>;
> + };
> + };
> + };
> +
> + fragment@1 {
> + target = <&enetc_port0>;
> +
> + __overlay__ {
> + phy-handle = <&slot1_sgmii>;
> + phy-mode = "sgmii";
> + managed = "in-band-status";
> + status = "okay";
> + };
> + };
> +
> + fragment@2 {
> + target = <&mdio_slot2>;
> +
> + __overlay__ {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* 4 ports on VSC8514 */
> + slot2_qsgmii0: ethernet-phy@8 {
> + reg = <0x8>;
> + };
> +
> + slot2_qsgmii1: ethernet-phy@9 {
> + reg = <0x9>;
> + };
> +
> + slot2_qsgmii2: ethernet-phy@a {
> + reg = <0xa>;
> + };
> +
> + slot2_qsgmii3: ethernet-phy@b {
> + reg = <0xb>;
> + };
> + };
> + };
> +
> + fragment@3 {
> + target = <&mscc_felix_ports>;
> +
> + __overlay__ {
> + port@0 {
> + status = "okay";
> + phy-handle = <&slot2_qsgmii0>;
> + phy-mode = "qsgmii";
> + managed = "in-band-status";
> + };
> +
> + port@1 {
> + status = "okay";
> + phy-handle = <&slot2_qsgmii1>;
> + phy-mode = "qsgmii";
> + managed = "in-band-status";
> + };
> +
> + port@2 {
> + status = "okay";
> + phy-handle = <&slot2_qsgmii2>;
> + phy-mode = "qsgmii";
> + managed = "in-band-status";
> + };
> +
> + port@3 {
> + status = "okay";
> + phy-handle = <&slot2_qsgmii3>;
> + phy-mode = "qsgmii";
> + managed = "in-band-status";
> + };
> + };
> + };
> +
> + fragment@4 {
> + target = <&mscc_felix>;
> +
> + __overlay__ {
> + status = "okay";
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts
> new file mode 100644
> index 000000000000..5d0a094e6c44
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-899b.dts
> @@ -0,0 +1,75 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree fragment for LS1028A QDS board, serdes 85xx
> + *
> + * Copyright 2019-2021 NXP
> + *
> + * Requires a LS1028A QDS board without lane B rework.
> + * Requires a SCH-24801 card in slot 1.
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +/ {
> + fragment@0 {
> + target = <&mdio_slot1>;
> + __overlay__ {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* VSC8234 */
> + slot1_sgmii0: ethernet-phy@1c {
> + reg = <0x1c>;
> + };
> +
> + slot1_sgmii1: ethernet-phy@1d {
> + reg = <0x1d>;
> + };
> +
> + slot1_sgmii2: ethernet-phy@1e {
> + reg = <0x1e>;
> + };
> +
> + slot1_sgmii3: ethernet-phy@1f {
> + reg = <0x1f>;
> + };
> + };
> + };
> +
> + fragment@1 {
> + target = <&enetc_port0>;
> + __overlay__ {
> + phy-handle = <&slot1_sgmii0>;
> + phy-mode = "sgmii";
> + managed = "in-band-status";
> + status = "okay";
> + };
> + };
> +
> + fragment@2 {
> + target = <&mscc_felix_ports>;
> + __overlay__ {
> + port@1 {
> + status = "okay";
> + phy-handle = <&slot1_sgmii1>;
> + phy-mode = "sgmii";
> + managed = "in-band-status";
> + };
> +
> + port@2 {
> + status = "okay";
> + phy-handle = <&slot1_sgmii2>;
> + phy-mode = "sgmii";
> + managed = "in-band-status";
> + };
> + };
> + };
> +
> + fragment@3 {
> + target = <&mscc_felix>;
> + __overlay__ {
> + status = "okay";
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts
> new file mode 100644
> index 000000000000..1ef743c48e84
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts
> @@ -0,0 +1,79 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Device Tree fragment for LS1028A QDS board, serdes 85xx
> + *
> + * Copyright 2019-2021 NXP
> + *
> + * Requires a LS1028A QDS board without lane B rework.
> + * Requires a SCH-24801 card in slot 1.
> + */
> +
> +/dts-v1/;
> +/plugin/;
> +
> +/ {
> + fragment@0 {
Is fragment0 more appropriate maybe, as @unit-address requires a
corresponding 'reg' property?
Shawn
> + target = <&mdio_slot1>;
> + __overlay__ {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + /* VSC8234 */
> + slot1_sgmii0: ethernet-phy@1c {
> + reg = <0x1c>;
> + };
> +
> + slot1_sgmii1: ethernet-phy@1d {
> + reg = <0x1d>;
> + };
> +
> + slot1_sgmii2: ethernet-phy@1e {
> + reg = <0x1e>;
> + };
> +
> + slot1_sgmii3: ethernet-phy@1f {
> + reg = <0x1f>;
> + };
> + };
> + };
> +
> + fragment@1 {
> + target = <&mscc_felix_ports>;
> + __overlay__ {
> + port@0 {
> + status = "okay";
> + phy-handle = <&slot1_sgmii0>;
> + phy-mode = "sgmii";
> + managed = "in-band-status";
> + };
> +
> + port@1 {
> + status = "okay";
> + phy-handle = <&slot1_sgmii1>;
> + phy-mode = "sgmii";
> + managed = "in-band-status";
> + };
> +
> + port@2 {
> + status = "okay";
> + phy-handle = <&slot1_sgmii2>;
> + phy-mode = "sgmii";
> + managed = "in-band-status";
> + };
> +
> + port@3 {
> + status = "okay";
> + phy-handle = <&slot1_sgmii3>;
> + phy-mode = "sgmii";
> + managed = "in-band-status";
> + };
> + };
> + };
> +
> + fragment@2 {
> + target = <&mscc_felix>;
> + __overlay__ {
> + status = "okay";
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> index 782853a449cc..177bc1405f0f 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts
> @@ -211,6 +211,16 @@ &duart1 {
> status = "okay";
> };
>
> +&enetc_port1 {
> + phy-handle = <&qds_phy1>;
> + phy-mode = "rgmii-id";
> + status = "okay";
> +};
> +
> +&enetc_port2 {
> + status = "okay";
> +};
> +
> &esdhc {
> status = "okay";
> };
> @@ -326,17 +336,16 @@ rtc@51 {
> };
> };
>
> -&enetc_port1 {
> - phy-handle = <&qds_phy1>;
> - phy-mode = "rgmii-id";
> +&lpuart0 {
> status = "okay";
> };
>
> -&lpuart0 {
> +&lpuart1 {
> status = "okay";
> };
>
> -&lpuart1 {
> +&mscc_felix_port4 {
> + ethernet = <&enetc_port2>;
> status = "okay";
> };
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> index 5c17dfaa50de..f305ac2906d8 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
> @@ -1115,7 +1115,7 @@ mscc_felix: ethernet-switch@0,5 {
> interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
> status = "disabled";
>
> - ports {
> + mscc_felix_ports: ports {
> #address-cells = <1>;
> #size-cells = <0>;
>
> --
> 2.25.1
>
> -----Original Message-----
> From: Shawn Guo <[email protected]>
> Sent: Tuesday, December 14, 2021 3:22 PM
> To: Leo Li <[email protected]>
> Cc: [email protected]; [email protected];
> Alexandru Marginean <[email protected]>; Ioana Ciornei
> <[email protected]>; Aisheng Dong <[email protected]>; Jason
> Liu <[email protected]>; Vladimir Oltean <[email protected]>
> Subject: Re: [PATCH v2 8/8] arm64: dts: ls1028a-qds: add overlays for various
> serdes protocols
>
> On Fri, Dec 03, 2021 at 06:17:18PM -0600, Li Yang wrote:
> > From: Alex Marginean <[email protected]>
> >
[snip]
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts
> > b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts
> > new file mode 100644
> > index 000000000000..1ef743c48e84
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a-qds-9999.dts
> > @@ -0,0 +1,79 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + * Device Tree fragment for LS1028A QDS board, serdes 85xx
> > + *
> > + * Copyright 2019-2021 NXP
> > + *
> > + * Requires a LS1028A QDS board without lane B rework.
> > + * Requires a SCH-24801 card in slot 1.
> > + */
> > +
> > +/dts-v1/;
> > +/plugin/;
> > +
> > +/ {
> > + fragment@0 {
>
> Is fragment0 more appropriate maybe, as @unit-address requires a
> corresponding 'reg' property?
Not sure if the overlay framework will use the index information somehow, but this is how it is demonstrated in the Documentation/devicetree/overlay-notes.rst document.
Regards,
Leo