Hi,
This series is a fix for RMII/MII operation mode of the dwmac-visconti driver.
It is composed of two parts:
* 1/2: fix constant definitions for cleared bits in ETHER_CLK_SEL register
* 2/2: fix configuration of ETHER_CLK_SEL register for running in RMII operation mode.
Best regards,
Yuji
Yuji Ishikawa (2):
net: stmmac: dwmac-visconti: Fix bit definitions for ETHER_CLK_SEL
net: stmmac: dwmac-visconti: Fix clock configuration for RMII mode
.../ethernet/stmicro/stmmac/dwmac-visconti.c | 42 ++++++++++++-------
1 file changed, 26 insertions(+), 16 deletions(-)
--
2.17.1
Bit pattern of the ETHER_CLOCK_SEL register for RMII/MII mode should be fixed.
Also, some control bits should be modified with a specific sequence.
Signed-off-by: Yuji Ishikawa <[email protected]>
Reviewed-by: Nobuhiro Iwamatsu <[email protected]>
---
.../ethernet/stmicro/stmmac/dwmac-visconti.c | 32 ++++++++++++-------
1 file changed, 21 insertions(+), 11 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
index 43a446cea..dde5b772a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-visconti.c
@@ -96,31 +96,41 @@ static void visconti_eth_fix_mac_speed(void *priv, unsigned int speed)
val |= ETHER_CLK_SEL_TX_O_E_N_IN;
writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
+ /* Set Clock-Mux, Start clock, Set TX_O direction */
switch (dwmac->phy_intf_sel) {
case ETHER_CONFIG_INTF_RGMII:
val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC;
+ writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
+
+ val |= ETHER_CLK_SEL_RX_TX_CLK_EN;
+ writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
+
+ val &= ~ETHER_CLK_SEL_TX_O_E_N_IN;
+ writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
break;
case ETHER_CONFIG_INTF_RMII:
val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_DIV |
- ETHER_CLK_SEL_TX_CLK_EXT_SEL_TXC | ETHER_CLK_SEL_TX_O_E_N_IN |
+ ETHER_CLK_SEL_TX_CLK_EXT_SEL_DIV | ETHER_CLK_SEL_TX_O_E_N_IN |
ETHER_CLK_SEL_RMII_CLK_SEL_RX_C;
+ writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
+
+ val |= ETHER_CLK_SEL_RMII_CLK_RST;
+ writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
+
+ val |= ETHER_CLK_SEL_RMII_CLK_EN | ETHER_CLK_SEL_RX_TX_CLK_EN;
+ writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
break;
case ETHER_CONFIG_INTF_MII:
default:
val = clk_sel_val | ETHER_CLK_SEL_RX_CLK_EXT_SEL_RXC |
- ETHER_CLK_SEL_TX_CLK_EXT_SEL_DIV | ETHER_CLK_SEL_TX_O_E_N_IN |
- ETHER_CLK_SEL_RMII_CLK_EN;
+ ETHER_CLK_SEL_TX_CLK_EXT_SEL_TXC | ETHER_CLK_SEL_TX_O_E_N_IN;
+ writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
+
+ val |= ETHER_CLK_SEL_RX_TX_CLK_EN;
+ writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
break;
}
- /* Start clock */
- writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
- val |= ETHER_CLK_SEL_RX_TX_CLK_EN;
- writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
-
- val &= ~ETHER_CLK_SEL_TX_O_E_N_IN;
- writel(val, dwmac->reg + REG_ETHER_CLOCK_SEL);
-
spin_unlock_irqrestore(&dwmac->lock, flags);
}
--
2.17.1
On Tue, 18 Jan 2022 14:39:48 +0900 Yuji Ishikawa wrote:
> This series is a fix for RMII/MII operation mode of the dwmac-visconti driver.
> It is composed of two parts:
>
> * 1/2: fix constant definitions for cleared bits in ETHER_CLK_SEL register
> * 2/2: fix configuration of ETHER_CLK_SEL register for running in RMII operation mode.
Please add appropriate Fixes tag pointing to the commits where the
buggy code was introduced, even if it's the initial commit adding
the driver.
Hi Jakub,
Thank you for your comment. I will add Fixed tags to commit messages.
-----Original Message-----
From: Jakub Kicinski <[email protected]>
Sent: Wednesday, January 19, 2022 9:50 AM
To: ishikawa yuji($B@P@n(B $BM*;J(B $B!{#R#D#C""#A#I#T#C!{#E#A3+(B) <[email protected]>
Cc: David S . Miller <[email protected]>; Giuseppe Cavallaro <[email protected]>; Alexandre Torgue <[email protected]>; Jose Abreu <[email protected]>; [email protected]; [email protected]; [email protected]; iwamatsu nobuhiro($B4d>>(B $B?.MN(B $B""#S#W#C"~#A#C#T(B) <[email protected]>
Subject: Re: [PATCH 0/2] net: stmmac: dwmac-visconti: Fix bit definitions and clock configuration for RMII mode
> On Tue, 18 Jan 2022 14:39:48 +0900 Yuji Ishikawa wrote:
> > This series is a fix for RMII/MII operation mode of the dwmac-visconti driver.
> > It is composed of two parts:
> >
> > * 1/2: fix constant definitions for cleared bits in ETHER_CLK_SEL
> > register
> > * 2/2: fix configuration of ETHER_CLK_SEL register for running in RMII operation mode.
>
> Please add appropriate Fixes tag pointing to the commits where the buggy code was introduced, even if it's the initial commit adding the driver.
Best regards,
Yuji Ishikawa