The main goal of this patchset was to add Baikal-T1 AHCI SATA specifics
support into the kernel AHCI subsystem. On the way of doing that we
figured out that mainly these specifics are actually DWC AHCI SATA
controller features, but still there were some Baikal-T1 SoC platform
peculiarities which we had to take into account. So the patchset
introduces two AHCI SATA controllers support and one AHCI SATA driver
with a series of preparation, optimization and cleanup patches.
The series starts used to start with converting the legacy AHCI SATA
controllers text-based DT-bindings to the DT-schema. But turned out that
has already been done in kernel v5.17. So instead we suggest to improve
the bindings usability by splitting up the AHCI DT bindings into two
schemas: one common AHCI SATA controller yaml-file, which can be reused by
any AHCI-compatible controller utilizing the kernel AHCI library
functions, and DT-bindings for the generic AHCI SATA devices indicated by
the "generic-ahci" compatible string and implemented in the
ahci_platform.c driver. Note after doing that we had to fix the
sata-common.yaml file SATA port IDs constraint.
Then a series of generic preparations-cleanups goes. First of all it
concerns the device-managed methods usage in the framework of the CSR
space remapping and the clocks requesting and enabling. Note since the
clocks handlers are requested and kept in the generic AHCI library it
seemed a good idea to add an AHCI-platform generic method to find and get
a particular clock handler from the pool of the requested ones. It was
used later in the series in the DWC/Baikal-T1-specific code. Secondly we
suggested to at least sanity check the number of SATA ports DT-sub-nodes
before using it further. Thirdly the ports-implemented DT-property
parsing was moved from the AHCI platform-driver to the AHCI-library so to
be used by the non-generic AHCI drivers if required (DT-schema is
accordingly fixed too). Finally due to having the shared-reset control
support we had to add a new AHCI-resource getter flag -
AHCI_PLATFORM_RST_TRIGGER, which indicated using a trigger-like reset
control. For such platforms the controller reset will be performed by
means of the reset_control_reset() and reset_control_rearm() methods.
AHCI-library reset functions encapsulating the way the reset procedure is
performed have been also added.
After that goes a patches series with the platform-specific
AHCI-capabilities initialization. The suggested functionality will be
useful for the platforms with no BIOS, comprehensive bootloader/firmware
installed. In that case the AHCI-related platform-specifics like drive
staggered spin-up, mechanical presence switch attached or FIS-based
switching capability usage, etc will be left uninitialized with no generic
way to be indicated as available if required. We suggested to use the AHCI
device tree node and its ports sub-nodes for that. AHCI-platform library
will be responsible fo the corresponding DT-properties parsing and
pre-initialization of the internal capability registers cache, which will
be then flashed back to the corresponding CSR after HBA reset. Thus a
supposed to be firmware-work will be done by means of the AHCI-library and
the DT-data. A set of the preparations/cleanups required to be done before
introducing the feature. First the DT-properties indicating the
corresponding capability availability were described in the common AHCI
DT-binding schema. Second we needed to add the enum items with the AHCI
Port CMD fields, which hadn't been added so far. Thirdly we suggested to
discard one of the port-map internal storage (force_port_map) in favor of
re-using another one (save_port_map) in order to simplify the port-map
initialization interface a bit by getting rid from a redundant variable.
Finally after discarding the double AHCI-version read procedure and
changing the __ahci_port_base() method prototype the platform
firmware-specific caps initialization functionality was introduced.
The main part of the series goes afterwards. A dedicated DWC AHCI SATA
controller driver was introduced together with the corresponding
DT-binding schema pre-patch. Note the driver built mode is activated
synchronously with the generic AHCI-platform driver by default so
automatically to be integrated into the kernel for the DWC AHCI-based
platforms which relied on activating the generic AHCI SATA controller
driver. Aside with the generic resources getting and AHCI-host
initialization, the driver implements the DWC-specific setups. In
particular it checks whether the platform capabilities activated by the
firmware (see the functionality described above) are actually supported by
the controller. It's done by means of the vendor-specific registers. Then
it makes sure that the embedded 1ms timer interval, which is used for the
DevSleep and CCC features, is correctly initialized based on the
application clock rate. The last but not least the driver provides a way
to tune the DMA-interface performance up by setting the Tx/Rx transactions
maximum size up. The required values are specified by means of the
"snps,tx-ts-max" and snps,rx-ts-max" DT-properties.
Finally we suggest to extend the DWC AHCI SATA controller driver
functionality with a way to add the DWC-AHCI-based platform-specific
quirks. Indeed there are many DWC AHCI-based controllers and just a few of
them are diverged too much to be handled by a dedicated AHCI-driver. The
rest of them most likely can work well either with a generic version of
the driver or require a simple normally platform-specific quirk to get up
and running. Such platforms can define a platform-data in the DWC AHCI
driver with a set of the controller-specific flags and initialization
functions. Those functions will be called at the corresponding stages of
the device probe/resume/remove procedures so to be performing the platform
setups/cleanups.
After the denoted above functionality is added we can finally introduce
the Baikal-T1 AHCI SATA controller support into the DWC AHCI SATA driver.
The controller is based on the DWC AHCI SATA IP-core v4.10a and can work
well with the generic DWC AHCI driver. The only peculiarity of it is
connected with the SATA Ports reference clock source. It can be supplied
either from the internal SoC PLL or from the chip pads. Currently we have
to prefer selecting the signal coming from the pads if the corresponding
clock source is specified because the link doesn't get stably established
when the internal clock signal is activated. In addition the platform has
trigger-based reset signals so the corresponding flag must be passed to
the generic AHCI-resource getter.
Link: https://lore.kernel.org/linux-ide/[email protected]/
Changelog v2:
- Rebase from kernel v5.17 to v5.18-rc3. (@Rob)
- Rebase onto the already available AHCI DT schema. As a result two more
patches have been added. (@Rob)
- Rename 'syscon' property to 'baikal,bt1-syscon'. (@Rob)
- Replace min/max constraints of the snps,{tx,rx}-ts-max property with
enum [ 1, 2, 4, ..., 1024 ]. (@Rob)
- Use dlemoal/libata.git git tree for the LIBATA SATA AHCI SYNOPSYS
DWC driver (@Damien).
- Change the local objects prefix from 'dwc_ahci_' to 'ahci_dwc_',
from 'bt1_ahci_' to 'ahci_bt1_'. (@Damien)
- Use LLDD term in place of 'glue-driver'. (@Damien)
- Convert the ahci_platform_assert_rsts() method to returning int status
(@Damien).
- Drop the else word from the DT child_nodes value checking if-else-if
statement (@Damien) and convert the after-else part into the ternary
operator-based statement.
- Convert to checking the error-case first in the devm_clk_bulk_get_all()
method invocation. (@Damien)
- Drop the rc variable initialization in the ahci_platform_get_resources()
method. (@Damien)
- Add comma and replace "channel" with "SATA port" in the reg property
description of the sata-common.yaml schema. (@Damien)
Signed-off-by: Serge Semin <[email protected]>
Cc: Alexey Malahov <[email protected]>
Cc: Pavel Parkhomenko <[email protected]>
Cc: Rob Herring <[email protected]>
Cc: [email protected]
Cc: [email protected]
Cc: [email protected]
Serge Semin (23):
dt-bindings: ata: ahci-platform: Drop dma-coherent property
declaration
dt-bindings: ata: ahci-platform: Detach common AHCI bindings
dt-bindings: ata: ahci-platform: Clarify common AHCI props constraints
dt-bindings: ata: sata: Extend number of SATA ports
ata: libahci_platform: Explicitly set rc on devres_alloc failure
ata: libahci_platform: Convert to using platform devm-ioremap methods
ata: libahci_platform: Convert to using devm bulk clocks API
ata: libahci_platform: Add function returning a clock-handle by id
ata: libahci_platform: Sanity check the DT child nodes number
ata: libahci_platform: Parse ports-implemented property in resources
getter
ata: libahci_platform: Introduce reset assertion/deassertion methods
dt-bindings: ata: ahci: Add platform capability properties
ata: libahci: Extend port-cmd flags set with port capabilities
ata: libahci: Discard redundant force_port_map parameter
ata: libahci: Don't read AHCI version twice in the save-config method
ata: ahci: Convert __ahci_port_base to accepting hpriv as arguments
ata: ahci: Introduce firmware-specific caps initialization
dt-bindings: ata: ahci: Add DWC AHCI SATA controller DT schema
ata: ahci: Add DWC AHCI SATA controller support
dt-bindings: ata: ahci: Add Baikal-T1 AHCI SATA controller DT schema
ata: ahci-dwc: Add platform-specific quirks support
ata: ahci-dwc: Add Baikal-T1 AHCI SATA interface support
MAINTAINERS: Add maintainers for DWC AHCI SATA driver
.../devicetree/bindings/ata/ahci-common.yaml | 188 +++++++
.../bindings/ata/ahci-platform.yaml | 89 +--
.../bindings/ata/baikal,bt1-ahci.yaml | 127 +++++
.../devicetree/bindings/ata/sata-common.yaml | 7 +-
.../bindings/ata/snps,dwc-ahci.yaml | 123 ++++
MAINTAINERS | 9 +
drivers/ata/Kconfig | 11 +
drivers/ata/Makefile | 1 +
drivers/ata/ahci.c | 4 +-
drivers/ata/ahci.h | 21 +-
drivers/ata/ahci_dwc.c | 526 ++++++++++++++++++
drivers/ata/ahci_mtk.c | 2 -
drivers/ata/ahci_platform.c | 5 -
drivers/ata/ahci_st.c | 3 -
drivers/ata/libahci.c | 63 ++-
drivers/ata/libahci_platform.c | 236 ++++++--
include/linux/ahci_platform.h | 8 +-
17 files changed, 1258 insertions(+), 165 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ata/ahci-common.yaml
create mode 100644 Documentation/devicetree/bindings/ata/baikal,bt1-ahci.yaml
create mode 100644 Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml
create mode 100644 drivers/ata/ahci_dwc.c
--
2.35.1
There are systems with no BIOS or comprehensive embedded firmware which
could be able to properly initialize the SATA AHCI controller
platform-specific capabilities. In that case a good alternative to having
a clever bootloader is to create a device tree node with the properties
well describing all the AHCI-related platform specifics. All the settings
which are normally detected and marked as available in the HBA and its
ports capabilities fields [1] could be defined in the platform DTB by
means of a set of the dedicated properties. Such approach perfectly fits
to the DTB-philosophy - to provide hardware/platform description.
So here we suggest to extend the SATA AHCI device tree bindings with the
next set of additional DT boolean properties:
1) hba-sss - Controller supports Staggered Spin-up.
2) hba-smps - Mechanical Presence Switch is support by controller.
3) hba-hpcp - Hot Plug Capable Port.
4) hba-mpsp - Mechanical Presence Switch Attached to Port.
5) hba-cpd - Cold Presence Detection.
6) hba-esp - External SATA Port.
7) hba-fbscp - FIS-based Switching Capable Port.
All of these capabilities require to have a corresponding hardware
configuration. Thus it's ok to have them defined in DTB.
Even though the driver currently takes into account the state of the ESP
and FBSCP flags state only, there is nothing wrong with having all them
supported by the generic AHCI library in order to have a complete OF-based
platform-capabilities initialization procedure. These properties will be
parsed in the ahci_platform_get_resources() method and their values will
be stored in the saved_* fields of the ahci_host_priv structure, which in
its turn then will be used to restore the H.CAP, H.PI and P#.CMD
capability fields on device init and after HBA reset.
Please note this modification concerns the HW-init HBA and its ports flags
only, which are by specification [1] are supposed to be initialized by the
BIOS/platform firmware/expansion ROM and which are normally declared in
the one-time-writable-after-reset register fields. Even though these flags
aren't supposed to be cleared after HBA reset some AHCI instances may
violate that rule so we still need to perform the fields resetting after
each reset. Luckily the corresponding functionality has already been
partly implemented in the framework of the ahci_save_initial_config() and
ahci_restore_initial_config() methods.
[1] Serial ATA AHCI 1.3.1 Specification, p. 103
Signed-off-by: Serge Semin <[email protected]>
---
drivers/ata/ahci.h | 1 +
drivers/ata/libahci.c | 51 ++++++++++++++++++++++++++++------
drivers/ata/libahci_platform.c | 51 ++++++++++++++++++++++++++++++++--
3 files changed, 92 insertions(+), 11 deletions(-)
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index 8b9826533ae5..0de221055961 100644
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -337,6 +337,7 @@ struct ahci_host_priv {
u32 saved_cap; /* saved initial cap */
u32 saved_cap2; /* saved initial cap2 */
u32 saved_port_map; /* saved initial port_map */
+ u32 saved_port_cap[AHCI_MAX_PORTS]; /* saved port_cap */
u32 em_loc; /* enclosure management location */
u32 em_buf_sz; /* EM buffer size in byte */
u32 em_msg_type; /* EM message type */
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
index 1ffaa5f5f21a..763ff1058da6 100644
--- a/drivers/ata/libahci.c
+++ b/drivers/ata/libahci.c
@@ -16,6 +16,7 @@
* http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
*/
+#include <linux/bitops.h>
#include <linux/kernel.h>
#include <linux/gfp.h>
#include <linux/module.h>
@@ -443,16 +444,28 @@ static ssize_t ahci_show_em_supported(struct device *dev,
void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
{
void __iomem *mmio = hpriv->mmio;
- u32 cap, cap2, vers, port_map;
+ void __iomem *port_mmio;
+ unsigned long port_map;
+ u32 cap, cap2, vers;
int i;
/* make sure AHCI mode is enabled before accessing CAP */
ahci_enable_ahci(mmio);
- /* Values prefixed with saved_ are written back to host after
- * reset. Values without are used for driver operation.
+ /*
+ * Values prefixed with saved_ are written back to the HBA and ports
+ * registers after reset. Values without are used for driver operation.
+ */
+
+ /*
+ * Override HW-init HBA capability fields with platform-specific values.
+ * The rest of the HBA capabilities are defined with strictly RO flags
+ * and can't be modified in CSR anyway.
*/
- hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
+ cap = readl(mmio + HOST_CAP);
+ if (hpriv->saved_cap)
+ cap = (cap & ~(HOST_CAP_SSS | HOST_CAP_MPS)) | hpriv->saved_cap;
+ hpriv->saved_cap = cap;
/* CAP2 register is only defined for AHCI 1.2 and later */
vers = readl(mmio + HOST_VERSION);
@@ -519,7 +532,7 @@ void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
/* Override the HBA ports mapping if the platform needs it */
port_map = readl(mmio + HOST_PORTS_IMPL);
if (hpriv->saved_port_map && port_map != hpriv->saved_port_map) {
- dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
+ dev_info(dev, "forcing port_map 0x%lx -> 0x%x\n",
port_map, hpriv->saved_port_map);
port_map = hpriv->saved_port_map;
} else {
@@ -527,7 +540,7 @@ void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
}
if (hpriv->mask_port_map) {
- dev_warn(dev, "masking port_map 0x%x -> 0x%x\n",
+ dev_warn(dev, "masking port_map 0x%lx -> 0x%lx\n",
port_map,
port_map & hpriv->mask_port_map);
port_map &= hpriv->mask_port_map;
@@ -546,7 +559,7 @@ void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
*/
if (map_ports > ahci_nr_ports(cap)) {
dev_warn(dev,
- "implemented port map (0x%x) contains more ports than nr_ports (%u), using nr_ports\n",
+ "implemented port map (0x%lx) contains more ports than nr_ports (%u), using nr_ports\n",
port_map, ahci_nr_ports(cap));
port_map = 0;
}
@@ -555,12 +568,26 @@ void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
/* fabricate port_map from cap.nr_ports for < AHCI 1.3 */
if (!port_map && vers < 0x10300) {
port_map = (1 << ahci_nr_ports(cap)) - 1;
- dev_warn(dev, "forcing PORTS_IMPL to 0x%x\n", port_map);
+ dev_warn(dev, "forcing PORTS_IMPL to 0x%lx\n", port_map);
/* write the fixed up value to the PI register */
hpriv->saved_port_map = port_map;
}
+ /*
+ * Preserve the ports capabilities defined by the platform. Note there
+ * is no need in storing the rest of the P#.CMD fields since they are
+ * volatile.
+ */
+ for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {
+ if (hpriv->saved_port_cap[i])
+ continue;
+
+ port_mmio = __ahci_port_base(hpriv, i);
+ hpriv->saved_port_cap[i] =
+ readl(port_mmio + PORT_CMD) & PORT_CMD_CAP;
+ }
+
/* record values to use during operation */
hpriv->cap = cap;
hpriv->cap2 = cap2;
@@ -590,13 +617,21 @@ EXPORT_SYMBOL_GPL(ahci_save_initial_config);
static void ahci_restore_initial_config(struct ata_host *host)
{
struct ahci_host_priv *hpriv = host->private_data;
+ unsigned long port_map = hpriv->port_map;
void __iomem *mmio = hpriv->mmio;
+ void __iomem *port_mmio;
+ int i;
writel(hpriv->saved_cap, mmio + HOST_CAP);
if (hpriv->saved_cap2)
writel(hpriv->saved_cap2, mmio + HOST_CAP2);
writel(hpriv->saved_port_map, mmio + HOST_PORTS_IMPL);
(void) readl(mmio + HOST_PORTS_IMPL); /* flush */
+
+ for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {
+ port_mmio = __ahci_port_base(hpriv, i);
+ writel(hpriv->saved_port_cap[i], port_mmio + PORT_CMD);
+ }
}
static unsigned ahci_scr_offset(struct ata_port *ap, unsigned int sc_reg)
diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c
index 56aced7a76cd..dece57364a3d 100644
--- a/drivers/ata/libahci_platform.c
+++ b/drivers/ata/libahci_platform.c
@@ -23,6 +23,7 @@
#include <linux/pm_runtime.h>
#include <linux/of_platform.h>
#include <linux/reset.h>
+
#include "ahci.h"
static void ahci_host_stop(struct ata_host *host);
@@ -410,6 +411,44 @@ static int ahci_platform_get_regulator(struct ahci_host_priv *hpriv, u32 port,
return rc;
}
+static int ahci_platform_get_firmware(struct ahci_host_priv *hpriv,
+ struct device *dev)
+{
+ struct device_node *child;
+ u32 port;
+
+ of_property_read_u32(dev->of_node,
+ "ports-implemented", &hpriv->saved_port_map);
+
+ if (of_property_read_bool(dev->of_node, "hba-sss"))
+ hpriv->saved_cap |= HOST_CAP_SSS;
+ if (of_property_read_bool(dev->of_node, "hba-smps"))
+ hpriv->saved_cap |= HOST_CAP_MPS;
+
+ for_each_child_of_node(dev->of_node, child) {
+ if (!of_device_is_available(child))
+ continue;
+
+ if (of_property_read_u32(child, "reg", &port)) {
+ of_node_put(child);
+ return -EINVAL;
+ }
+
+ if (of_property_read_bool(child, "hba-hpcp"))
+ hpriv->saved_port_cap[port] |= PORT_CMD_HPCP;
+ if (of_property_read_bool(child, "hba-mpsp"))
+ hpriv->saved_port_cap[port] |= PORT_CMD_MPSP;
+ if (of_property_read_bool(child, "hba-cpd"))
+ hpriv->saved_port_cap[port] |= PORT_CMD_CPD;
+ if (of_property_read_bool(child, "hba-esp"))
+ hpriv->saved_port_cap[port] |= PORT_CMD_ESP;
+ if (of_property_read_bool(child, "hba-fbscp"))
+ hpriv->saved_port_cap[port] |= PORT_CMD_FBSCP;
+ }
+
+ return 0;
+}
+
/**
* ahci_platform_get_resources - Get platform resources
* @pdev: platform device to get resources for
@@ -552,9 +591,6 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev,
goto err_out;
}
- of_property_read_u32(dev->of_node,
- "ports-implemented", &hpriv->saved_port_map);
-
if (child_nodes) {
for_each_child_of_node(dev->of_node, child) {
u32 port;
@@ -619,6 +655,15 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev,
if (rc == -EPROBE_DEFER)
goto err_out;
}
+
+ /*
+ * Retrieve firmware-specific flags which then will be used to set
+ * the HW-init fields of HBA and its ports
+ */
+ rc = ahci_platform_get_firmware(hpriv, dev);
+ if (rc)
+ goto err_out;
+
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
hpriv->got_runtime_pm = true;
--
2.35.1
In order to create a more sophisticated AHCI controller DT bindings let's
divide the already available generic AHCI platform YAML schema into the
platform part and a set of the common AHCI properties. The former part
will be used to evaluate the AHCI DT nodes mainly compatible with the
generic AHCI controller while the later schema will be used for more
thorough AHCI DT nodes description. For instance such YAML schemas design
will be useful for our DW AHCI SATA controller derivative with four clock
sources, two reset lines, one system controller reference and specific
max Rx/Tx DMA xfers size constraints.
Note the phys and target-supply property requirement is preserved in the
generic AHCI platform bindings because some platforms can lack of the
explicitly specified PHYs or target device power regulators.
Signed-off-by: Serge Semin <[email protected]>
---
Folks, I don't really see why the phys/target-supply requirement has been
added to the generic AHCI DT schema in the first place. Probably just to
imply some meaning for the sub-nodes definition. Anyway in one of the
further patches I am adding the DW AHCI SATA controller DT bindings which
won't require having these properties specified in the sub-nodes, but will
describe additional port-specific properties. That's why I get to keep the
constraints in the ahci-platform.yaml schema instead of moving them to the
common schema.
Changelog v2:
- This is a new patch created after rebasing v1 onto the 5.18-rc3 kernel.
---
.../devicetree/bindings/ata/ahci-common.yaml | 117 ++++++++++++++++++
.../bindings/ata/ahci-platform.yaml | 68 +---------
2 files changed, 123 insertions(+), 62 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ata/ahci-common.yaml
diff --git a/Documentation/devicetree/bindings/ata/ahci-common.yaml b/Documentation/devicetree/bindings/ata/ahci-common.yaml
new file mode 100644
index 000000000000..72e24b246040
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/ahci-common.yaml
@@ -0,0 +1,117 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ata/ahci-common.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Common Properties for Serial ATA AHCI controllers
+
+maintainers:
+ - Hans de Goede <[email protected]>
+ - Jens Axboe <[email protected]>
+
+description:
+ This document defines device tree properties for a common AHCI SATA
+ controller implementation. It's hardware interface is supposed to
+ conform to the technical standard defined by Intel (see Serial ATA
+ Advanced Host Controller Interface specification for details). The
+ document doesn't constitute a DT-node binding by itself but merely
+ defines a set of common properties for the AHCI-compatible devices.
+
+select: false
+
+allOf:
+ - $ref: sata-common.yaml#
+
+properties:
+ reg:
+ description:
+ Generic AHCI registers space conforming to the Serial ATA AHCI
+ specification.
+
+ reg-names:
+ description: CSR space IDs
+
+ interrupts:
+ description:
+ Generic AHCI state change interrupt. Can be implemented either as a
+ single line attached to the controller as a set of the dedicated signals
+ for the global and particular port events.
+
+ clocks:
+ description:
+ List of all the reference clocks connected to the controller.
+
+ clock-names:
+ description: Reference clocks IDs
+
+ resets:
+ description:
+ List of the reset control lines to reset the controller clock
+ domains.
+
+ reset-names:
+ description: Reset line IDs
+
+ power-domains:
+ description:
+ List of the power domain the AHCI controller being a part of.
+
+ ahci-supply:
+ description: Power regulator for AHCI controller
+
+ target-supply:
+ description: Power regulator for SATA target device
+
+ phy-supply:
+ description: Power regulator for SATA PHY
+
+ phys:
+ description: Reference to the SATA PHY node
+ maxItems: 1
+
+ phy-names:
+ maxItems: 1
+
+ ports-implemented:
+ $ref: '/schemas/types.yaml#/definitions/uint32'
+ description:
+ Mask that indicates which ports the HBA supports. Useful if PI is not
+ programmed by the BIOS, which is true for some embedded SoC's.
+ maximum: 0x1f
+
+patternProperties:
+ "^sata-port@[0-9a-f]+$":
+ type: object
+ description:
+ It is optionally possible to describe the ports as sub-nodes so
+ to enable each port independently when dealing with multiple PHYs.
+
+ properties:
+ reg:
+ description: AHCI SATA port identifier
+ maxItems: 1
+
+ phys:
+ description: Individual AHCI SATA port PHY
+ maxItems: 1
+
+ phy-names:
+ description: AHCI SATA port PHY ID
+ maxItems: 1
+
+ target-supply:
+ description: Power regulator for SATA port target device
+
+ required:
+ - reg
+
+ additionalProperties: true
+
+required:
+ - reg
+ - interrupts
+
+additionalProperties: true
+
+...
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.yaml b/Documentation/devicetree/bindings/ata/ahci-platform.yaml
index 9304e4731965..76075d3c8987 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.yaml
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.yaml
@@ -36,8 +36,7 @@ select:
- compatible
allOf:
- - $ref: "sata-common.yaml#"
-
+ - $ref: "ahci-common.yaml#"
properties:
compatible:
@@ -69,90 +68,35 @@ properties:
maxItems: 1
clocks:
- description:
- Clock IDs array as required by the controller.
minItems: 1
maxItems: 3
clock-names:
- description:
- Names of clocks corresponding to IDs in the clock property.
minItems: 1
maxItems: 3
interrupts:
maxItems: 1
- ahci-supply:
- description:
- regulator for AHCI controller
-
- phy-supply:
- description:
- regulator for PHY power
-
- phys:
- description:
- List of all PHYs on this controller
- maxItems: 1
-
- phy-names:
- description:
- Name specifier for the PHYs
- maxItems: 1
-
- ports-implemented:
- $ref: '/schemas/types.yaml#/definitions/uint32'
- description: |
- Mask that indicates which ports that the HBA supports
- are available for software to use. Useful if PORTS_IMPL
- is not programmed by the BIOS, which is true with
- some embedded SoCs.
- maximum: 0x1f
-
power-domains:
maxItems: 1
resets:
maxItems: 1
- target-supply:
- description:
- regulator for SATA target power
-
-required:
- - compatible
- - reg
- - interrupts
-
patternProperties:
"^sata-port@[0-9a-f]+$":
type: object
- additionalProperties: false
- description:
- Subnode with configuration of the Ports.
-
- properties:
- reg:
- maxItems: 1
-
- phys:
- maxItems: 1
-
- phy-names:
- maxItems: 1
-
- target-supply:
- description:
- regulator for SATA target power
-
- required:
- - reg
anyOf:
- required: [ phys ]
- required: [ target-supply ]
+required:
+ - compatible
+ - reg
+ - interrupts
+
unevaluatedProperties: false
examples:
--
2.35.1
It's almost fully compatible DWC AHCI SATA IP-core derivative except the
reference clocks source, which need to be very carefully selected. In
particular the DWC AHCI SATA PHY can be clocked either from the pads
ref_pad_clk_{m,p} or from the internal wires ref_alt_clk_{m,n}. In the
later case the clock signal is generated from the Baikal-T1 CCU SATA PLL.
The clocks source is selected by means of the ref_use_pad wire connected
to the CCU SATA reference clock CSR.
In normal situation it would be much more handy to use the internal
reference clock source, but alas we haven't managed to make the AHCI
controller working well with it so far. So it's preferable to have the
controller clocked from the external clock generator and fallback to the
internal clock source only as a last resort. Other than that the
controller is full compatible with the DWC AHCI SATA IP-core.
Signed-off-by: Serge Semin <[email protected]>
---
Changelog v2:
- Rename 'syscon' property to 'baikal,bt1-syscon'.
- Change the local objects prefix from 'dwc_ahci_' to 'ahci_dwc_',
from 'bt1_ahci_' to 'ahci_bt1_'. (@Damien)
---
drivers/ata/Kconfig | 1 +
drivers/ata/ahci_dwc.c | 87 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 88 insertions(+)
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 95e0e022b5bb..249717cdc74f 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -180,6 +180,7 @@ config AHCI_DWC
tristate "Synopsys DWC AHCI SATA support"
select SATA_HOST
default SATA_AHCI_PLATFORM
+ select MFD_SYSCON if (MIPS_BAIKAL_T1 || COMPILE_TEST)
help
This option enables support for the Synopsys DWC AHCI SATA
controller implementation.
diff --git a/drivers/ata/ahci_dwc.c b/drivers/ata/ahci_dwc.c
index f987efa1ad59..d464db20f869 100644
--- a/drivers/ata/ahci_dwc.c
+++ b/drivers/ata/ahci_dwc.c
@@ -13,10 +13,12 @@
#include <linux/kernel.h>
#include <linux/libata.h>
#include <linux/log2.h>
+#include <linux/mfd/syscon.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/platform_device.h>
#include <linux/pm.h>
+#include <linux/regmap.h>
#include "ahci.h"
@@ -90,6 +92,26 @@
#define AHCI_DWC_PORT_PHYCR 0x74
#define AHCI_DWC_PORT_PHYSR 0x78
+/* Baikal-T1 AHCI SATA specific registers */
+#define AHCI_BT1_HOST_PHYCR AHCI_DWC_HOST_GPCR
+#define AHCI_BT1_HOST_MPLM_MASK GENMASK(29, 23)
+#define AHCI_BT1_HOST_LOSDT_MASK GENMASK(22, 20)
+#define AHCI_BT1_HOST_CRR BIT(19)
+#define AHCI_BT1_HOST_CRW BIT(18)
+#define AHCI_BT1_HOST_CRCD BIT(17)
+#define AHCI_BT1_HOST_CRCA BIT(16)
+#define AHCI_BT1_HOST_CRDI_MASK GENMASK(15, 0)
+
+#define AHCI_BT1_HOST_PHYSR AHCI_DWC_HOST_GPSR
+#define AHCI_BT1_HOST_CRA BIT(16)
+#define AHCI_BT1_HOST_CRDO_MASK GENMASK(15, 0)
+
+/* Baikal-T1 CCU registers concerning the AHCI SATA module */
+#define BT1_CCU_SYS_SATA_REF 0x60
+#define BT1_CCU_SYS_SATA_REF_EXT BIT(28)
+#define BT1_CCU_SYS_SATA_REF_INV BIT(29)
+#define BT1_CCU_SYS_SATA_REF_BUF BIT(30)
+
struct ahci_dwc_plat_data {
unsigned int pflags;
unsigned int hflags;
@@ -106,6 +128,65 @@ struct ahci_dwc_host_priv {
u32 dmacr[AHCI_MAX_PORTS];
};
+static int ahci_bt1_init(struct ahci_host_priv *hpriv)
+{
+ struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;
+ struct regmap *sys_regs;
+ u32 ref_ctl, mask;
+
+ /* APB and application clocks are required */
+ if (!ahci_platform_find_clk(hpriv, "pclk") ||
+ !ahci_platform_find_clk(hpriv, "aclk")) {
+ dev_err(&dpriv->pdev->dev, "No system clocks specified\n");
+ return -EINVAL;
+ }
+
+ /*
+ * We need to select the PHY reference clock source. The signal
+ * can be delivered either from the chip pads or from the internal
+ * PLL. The source is selected by the PHY's ref_use_pad signal
+ * tied up into one of the CCU SATA ref-ctl register field.
+ */
+ sys_regs = syscon_regmap_lookup_by_phandle(dpriv->pdev->dev.of_node,
+ "baikal,bt1-syscon");
+ if (IS_ERR(sys_regs)) {
+ dev_err(&dpriv->pdev->dev, "CCU syscon couldn't be found\n");
+ return PTR_ERR(sys_regs);
+ }
+
+ (void)regmap_read(sys_regs, BT1_CCU_SYS_SATA_REF, &ref_ctl);
+
+ /*
+ * Prefer activating external reference clock if one is supplied.
+ * If there is no external ref clock, then we have no choice but
+ * to fall back to the internal signal coming from PLL. Alas
+ * we haven't managed to make the interface working well when it's
+ * used so far, but in no alternative let's at least try...
+ */
+ if (ahci_platform_find_clk(hpriv, "ref_ext")) {
+ ref_ctl |= BT1_CCU_SYS_SATA_REF_EXT;
+ mask = BT1_CCU_SYS_SATA_REF_EXT;
+ } else if (ahci_platform_find_clk(hpriv, "ref_int")) {
+ ref_ctl &= ~BT1_CCU_SYS_SATA_REF_EXT;
+ ref_ctl |= BT1_CCU_SYS_SATA_REF_INV | BT1_CCU_SYS_SATA_REF_BUF;
+ mask = BT1_CCU_SYS_SATA_REF_EXT |
+ BT1_CCU_SYS_SATA_REF_INV | BT1_CCU_SYS_SATA_REF_BUF;
+ dev_warn(&dpriv->pdev->dev, "Fallback to PLL-based ref clock!\n");
+ } else {
+ dev_err(&dpriv->pdev->dev, "No ref clock specified\n");
+ return -EINVAL;
+ }
+
+ regmap_update_bits(sys_regs, BT1_CCU_SYS_SATA_REF, mask, ref_ctl);
+
+ /*
+ * Fully reset the SATA AXI and ref clocks domain so to ensure the
+ * state machine is working from scratch.
+ */
+ ahci_platform_assert_rsts(hpriv);
+ return ahci_platform_deassert_rsts(hpriv);
+}
+
static struct ahci_host_priv *ahci_dwc_get_resources(struct platform_device *pdev)
{
struct ahci_dwc_host_priv *dpriv;
@@ -415,9 +496,15 @@ struct ahci_dwc_plat_data ahci_dwc_plat = {
.pflags = AHCI_PLATFORM_GET_RESETS,
};
+struct ahci_dwc_plat_data ahci_bt1_plat = {
+ .pflags = AHCI_PLATFORM_GET_RESETS | AHCI_PLATFORM_RST_TRIGGER,
+ .init = ahci_bt1_init,
+};
+
static const struct of_device_id ahci_dwc_of_match[] = {
{ .compatible = "snps,dwc-ahci", &ahci_dwc_plat },
{ .compatible = "snps,spear-ahci", &ahci_dwc_plat },
+ { .compatible = "baikal,bt1-ahci", &ahci_bt1_plat },
{},
};
MODULE_DEVICE_TABLE(of, ahci_dwc_of_match);
--
2.35.1
Since all the clocks are retrieved by the method
ahci_platform_get_resources() there is no need for the LLD (glue) drivers
to be looking for some particular of them in the kernel clocks table
again. Instead we suggest to add a simple method returning a
device-specific clock with passed connection ID if it is managed to be
found. Otherwise the function will return NULL. Thus the glue-drivers
won't need to either manually touching the hpriv->clks array or calling
clk_get()-friends. The AHCI platform drivers will be able to use the new
function right after the ahci_platform_get_resources() method invocation
and up to the device removal.
Signed-off-by: Serge Semin <[email protected]>
---
Changelog v2:
- Fix some grammar mistakes in the method description.
---
drivers/ata/libahci_platform.c | 27 +++++++++++++++++++++++++++
include/linux/ahci_platform.h | 3 +++
2 files changed, 30 insertions(+)
diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c
index 3cff86c225fd..7ff6626fd569 100644
--- a/drivers/ata/libahci_platform.c
+++ b/drivers/ata/libahci_platform.c
@@ -94,6 +94,33 @@ void ahci_platform_disable_phys(struct ahci_host_priv *hpriv)
}
EXPORT_SYMBOL_GPL(ahci_platform_disable_phys);
+/**
+ * ahci_platform_find_clk - Find platform clock
+ * @hpriv: host private area to store config values
+ * @con_id: clock connection ID
+ *
+ * This function returns a pointer to the clock descriptor of the clock with
+ * the passed ID.
+ *
+ * RETURNS:
+ * Pointer to the clock descriptor on success otherwise NULL
+ */
+struct clk *ahci_platform_find_clk(struct ahci_host_priv *hpriv, const char *con_id)
+{
+ struct clk *clk = NULL;
+ int i;
+
+ for (i = 0; i < hpriv->n_clks; i++) {
+ if (!strcmp(hpriv->clks[i].id, con_id)) {
+ clk = hpriv->clks[i].clk;
+ break;
+ }
+ }
+
+ return clk;
+}
+EXPORT_SYMBOL_GPL(ahci_platform_find_clk);
+
/**
* ahci_platform_enable_clks - Enable platform clocks
* @hpriv: host private area to store config values
diff --git a/include/linux/ahci_platform.h b/include/linux/ahci_platform.h
index 49e5383d4222..fd964e6a68d6 100644
--- a/include/linux/ahci_platform.h
+++ b/include/linux/ahci_platform.h
@@ -13,6 +13,7 @@
#include <linux/compiler.h>
+struct clk;
struct device;
struct ata_port_info;
struct ahci_host_priv;
@@ -21,6 +22,8 @@ struct scsi_host_template;
int ahci_platform_enable_phys(struct ahci_host_priv *hpriv);
void ahci_platform_disable_phys(struct ahci_host_priv *hpriv);
+struct clk *
+ahci_platform_find_clk(struct ahci_host_priv *hpriv, const char *con_id);
int ahci_platform_enable_clks(struct ahci_host_priv *hpriv);
void ahci_platform_disable_clks(struct ahci_host_priv *hpriv);
int ahci_platform_enable_regulators(struct ahci_host_priv *hpriv);
--
2.35.1
Having greater than (AHCI_MAX_PORTS = 32) ports detected isn't that
critical from the further AHCI-platform initialization point of view since
exceeding the ports upper limit will cause allocating more resources than
will be used afterwards. But detecting too many child DT-nodes doesn't
seem right since it's very unlikely to have it on an ordinary platform. In
accordance with the AHCI specification there can't be more than 32 ports
implemented at least due to having the CAP.NP field of 4 bits wide and the
PI register of dword size. Thus if such situation is found the DTB must
have been corrupted and the data read from it shouldn't be reliable. Let's
consider that as an erroneous situation and halt further resources
allocation.
Note it's logically more correct to have the nports set only after the
initialization value is checked for being sane. So while at it let's make
sure nports is assigned with a correct value.
Signed-off-by: Serge Semin <[email protected]>
---
Changelog v2:
- Drop the else word from the child_nodes value checking if-else-if
statement (@Damien) and convert the after-else part into the ternary
operator-based statement.
---
drivers/ata/libahci_platform.c | 13 ++++++++++---
1 file changed, 10 insertions(+), 3 deletions(-)
diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c
index 7ff6626fd569..4e54e19f07b2 100644
--- a/drivers/ata/libahci_platform.c
+++ b/drivers/ata/libahci_platform.c
@@ -480,15 +480,22 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev,
}
}
- hpriv->nports = child_nodes = of_get_child_count(dev->of_node);
+ /*
+ * Too many sub-nodes most likely means having something wrong with
+ * the firmware.
+ */
+ child_nodes = of_get_child_count(dev->of_node);
+ if (child_nodes > AHCI_MAX_PORTS) {
+ rc = -EINVAL;
+ goto err_out;
+ }
/*
* If no sub-node was found, we still need to set nports to
* one in order to be able to use the
* ahci_platform_[en|dis]able_[phys|regulators] functions.
*/
- if (!child_nodes)
- hpriv->nports = 1;
+ hpriv->nports = child_nodes ?: 1;
hpriv->phys = devm_kcalloc(dev, hpriv->nports, sizeof(*hpriv->phys), GFP_KERNEL);
if (!hpriv->phys) {
--
2.35.1
In case if the platform doesn't have BIOS or a comprehensive firmware
installed then the HBA capability flags will be left uninitialized. As a
good alternative we can define a set AHCI DT-node properties to describe
all of HW-init capabilities flags. Luckily there aren't too many of them.
SSS - Staggered Spin-up support and MPS - Mechanical Presence Switch
support determine the corresponding feature availability for whole HBA by
means of the "hba-sss" and "hba-smps" properties. Each port can have the
"hba-{hpcp,mpsp,cpd,esp,fbscp}" defined indicatating that the port
supports the next functionality: HPCP - HotPlug capable port, MPSP -
Mechanical Presence Switch attached to a port, CPD - Cold Plug detection,
ESP - External SATA Port (eSATA), FBSCP - FIS-based switching capable
port.
Signed-off-by: Serge Semin <[email protected]>
---
Alternatively we could define them as a bitfield, but having a set of
boolean properties seemed a better idea since in that case we can
implement a simple inter-dependency rules for them, which can't be done
should we take the bitfields path.
---
.../devicetree/bindings/ata/ahci-common.yaml | 66 +++++++++++++++++++
.../bindings/ata/ahci-platform.yaml | 11 ++++
2 files changed, 77 insertions(+)
diff --git a/Documentation/devicetree/bindings/ata/ahci-common.yaml b/Documentation/devicetree/bindings/ata/ahci-common.yaml
index 70f915748270..371f5bd90639 100644
--- a/Documentation/devicetree/bindings/ata/ahci-common.yaml
+++ b/Documentation/devicetree/bindings/ata/ahci-common.yaml
@@ -75,6 +75,19 @@ properties:
phy-names:
const: sata-phy
+ hba-sss:
+ type: boolean
+ description:
+ Staggered Spin-up Support. Indicates whether the HBA supports the
+ staggered spin-up on its ports, for use in balancing power spikes.
+
+ hba-smps:
+ type: boolean
+ description:
+ Mechanical Presence Switch Support. Indicates whether the HBA supports
+ mechanical presence switches on its ports for use in hot plug
+ operations.
+
ports-implemented:
$ref: '/schemas/types.yaml#/definitions/uint32'
description:
@@ -97,6 +110,40 @@ patternProperties:
minimum: 0
maximum: 31
+ hba-hpcp:
+ type: boolean
+ description:
+ Hot Plug Capable Port. Indicates that this port’s signal and power
+ connectors are externally accessible via a joint signal and power
+ connector for blindmate device hot plug. It is mutually exclusive
+ with the ESP feature.
+
+ hba-mpsp:
+ type: boolean
+ description:
+ Mechanical Presence Switch Attached to Port. Indicates whether
+ the platform an mechanical presence switch attached to this
+ port.
+
+ hba-cpd:
+ type: boolean
+ description:
+ Cold Presence Detection. Indicates whether the platform supports
+ cold presence detection on this port.
+
+ hba-esp:
+ type: boolean
+ description:
+ External SATA Port. Indicates that this port’s signal connector
+ is externally accessible on a signal only connector (e.g. eSATA
+ connector).
+
+ hba-fbscp:
+ type: boolean
+ description:
+ FIS-based Switching Capable Port. Indicates whether this port
+ supports Port Multiplier FIS-based switching.
+
phys:
description: Individual AHCI SATA port PHY
maxItems: 1
@@ -111,6 +158,25 @@ patternProperties:
required:
- reg
+ # eSATA can't be enabled together with the HotPlug capability
+ oneOf:
+ - required:
+ - hba-hpcp
+ - required:
+ - hba-esp
+ - not:
+ anyOf:
+ - required:
+ - hba-hpcp
+ - required:
+ - hba-esp
+
+ # HotPlug capability must be enabled together with Cold Plug
+ # Detection and Mechanical Presence Switching.
+ dependencies:
+ hba-cpd: ["hba-hpcp"]
+ hba-mpsp: ["hba-hpcp"]
+
additionalProperties: true
required:
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.yaml b/Documentation/devicetree/bindings/ata/ahci-platform.yaml
index 76075d3c8987..6cad7e86f3bb 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.yaml
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.yaml
@@ -117,14 +117,25 @@ examples:
#address-cells = <1>;
#size-cells = <0>;
+ hba-smps;
+
sata0: sata-port@0 {
reg = <0>;
+
+ hba-fbscp;
+ hba-esp;
+
phys = <&sata_phy 0>;
target-supply = <®_sata0>;
};
sata1: sata-port@1 {
reg = <1>;
+
+ hba-fbscp;
+ hba-hpcp;
+ hba-mpsp;
+
phys = <&sata_phy 1>;
target-supply = <®_sata1>;
};
--
2.35.1
It's redundant to have the 'dma-coherent' property explicitly specified in
the DT schema because it's a generic property described in the core
DT-schema by which the property is always evaluated.
Signed-off-by: Serge Semin <[email protected]>
---
Changelog v2:
- This is a new patch created after rebasing v1 onto the 5.18-rc3 kernel.
---
Documentation/devicetree/bindings/ata/ahci-platform.yaml | 2 --
1 file changed, 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.yaml b/Documentation/devicetree/bindings/ata/ahci-platform.yaml
index c146ab8e14e5..9304e4731965 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.yaml
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.yaml
@@ -87,8 +87,6 @@ properties:
description:
regulator for AHCI controller
- dma-coherent: true
-
phy-supply:
description:
regulator for PHY power
--
2.35.1
Currently there are four port-map-related fields declared in the
ahci_host_priv structure and used to setup the HBA ports mapping. First
the ports-mapping is read from the PI register and immediately stored in
the saved_port_map field. If forced_port_map is initialized with non-zero
value then its value will have greater priority over the value read from
PI, thus it will override the saved_port_map field. That value will be
then masked by a non-zero mask_port_map field and after some sanity checks
it will be stored in the ahci_host_priv.port_map field as a final port
mapping.
As you can see the logic is a bit too complicated for such a simple task.
We can freely get rid from at least one of the fields with no change to
the implemented semantic. The force_port_map field can be replaced with
taking non-zero saved_port_map value into account. So if saved_port_map is
pre-initialized by the low level drivers (platform drivers) then it will
have greater priority over the value read from PI register and will be
used as actual HBA ports mapping later on. Thus the ports map forcing task
will be just transferred from the force_port_map to saved_port_map field.
This modification will perfectly fit into the feature of having OF-based
initialization of the HW-init HBA CSR fields we are about to introduce in
the next commit.
Signed-off-by: Serge Semin <[email protected]>
---
drivers/ata/ahci.c | 2 +-
drivers/ata/ahci.h | 1 -
drivers/ata/libahci.c | 10 ++++++----
drivers/ata/libahci_platform.c | 2 +-
4 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 397dfd27c90d..9bc8fa77e92f 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -656,7 +656,7 @@ static void ahci_pci_save_initial_config(struct pci_dev *pdev,
{
if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
dev_info(&pdev->dev, "JMB361 has only one port\n");
- hpriv->force_port_map = 1;
+ hpriv->saved_port_map = 1;
}
/*
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index f501531bd1b3..0e66446a5883 100644
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -327,7 +327,6 @@ struct ahci_port_priv {
struct ahci_host_priv {
/* Input fields */
unsigned int flags; /* AHCI_HFLAG_* */
- u32 force_port_map; /* force port map */
u32 mask_port_map; /* mask out particular bits */
void __iomem * mmio; /* bus-independent mem map */
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
index cf8c7fd59ada..000a7072614f 100644
--- a/drivers/ata/libahci.c
+++ b/drivers/ata/libahci.c
@@ -453,7 +453,6 @@ void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
* reset. Values without are used for driver operation.
*/
hpriv->saved_cap = cap = readl(mmio + HOST_CAP);
- hpriv->saved_port_map = port_map = readl(mmio + HOST_PORTS_IMPL);
/* CAP2 register is only defined for AHCI 1.2 and later */
vers = readl(mmio + HOST_VERSION);
@@ -517,10 +516,13 @@ void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
cap &= ~HOST_CAP_SXS;
}
- if (hpriv->force_port_map && port_map != hpriv->force_port_map) {
+ /* Override the HBA ports mapping if the platform needs it */
+ port_map = readl(mmio + HOST_PORTS_IMPL);
+ if (hpriv->saved_port_map && port_map != hpriv->saved_port_map) {
dev_info(dev, "forcing port_map 0x%x -> 0x%x\n",
- port_map, hpriv->force_port_map);
- port_map = hpriv->force_port_map;
+ port_map, hpriv->saved_port_map);
+ port_map = hpriv->saved_port_map;
+ } else {
hpriv->saved_port_map = port_map;
}
diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c
index f5ee2f9d014b..56aced7a76cd 100644
--- a/drivers/ata/libahci_platform.c
+++ b/drivers/ata/libahci_platform.c
@@ -553,7 +553,7 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev,
}
of_property_read_u32(dev->of_node,
- "ports-implemented", &hpriv->force_port_map);
+ "ports-implemented", &hpriv->saved_port_map);
if (child_nodes) {
for_each_child_of_node(dev->of_node, child) {
--
2.35.1
The ports-implemented property is mainly used on the OF-based platforms
with no ports mapping initialized by a bootloader/BIOS firmware. Seeing
the same of_property_read_u32()-based pattern has already been implemented
in the generic AHCI LLDD (glue) driver and in the Mediatek, St AHCI
drivers let's move the property read procedure to the generic
ahci_platform_get_resources() method. Thus we'll have the forced ports
mapping feature supported for each OF-based platform which requires that,
and stop re-implementing the same pattern in there a bit simplifying the
code.
Signed-off-by: Serge Semin <[email protected]>
---
drivers/ata/ahci_mtk.c | 2 --
drivers/ata/ahci_platform.c | 3 ---
drivers/ata/ahci_st.c | 3 ---
drivers/ata/libahci_platform.c | 3 +++
4 files changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/ata/ahci_mtk.c b/drivers/ata/ahci_mtk.c
index 1f6c85fde983..c056378e3e72 100644
--- a/drivers/ata/ahci_mtk.c
+++ b/drivers/ata/ahci_mtk.c
@@ -118,8 +118,6 @@ static int mtk_ahci_parse_property(struct ahci_host_priv *hpriv,
SYS_CFG_SATA_EN);
}
- of_property_read_u32(np, "ports-implemented", &hpriv->force_port_map);
-
return 0;
}
diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
index 28a8de5b48b9..9b56490ecbc3 100644
--- a/drivers/ata/ahci_platform.c
+++ b/drivers/ata/ahci_platform.c
@@ -56,9 +56,6 @@ static int ahci_probe(struct platform_device *pdev)
if (rc)
return rc;
- of_property_read_u32(dev->of_node,
- "ports-implemented", &hpriv->force_port_map);
-
if (of_device_is_compatible(dev->of_node, "hisilicon,hisi-ahci"))
hpriv->flags |= AHCI_HFLAG_NO_FBS | AHCI_HFLAG_NO_NCQ;
diff --git a/drivers/ata/ahci_st.c b/drivers/ata/ahci_st.c
index 7526653c843b..068621099c00 100644
--- a/drivers/ata/ahci_st.c
+++ b/drivers/ata/ahci_st.c
@@ -168,9 +168,6 @@ static int st_ahci_probe(struct platform_device *pdev)
st_ahci_configure_oob(hpriv->mmio);
- of_property_read_u32(dev->of_node,
- "ports-implemented", &hpriv->force_port_map);
-
err = ahci_platform_init_host(pdev, hpriv, &st_ahci_port_info,
&ahci_platform_sht);
if (err) {
diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c
index 4e54e19f07b2..f7f9cac10cb1 100644
--- a/drivers/ata/libahci_platform.c
+++ b/drivers/ata/libahci_platform.c
@@ -512,6 +512,9 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev,
goto err_out;
}
+ of_property_read_u32(dev->of_node,
+ "ports-implemented", &hpriv->force_port_map);
+
if (child_nodes) {
for_each_child_of_node(dev->of_node, child) {
u32 port;
--
2.35.1
Add myself as a maintainer of the new DWC AHCI SATA driver and
its DT-bindings schema.
Signed-off-by: Serge Semin <[email protected]>
---
Changelog v2:
- Use dlemoal/libata.git git tree for the LIBATA SATA AHCI SYNOPSYS
DWC driver (@Damien).
---
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 40fa1955ca3f..04f470519708 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11135,6 +11135,15 @@ F: drivers/ata/ahci_platform.c
F: drivers/ata/libahci_platform.c
F: include/linux/ahci_platform.h
+LIBATA SATA AHCI SYNOPSYS DWC CONTROLLER DRIVER
+M: Serge Semin <[email protected]>
+L: [email protected]
+S: Maintained
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/dlemoal/libata.git
+F: Documentation/devicetree/bindings/ata/baikal,bt1-ahci.yaml
+F: Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml
+F: drivers/ata/ahci_dwc.c
+
LIBATA SATA PROMISE TX2/TX4 CONTROLLER DRIVER
M: Mikael Pettersson <[email protected]>
L: [email protected]
--
2.35.1
It may get required to retrieve the port-base address even before the
ata_host instance is initialized and activated, for instance in the
ahci_save_initial_config() method which we about to update (consider this
modification as a preparation for that one). Seeing the __ahci_port_base()
function isn't used much it's the best candidate to provide the required
functionality. So let's convert it to accepting the ahci_host_priv
structure pointer.
Signed-off-by: Serge Semin <[email protected]>
---
drivers/ata/ahci.c | 2 +-
drivers/ata/ahci.h | 7 ++++---
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 9bc8fa77e92f..d14d74649e0e 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -689,7 +689,7 @@ static void ahci_pci_init_controller(struct ata_host *host)
mv = 2;
else
mv = 4;
- port_mmio = __ahci_port_base(host, mv);
+ port_mmio = __ahci_port_base(hpriv, mv);
writel(0, port_mmio + PORT_IRQ_MASK);
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index 0e66446a5883..8b9826533ae5 100644
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -431,10 +431,9 @@ int ahci_host_activate(struct ata_host *host, struct scsi_host_template *sht);
void ahci_error_handler(struct ata_port *ap);
u32 ahci_handle_port_intr(struct ata_host *host, u32 irq_masked);
-static inline void __iomem *__ahci_port_base(struct ata_host *host,
+static inline void __iomem *__ahci_port_base(struct ahci_host_priv *hpriv,
unsigned int port_no)
{
- struct ahci_host_priv *hpriv = host->private_data;
void __iomem *mmio = hpriv->mmio;
return mmio + 0x100 + (port_no * 0x80);
@@ -442,7 +441,9 @@ static inline void __iomem *__ahci_port_base(struct ata_host *host,
static inline void __iomem *ahci_port_base(struct ata_port *ap)
{
- return __ahci_port_base(ap->host, ap->port_no);
+ struct ahci_host_priv *hpriv = ap->host->private_data;
+
+ return __ahci_port_base(hpriv, ap->port_no);
}
static inline int ahci_nr_ports(u32 cap)
--
2.35.1
It's better for readability and maintainability to explicitly assign an
error number to the variable used then as a return value from the method
on the cleanup-on-error path. So adding new code in the method we won't
have to think whether the overridden rc-variable is set afterward in case
of an error. Saving one line of code doesn't worth it especially seeing
the rest of the ahci_platform_get_resources() function errors handling
blocks do explicitly write errno to rc.
Signed-off-by: Serge Semin <[email protected]>
---
Changelog v2:
- Drop rc variable initialization (@Damien)
---
drivers/ata/libahci_platform.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/ata/libahci_platform.c b/drivers/ata/libahci_platform.c
index 32495ae96567..f7f9bfcfc164 100644
--- a/drivers/ata/libahci_platform.c
+++ b/drivers/ata/libahci_platform.c
@@ -389,7 +389,7 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev,
struct ahci_host_priv *hpriv;
struct clk *clk;
struct device_node *child;
- int i, enabled_ports = 0, rc = -ENOMEM, child_nodes;
+ int i, enabled_ports = 0, rc, child_nodes;
u32 mask_port_map = 0;
if (!devres_open_group(dev, NULL, GFP_KERNEL))
@@ -397,8 +397,10 @@ struct ahci_host_priv *ahci_platform_get_resources(struct platform_device *pdev,
hpriv = devres_alloc(ahci_platform_put_resources, sizeof(*hpriv),
GFP_KERNEL);
- if (!hpriv)
+ if (!hpriv) {
+ rc = -ENOMEM;
goto err_out;
+ }
devres_add(dev, hpriv);
--
2.35.1
There is no point in reading the AHCI version all over in the tail of the
ahci_save_initial_config() method. That register is RO and doesn't change
its value even after reset. So just reuse the data, which has already been
read from there earlier in the head of the function.
Signed-off-by: Serge Semin <[email protected]>
---
drivers/ata/libahci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
index 000a7072614f..1ffaa5f5f21a 100644
--- a/drivers/ata/libahci.c
+++ b/drivers/ata/libahci.c
@@ -564,7 +564,7 @@ void ahci_save_initial_config(struct device *dev, struct ahci_host_priv *hpriv)
/* record values to use during operation */
hpriv->cap = cap;
hpriv->cap2 = cap2;
- hpriv->version = readl(mmio + HOST_VERSION);
+ hpriv->version = vers;
hpriv->port_map = port_map;
if (!hpriv->start_engine)
--
2.35.1
Synopsys AHCI SATA controller can work pretty under with the generic
AHCI-platform driver control. But there are vendor-specific peculiarities
which can tune the device performance up and which may need to be fixed up
for proper device functioning. In addition some DWC AHCI-based controllers
may require small platform-specific fixups, so adding them in the generic
AHCI driver would have ruined the code simplicity. Shortly speaking in
order to keep the generic AHCI-platform code clean and have DWC AHCI
SATA-specific features supported we suggest to add a dedicated DWC AHCI
SATA device driver. Aside with the standard AHCI-platform resources
getting, enabling/disabling and the controller registration the new driver
performs the next actions.
First of all there is a way to verify whether the HBA/ports capabilities
activated in OF are correct. Almost all features availability is reflected
in the vendor-specific parameters registers. So the DWC AHCI driver does
the capabilities sanity check based on the corresponding fields state.
Secondly if either the Command Completion Coalescing or the Device Sleep
feature is enabled the DWC AHCI-specific internal 1ms timer must be fixed
in accordance with the application clock signal frequency. In particular
the timer value must be set to be Fapp * 1000. Normally the SoC designers
pre-configure the TIMER1MS register to contain a correct value by default.
But the platforms can support the application clock rate change. If that
happens the 1ms timer value must be accordingly updated otherwise the
dependent features won't work as expected. In the DWC AHCI driver we
suggest to rely on the "aclk" reference clock rate to set the timer
interval up. That clock source is supposed to be the AHCI SATA application
clock in accordance with the DT bindings.
Finally DWC AHCI SATA controller AXI/AHB bus DMA-engine can be tuned up to
transfer up to 1024 * FIFO words at a time by setting the Tx/Rx
transaction size in the DMA control register. The maximum value depends on
the DMA data bus and AXI/AHB bus maximum burst length. In most of the
cases it's better to set the maximum possible value to reach the best AHCI
SATA controller performance. But sometimes in order to improve the system
interconnect responsiveness, transferring in smaller data chunks may be
more preferable. For such cases and for the case when the default value
doesn't provide the best DMA bus performance we suggest to use the new
HBA-port specific DT-properties "snps,{tx,rx}-ts-max" to tune the DMA
transactions size up.
After all the settings denoted above are handled the DWC AHCI SATA driver
proceeds further with the standard AHCI-platform host initializations.
Note since DWC AHCI controller is now have a dedicated driver we can
discard the corresponding compatible string from the ahci-platform.c
module. The same concerns "snps,spear-ahci" compatible string, which is
also based on the DWC AHCI IP-core.
Signed-off-by: Serge Semin <[email protected]>
---
Note there are three more AHCI SATA drivers which have been created for
the devices based on the DWC AHCI SATA IP-core. It's AHCI SunXi, St and
iMX drivers. Mostly they don't support the features implemented in this
driver. So hopefully sometime in future they can be converted to be based
on the generic DWC AHCI SATA driver and just perform some
subvendor-specific setups in their own LLDD (glue) driver code. But for
now let's leave the generic DWC AHCI SATA code as is. Hopefully the new
DWC AHCI-based device drivers will try at least to re-use a part of the
DWC AHCI driver methods if not being able to be integrated in the generic
DWC driver code.
Changelog v2:
- Change the local objects prefix from 'dwc_ahci_' to 'ahci_dwc_'.
(@Damien)
---
drivers/ata/Kconfig | 10 +
drivers/ata/Makefile | 1 +
drivers/ata/ahci_dwc.c | 395 ++++++++++++++++++++++++++++++++++++
drivers/ata/ahci_platform.c | 2 -
4 files changed, 406 insertions(+), 2 deletions(-)
create mode 100644 drivers/ata/ahci_dwc.c
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index bb45a9c00514..95e0e022b5bb 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -176,6 +176,16 @@ config AHCI_DM816
If unsure, say N.
+config AHCI_DWC
+ tristate "Synopsys DWC AHCI SATA support"
+ select SATA_HOST
+ default SATA_AHCI_PLATFORM
+ help
+ This option enables support for the Synopsys DWC AHCI SATA
+ controller implementation.
+
+ If unsure, say N.
+
config AHCI_ST
tristate "ST AHCI SATA support"
depends on ARCH_STI
diff --git a/drivers/ata/Makefile b/drivers/ata/Makefile
index b8aebfb14e82..34623365d9a6 100644
--- a/drivers/ata/Makefile
+++ b/drivers/ata/Makefile
@@ -17,6 +17,7 @@ obj-$(CONFIG_AHCI_BRCM) += ahci_brcm.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_CEVA) += ahci_ceva.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_DA850) += ahci_da850.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_DM816) += ahci_dm816.o libahci.o libahci_platform.o
+obj-$(CONFIG_AHCI_DWC) += ahci_dwc.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_IMX) += ahci_imx.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_MTK) += ahci_mtk.o libahci.o libahci_platform.o
obj-$(CONFIG_AHCI_MVEBU) += ahci_mvebu.o libahci.o libahci_platform.o
diff --git a/drivers/ata/ahci_dwc.c b/drivers/ata/ahci_dwc.c
new file mode 100644
index 000000000000..73380aaaebab
--- /dev/null
+++ b/drivers/ata/ahci_dwc.c
@@ -0,0 +1,395 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * DWC AHCI SATA Platform driver
+ *
+ * Copyright (C) 2021 BAIKAL ELECTRONICS, JSC
+ */
+
+#include <linux/ahci_platform.h>
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/libata.h>
+#include <linux/log2.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+
+#include "ahci.h"
+
+#define DRV_NAME "ahci-dwc"
+
+#define AHCI_DWC_FBS_PMPN_MAX 15
+
+/* DWC AHCI SATA controller specific registers */
+#define AHCI_DWC_HOST_OOBR 0xbc
+#define AHCI_DWC_HOST_OOB_WE BIT(31)
+#define AHCI_DWC_HOST_CWMIN_MASK GENMASK(30, 24)
+#define AHCI_DWC_HOST_CWMAX_MASK GENMASK(23, 16)
+#define AHCI_DWC_HOST_CIMIN_MASK GENMASK(15, 8)
+#define AHCI_DWC_HOST_CIMAX_MASK GENMASK(7, 0)
+
+#define AHCI_DWC_HOST_GPCR 0xd0
+#define AHCI_DWC_HOST_GPSR 0xd4
+
+#define AHCI_DWC_HOST_TIMER1MS 0xe0
+#define AHCI_DWC_HOST_TIMV_MASK GENMASK(19, 0)
+
+#define AHCI_DWC_HOST_GPARAM1R 0xe8
+#define AHCI_DWC_HOST_ALIGN_M BIT(31)
+#define AHCI_DWC_HOST_RX_BUFFER BIT(30)
+#define AHCI_DWC_HOST_PHY_DATA_MASK GENMASK(29, 28)
+#define AHCI_DWC_HOST_PHY_RST BIT(27)
+#define AHCI_DWC_HOST_PHY_CTRL_MASK GENMASK(26, 21)
+#define AHCI_DWC_HOST_PHY_STAT_MASK GENMASK(20, 15)
+#define AHCI_DWC_HOST_LATCH_M BIT(14)
+#define AHCI_DWC_HOST_PHY_TYPE_MASK GENMASK(13, 11)
+#define AHCI_DWC_HOST_RET_ERR BIT(10)
+#define AHCI_DWC_HOST_AHB_ENDIAN_MASK GENMASK(9, 8)
+#define AHCI_DWC_HOST_S_HADDR BIT(7)
+#define AHCI_DWC_HOST_M_HADDR BIT(6)
+#define AHCI_DWC_HOST_S_HDATA_MASK GENMASK(5, 3)
+#define AHCI_DWC_HOST_M_HDATA_MASK GENMASK(2, 0)
+
+#define AHCI_DWC_HOST_GPARAM2R 0xec
+#define AHCI_DWC_HOST_FBS_MEM_S BIT(19)
+#define AHCI_DWC_HOST_FBS_PMPN_MASK GENMASK(17, 16)
+#define AHCI_DWC_HOST_FBS_SUP BIT(15)
+#define AHCI_DWC_HOST_DEV_CP BIT(14)
+#define AHCI_DWC_HOST_DEV_MP BIT(13)
+#define AHCI_DWC_HOST_ENCODE_M BIT(12)
+#define AHCI_DWC_HOST_RXOOB_CLK_M BIT(11)
+#define AHCI_DWC_HOST_RXOOB_M BIT(10)
+#define AHCI_DWC_HOST_TXOOB_M BIT(9)
+#define AHCI_DWC_HOST_RXOOB_M BIT(10)
+#define AHCI_DWC_HOST_RXOOB_CLK_MASK GENMASK(8, 0)
+
+#define AHCI_DWC_HOST_PPARAMR 0xf0
+#define AHCI_DWC_HOST_TX_MEM_M BIT(11)
+#define AHCI_DWC_HOST_TX_MEM_S BIT(10)
+#define AHCI_DWC_HOST_RX_MEM_M BIT(9)
+#define AHCI_DWC_HOST_RX_MEM_S BIT(8)
+#define AHCI_DWC_HOST_TXFIFO_DEPTH GENMASK(7, 4)
+#define AHCI_DWC_HOST_RXFIFO_DEPTH GENMASK(3, 0)
+
+#define AHCI_DWC_HOST_TESTR 0xf4
+#define AHCI_DWC_HOST_PSEL_MASK GENMASK(18, 16)
+#define AHCI_DWC_HOST_TEST_IF BIT(0)
+
+#define AHCI_DWC_HOST_VERSIONR 0xf8
+#define AHCI_DWC_HOST_IDR 0xfc
+
+#define AHCI_DWC_PORT_DMACR 0x70
+#define AHCI_DWC_PORT_RXABL_MASK GENMASK(15, 12)
+#define AHCI_DWC_PORT_TXABL_MASK GENMASK(11, 8)
+#define AHCI_DWC_PORT_RXTS_MASK GENMASK(7, 4)
+#define AHCI_DWC_PORT_TXTS_MASK GENMASK(3, 0)
+#define AHCI_DWC_PORT_PHYCR 0x74
+#define AHCI_DWC_PORT_PHYSR 0x78
+
+struct ahci_dwc_host_priv {
+ struct platform_device *pdev;
+
+ u32 timv;
+ u32 dmacr[AHCI_MAX_PORTS];
+};
+
+static struct ahci_host_priv *ahci_dwc_get_resources(struct platform_device *pdev)
+{
+ struct ahci_dwc_host_priv *dpriv;
+ struct ahci_host_priv *hpriv;
+
+ dpriv = devm_kzalloc(&pdev->dev, sizeof(*dpriv), GFP_KERNEL);
+ if (!dpriv)
+ return ERR_PTR(-ENOMEM);
+
+ dpriv->pdev = pdev;
+
+ hpriv = ahci_platform_get_resources(pdev, AHCI_PLATFORM_GET_RESETS);
+ if (IS_ERR(hpriv))
+ return hpriv;
+
+ hpriv->plat_data = (void *)dpriv;
+
+ return hpriv;
+}
+
+static void ahci_dwc_check_cap(struct ahci_host_priv *hpriv)
+{
+ unsigned long port_map = hpriv->saved_port_map | hpriv->mask_port_map;
+ struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;
+ bool dev_mp, dev_cp, fbs_sup;
+ unsigned int fbs_pmp;
+ u32 param;
+ int i;
+
+ param = readl(hpriv->mmio + AHCI_DWC_HOST_GPARAM2R);
+ dev_mp = !!(param & AHCI_DWC_HOST_DEV_MP);
+ dev_cp = !!(param & AHCI_DWC_HOST_DEV_CP);
+ fbs_sup = !!(param & AHCI_DWC_HOST_FBS_SUP);
+ fbs_pmp = 5 * FIELD_GET(AHCI_DWC_HOST_FBS_PMPN_MASK, param);
+
+ if (!dev_mp && hpriv->saved_cap & HOST_CAP_MPS) {
+ dev_warn(&dpriv->pdev->dev, "MPS is unsupported\n");
+ hpriv->saved_cap &= ~HOST_CAP_MPS;
+ }
+
+
+ if (fbs_sup && fbs_pmp < AHCI_DWC_FBS_PMPN_MAX) {
+ dev_warn(&dpriv->pdev->dev, "PMPn is limited up to %u ports\n",
+ fbs_pmp);
+ }
+
+ for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {
+ if (!dev_mp && hpriv->saved_port_cap[i] & PORT_CMD_MPSP) {
+ dev_warn(&dpriv->pdev->dev, "MPS incapable port %d\n", i);
+ hpriv->saved_port_cap[i] &= ~PORT_CMD_MPSP;
+ }
+
+ if (!dev_cp && hpriv->saved_port_cap[i] & PORT_CMD_CPD) {
+ dev_warn(&dpriv->pdev->dev, "CPD incapable port %d\n", i);
+ hpriv->saved_port_cap[i] &= ~PORT_CMD_CPD;
+ }
+
+ if (!fbs_sup && hpriv->saved_port_cap[i] & PORT_CMD_FBSCP) {
+ dev_warn(&dpriv->pdev->dev, "FBS incapable port %d\n", i);
+ hpriv->saved_port_cap[i] &= ~PORT_CMD_FBSCP;
+ }
+ }
+}
+
+static void ahci_dwc_init_timer(struct ahci_host_priv *hpriv)
+{
+ struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;
+ unsigned long rate;
+ struct clk *aclk;
+ u32 cap, cap2;
+
+ /* 1ms tick is generated only for the CCC or DevSleep features */
+ cap = readl(hpriv->mmio + HOST_CAP);
+ cap2 = readl(hpriv->mmio + HOST_CAP2);
+ if (!(cap & HOST_CAP_CCC) && !(cap2 & HOST_CAP2_SDS))
+ return;
+
+ /*
+ * Tick is generated based on the AXI/AHB application clocks signal
+ * so we need to be sure in the clock we are going to use.
+ */
+ aclk = ahci_platform_find_clk(hpriv, "aclk");
+ if (!aclk)
+ return;
+
+ /* 1ms timer interval is set as TIMV = AMBA_FREQ[MHZ] * 1000 */
+ dpriv->timv = readl(hpriv->mmio + AHCI_DWC_HOST_TIMER1MS);
+ dpriv->timv = FIELD_GET(AHCI_DWC_HOST_TIMV_MASK, dpriv->timv);
+ rate = clk_get_rate(aclk) / 1000UL;
+ if (rate == dpriv->timv)
+ return;
+
+ dev_info(&dpriv->pdev->dev, "Update CCC/DevSlp timer for Fapp %lu MHz\n",
+ rate / 1000UL);
+ dpriv->timv = FIELD_PREP(AHCI_DWC_HOST_TIMV_MASK, rate);
+ writel(dpriv->timv, hpriv->mmio + AHCI_DWC_HOST_TIMER1MS);
+}
+
+static int ahci_dwc_init_dmacr(struct ahci_host_priv *hpriv)
+{
+ struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;
+ struct device_node *child;
+ void __iomem *port_mmio;
+ u32 port, dmacr, ts;
+
+ /*
+ * Update the DMA Tx/Rx transaction sizes in accordance with the
+ * platform setup. Note values exceeding maximal or minimal limits will
+ * be automatically clamped. Also note the register isn't affected by
+ * the HBA global reset so we can freely initialize it once until the
+ * next system reset.
+ */
+ for_each_child_of_node(dpriv->pdev->dev.of_node, child) {
+ if (!of_device_is_available(child))
+ continue;
+
+ if (of_property_read_u32(child, "reg", &port)) {
+ of_node_put(child);
+ return -EINVAL;
+ }
+
+ port_mmio = __ahci_port_base(hpriv, port);
+ dmacr = readl(port_mmio + AHCI_DWC_PORT_DMACR);
+
+ if (!of_property_read_u32(child, "snps,tx-ts-max", &ts)) {
+ ts = ilog2(ts);
+ dmacr &= ~AHCI_DWC_PORT_TXTS_MASK;
+ dmacr |= FIELD_PREP(AHCI_DWC_PORT_TXTS_MASK, ts);
+ }
+
+ if (!of_property_read_u32(child, "snps,rx-ts-max", &ts)) {
+ ts = ilog2(ts);
+ dmacr &= ~AHCI_DWC_PORT_RXTS_MASK;
+ dmacr |= FIELD_PREP(AHCI_DWC_PORT_RXTS_MASK, ts);
+ }
+
+ writel(dmacr, port_mmio + AHCI_DWC_PORT_DMACR);
+ dpriv->dmacr[port] = dmacr;
+ }
+
+ return 0;
+}
+
+static int ahci_dwc_init_host(struct ahci_host_priv *hpriv)
+{
+ int rc;
+
+ rc = ahci_platform_enable_resources(hpriv);
+ if (rc)
+ return rc;
+
+ ahci_dwc_check_cap(hpriv);
+
+ ahci_dwc_init_timer(hpriv);
+
+ rc = ahci_dwc_init_dmacr(hpriv);
+ if (rc)
+ goto err_disable_resources;
+
+ return 0;
+
+err_disable_resources:
+ ahci_platform_disable_resources(hpriv);
+
+ return rc;
+}
+
+static int ahci_dwc_reinit_host(struct ahci_host_priv *hpriv)
+{
+ struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;
+ unsigned long port_map = hpriv->port_map;
+ void __iomem *port_mmio;
+ int i, rc;
+
+ rc = ahci_platform_enable_resources(hpriv);
+ if (rc)
+ return rc;
+
+ writel(dpriv->timv, hpriv->mmio + AHCI_DWC_HOST_TIMER1MS);
+
+ for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {
+ port_mmio = __ahci_port_base(hpriv, i);
+ writel(dpriv->dmacr[i], port_mmio + AHCI_DWC_PORT_DMACR);
+ }
+
+ return 0;
+}
+
+static void ahci_dwc_clear_host(struct ahci_host_priv *hpriv)
+{
+ ahci_platform_disable_resources(hpriv);
+}
+
+static void ahci_dwc_stop_host(struct ata_host *host)
+{
+ struct ahci_host_priv *hpriv = host->private_data;
+
+ ahci_dwc_clear_host(hpriv);
+}
+
+static struct ata_port_operations ahci_dwc_port_ops = {
+ .inherits = &ahci_platform_ops,
+ .host_stop = ahci_dwc_stop_host,
+};
+
+static const struct ata_port_info ahci_dwc_port_info = {
+ .flags = AHCI_FLAG_COMMON,
+ .pio_mask = ATA_PIO4,
+ .udma_mask = ATA_UDMA6,
+ .port_ops = &ahci_dwc_port_ops,
+};
+
+static struct scsi_host_template ahci_dwc_scsi_info = {
+ AHCI_SHT(DRV_NAME),
+};
+
+static int ahci_dwc_probe(struct platform_device *pdev)
+{
+ struct ahci_host_priv *hpriv;
+ int rc;
+
+ hpriv = ahci_dwc_get_resources(pdev);
+ if (IS_ERR(hpriv))
+ return PTR_ERR(hpriv);
+
+ rc = ahci_dwc_init_host(hpriv);
+ if (rc)
+ return rc;
+
+ rc = ahci_platform_init_host(pdev, hpriv, &ahci_dwc_port_info,
+ &ahci_dwc_scsi_info);
+ if (rc)
+ goto err_clear_host;
+
+ return 0;
+
+err_clear_host:
+ ahci_dwc_clear_host(hpriv);
+
+ return rc;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int ahci_dwc_suspend(struct device *dev)
+{
+ struct ata_host *host = dev_get_drvdata(dev);
+ struct ahci_host_priv *hpriv = host->private_data;
+ int rc;
+
+ rc = ahci_platform_suspend_host(dev);
+ if (rc)
+ return rc;
+
+ ahci_dwc_clear_host(hpriv);
+
+ return 0;
+}
+
+static int ahci_dwc_resume(struct device *dev)
+{
+ struct ata_host *host = dev_get_drvdata(dev);
+ struct ahci_host_priv *hpriv = host->private_data;
+ int rc;
+
+ rc = ahci_dwc_reinit_host(hpriv);
+ if (rc)
+ return rc;
+
+ return ahci_platform_resume_host(dev);
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(ahci_dwc_pm_ops, ahci_dwc_suspend, ahci_dwc_resume);
+
+static const struct of_device_id ahci_dwc_of_match[] = {
+ { .compatible = "snps,dwc-ahci", },
+ { .compatible = "snps,spear-ahci", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ahci_dwc_of_match);
+
+static struct platform_driver ahci_dwc_driver = {
+ .probe = ahci_dwc_probe,
+ .remove = ata_platform_remove_one,
+ .shutdown = ahci_platform_shutdown,
+ .driver = {
+ .name = DRV_NAME,
+ .of_match_table = ahci_dwc_of_match,
+ .pm = &ahci_dwc_pm_ops,
+ },
+};
+module_platform_driver(ahci_dwc_driver);
+
+MODULE_DESCRIPTION("DWC AHCI SATA platform driver");
+MODULE_AUTHOR("Serge Semin <[email protected]>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/ata/ahci_platform.c b/drivers/ata/ahci_platform.c
index 9b56490ecbc3..8f5572a9f8f1 100644
--- a/drivers/ata/ahci_platform.c
+++ b/drivers/ata/ahci_platform.c
@@ -80,9 +80,7 @@ static SIMPLE_DEV_PM_OPS(ahci_pm_ops, ahci_platform_suspend,
static const struct of_device_id ahci_of_match[] = {
{ .compatible = "generic-ahci", },
/* Keep the following compatibles for device tree compatibility */
- { .compatible = "snps,spear-ahci", },
{ .compatible = "ibm,476gtr-ahci", },
- { .compatible = "snps,dwc-ahci", },
{ .compatible = "hisilicon,hisi-ahci", },
{ .compatible = "cavium,octeon-7130-ahci", },
{ /* sentinel */ }
--
2.35.1
Synopsys AHCI SATA controller is mainly compatible with the generic AHCI
SATA controller except a few peculiarities and the platform environment
requirements. In particular it can have one or two reference clocks to
feed up its AXI/AHB interface and SATA PHYs domain and at least one reset
control for the application clock domain. In addition to that the DMA
interface of each port can be tuned up to work with the predefined maximum
data chunk size. Note unlike generic AHCI controller DWC AHCI can't have
more than 8 ports. All of that is reflected in the new DWC AHCI SATA
device DT binding.
Note the DWC AHCI SATA controller DT-schema has been created in a way so
to be reused for the vendor-specific DT-schemas (see for example the
"snps,dwc-ahci" compatible string binding). One of which we are about to
introduce.
Signed-off-by: Serge Semin <[email protected]>
---
Changelog v2:
- Replace min/max constraints of the snps,{tx,rx}-ts-max property with
enum [ 1, 2, 4, ..., 1024 ]. (@Rob)
---
.../bindings/ata/ahci-platform.yaml | 8 --
.../bindings/ata/snps,dwc-ahci.yaml | 123 ++++++++++++++++++
2 files changed, 123 insertions(+), 8 deletions(-)
create mode 100644 Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml
diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.yaml b/Documentation/devicetree/bindings/ata/ahci-platform.yaml
index 6cad7e86f3bb..4b65966ec23b 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.yaml
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.yaml
@@ -30,8 +30,6 @@ select:
- marvell,armada-3700-ahci
- marvell,armada-8k-ahci
- marvell,berlin2q-ahci
- - snps,dwc-ahci
- - snps,spear-ahci
required:
- compatible
@@ -48,17 +46,11 @@ properties:
- marvell,berlin2-ahci
- marvell,berlin2q-ahci
- const: generic-ahci
- - items:
- - enum:
- - rockchip,rk3568-dwc-ahci
- - const: snps,dwc-ahci
- enum:
- cavium,octeon-7130-ahci
- hisilicon,hisi-ahci
- ibm,476gtr-ahci
- marvell,armada-3700-ahci
- - snps,dwc-ahci
- - snps,spear-ahci
reg:
minItems: 1
diff --git a/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml b/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml
new file mode 100644
index 000000000000..a13fd77a451f
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml
@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Synopsys DWC AHCI SATA controller
+
+maintainers:
+ - Serge Semin <[email protected]>
+
+description:
+ This document defines device tree bindings for the Synopsys DWC
+ implementation of the AHCI SATA controller.
+
+allOf:
+ - $ref: ahci-common.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - description: Synopsys AHCI SATA-compatible devices
+ contains:
+ const: snps,dwc-ahci
+ - description: SPEAr1340 AHCI SATA device
+ const: snps,spear-ahci
+ - description: Rockhip RK3568 ahci controller
+ const: rockchip,rk3568-dwc-ahci
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ description:
+ Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock
+ and embedded PHYs reference clock together with vendor-specific set
+ of clocks.
+ minItems: 1
+ maxItems: 4
+
+ clock-names:
+ contains:
+ anyOf:
+ - description: Application AXI/AHB BIU clock source
+ enum:
+ - aclk
+ - sata
+ - description: SATA Ports reference clock
+ enum:
+ - ref
+ - sata_ref
+
+ resets:
+ description:
+ At least basic core and application clock domains reset is normally
+ supported by the DWC AHCI SATA controller. Some platform specific
+ clocks can be also specified though.
+
+ reset-names:
+ contains:
+ description: Core and application clock domains reset control
+ const: arst
+
+patternProperties:
+ "^sata-port@[0-9a-e]$":
+ type: object
+
+ properties:
+ reg:
+ minimum: 0
+ maximum: 7
+
+ snps,tx-ts-max:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Maximal size of Tx DMA transactions in FIFO words
+ enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ]
+
+ snps,rx-ts-max:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: Maximal size of Rx DMA transactions in FIFO words
+ enum: [ 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024 ]
+
+ additionalProperties: true
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ sata@122f0000 {
+ compatible = "snps,dwc-ahci";
+ reg = <0x122F0000 0x1ff>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&clock1>, <&clock2>;
+ clock-names = "aclk", "ref";
+
+ phys = <&sata_phy>;
+ phy-names = "sata-phy";
+
+ ports-implemented = <0x1>;
+
+ sata-port@0 {
+ reg = <0>;
+
+ hba-fbscp;
+ snps,tx-ts-max = <512>;
+ snps,rx-ts-max = <512>;
+ };
+ };
+...
--
2.35.1
Baikal-T1 AHCI controller is based on the DWC AHCI SATA IP-core v4.10a
with the next specific settings: two SATA ports, cascaded CSR access based
on two clock domains (APB and AXI), selectable source of the reference
clock (though stable work is currently available from the external source
only), two reset lanes for the application and SATA ports domains. Other
than that the device is fully compatible with the generic DWC AHCI SATA
bindings.
Signed-off-by: Serge Semin <[email protected]>
---
Changelog v2:
- Rename 'syscon' property to 'baikal,bt1-syscon'.
- Drop macro usage from the example node.
---
.../bindings/ata/baikal,bt1-ahci.yaml | 127 ++++++++++++++++++
1 file changed, 127 insertions(+)
create mode 100644 Documentation/devicetree/bindings/ata/baikal,bt1-ahci.yaml
diff --git a/Documentation/devicetree/bindings/ata/baikal,bt1-ahci.yaml b/Documentation/devicetree/bindings/ata/baikal,bt1-ahci.yaml
new file mode 100644
index 000000000000..7c2eae75434f
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/baikal,bt1-ahci.yaml
@@ -0,0 +1,127 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/ata/baikal,bt1-ahci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Baikal-T1 SoC AHCI SATA controller
+
+maintainers:
+ - Serge Semin <[email protected]>
+
+description: |
+ AHCI SATA controller embedded into the Baikal-T1 SoC is based on the
+ DWC AHCI SATA v4.10a IP-core.
+
+allOf:
+ - $ref: snps,dwc-ahci.yaml#
+
+properties:
+ compatible:
+ contains:
+ const: baikal,bt1-ahci
+
+ clocks:
+ items:
+ - description: Peripheral APB bus clock source
+ - description: Application AXI BIU clock
+ - description: Internal SATA Ports reference clock
+ - description: External SATA Ports reference clock
+
+ clock-names:
+ items:
+ - const: pclk
+ - const: aclk
+ - const: ref_int
+ - const: ref_ext
+
+ resets:
+ items:
+ - description: Application AXI BIU domain reset
+ - description: SATA Ports clock domain reset
+
+ reset-names:
+ items:
+ - const: arst
+ - const: ref
+
+ baikal,bt1-syscon:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle reference to the CCU system controller. It is required to
+ switch between internal and external SATA reference clock sources.
+
+ ports-implemented:
+ maximum: 0x3
+
+patternProperties:
+ "^sata-port@[0-9a-e]$":
+ type: object
+
+ properties:
+ reg:
+ minimum: 0
+ maximum: 1
+
+ snps,tx-ts-max:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Due to having AXI3 bus interface utilized the maximum Tx DMA
+ transaction size can't exceed 16 beats (AxLEN[3:0]).
+ minimum: 1
+ maximum: 16
+
+ snps,rx-ts-max:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Due to having AXI3 bus interface utilized the maximum Rx DMA
+ transaction size can't exceed 16 beats (AxLEN[3:0]).
+ minimum: 1
+ maximum: 16
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - resets
+ - baikal,bt1-syscon
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ sata@1f050000 {
+ compatible = "baikal,bt1-ahci", "snps,dwc-ahci";
+ reg = <0x1f050000 0x2000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ interrupts = <0 64 4>;
+
+ clocks = <&ccu_sys 1>, <&ccu_axi 2>, <&ccu_sys 0>, <&clk_sata>;
+ clock-names = "pclk", "aclk", "ref_int", "ref_ext";
+
+ resets = <&ccu_axi 2>, <&ccu_sys 0>;
+ reset-names = "arst", "ref";
+
+ baikal,bt1-syscon = <&syscon>;
+
+ ports-implemented = <0x3>;
+
+ sata-port@0 {
+ reg = <0>;
+
+ snps,tx-ts-max = <4>;
+ snps,rx-ts-max = <4>;
+ };
+
+ sata-port@1 {
+ reg = <1>;
+
+ snps,tx-ts-max = <4>;
+ snps,rx-ts-max = <4>;
+ };
+ };
+...
--
2.35.1
Some DWC AHCI SATA IP-core derivatives require to perform small platform
or IP-core specific setups. They are too small to be placed in a dedicated
driver. It's just much easier to have a set of quirks for them right in
the DWC AHCI driver code. Since we are about to add such platform support,
as a pre-requisite we introduce a platform-data based DWC AHCI quirks API.
The platform data can be used to define the flags passed to the
ahci_platform_get_resources() method, additional AHCI host-flags and a set
of callbacks to initialize, re-initialize and clear the platform settings.
Signed-off-by: Serge Semin <[email protected]>
---
Changelog v2:
- Change the local objects prefix from 'dwc_ahci_' to 'ahci_dwc_'.
(@Damien)
---
drivers/ata/ahci_dwc.c | 52 ++++++++++++++++++++++++++++++++++++++----
1 file changed, 48 insertions(+), 4 deletions(-)
diff --git a/drivers/ata/ahci_dwc.c b/drivers/ata/ahci_dwc.c
index 73380aaaebab..f987efa1ad59 100644
--- a/drivers/ata/ahci_dwc.c
+++ b/drivers/ata/ahci_dwc.c
@@ -90,7 +90,16 @@
#define AHCI_DWC_PORT_PHYCR 0x74
#define AHCI_DWC_PORT_PHYSR 0x78
+struct ahci_dwc_plat_data {
+ unsigned int pflags;
+ unsigned int hflags;
+ int (*init)(struct ahci_host_priv *hpriv);
+ int (*reinit)(struct ahci_host_priv *hpriv);
+ void (*clear)(struct ahci_host_priv *hpriv);
+};
+
struct ahci_dwc_host_priv {
+ const struct ahci_dwc_plat_data *pdata;
struct platform_device *pdev;
u32 timv;
@@ -107,11 +116,15 @@ static struct ahci_host_priv *ahci_dwc_get_resources(struct platform_device *pde
return ERR_PTR(-ENOMEM);
dpriv->pdev = pdev;
+ dpriv->pdata = device_get_match_data(&pdev->dev);
+ if (!dpriv->pdata)
+ return ERR_PTR(-EINVAL);
- hpriv = ahci_platform_get_resources(pdev, AHCI_PLATFORM_GET_RESETS);
+ hpriv = ahci_platform_get_resources(pdev, dpriv->pdata->pflags);
if (IS_ERR(hpriv))
return hpriv;
+ hpriv->flags |= dpriv->pdata->hflags;
hpriv->plat_data = (void *)dpriv;
return hpriv;
@@ -242,22 +255,33 @@ static int ahci_dwc_init_dmacr(struct ahci_host_priv *hpriv)
static int ahci_dwc_init_host(struct ahci_host_priv *hpriv)
{
+ struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;
int rc;
rc = ahci_platform_enable_resources(hpriv);
if (rc)
return rc;
+ if (dpriv->pdata->init) {
+ rc = dpriv->pdata->init(hpriv);
+ if (rc)
+ goto err_disable_resources;
+ }
+
ahci_dwc_check_cap(hpriv);
ahci_dwc_init_timer(hpriv);
rc = ahci_dwc_init_dmacr(hpriv);
if (rc)
- goto err_disable_resources;
+ goto err_clear_platform;
return 0;
+err_clear_platform:
+ if (dpriv->pdata->clear)
+ dpriv->pdata->clear(hpriv);
+
err_disable_resources:
ahci_platform_disable_resources(hpriv);
@@ -275,6 +299,12 @@ static int ahci_dwc_reinit_host(struct ahci_host_priv *hpriv)
if (rc)
return rc;
+ if (dpriv->pdata->reinit) {
+ rc = dpriv->pdata->reinit(hpriv);
+ if (rc)
+ goto err_disable_resources;
+ }
+
writel(dpriv->timv, hpriv->mmio + AHCI_DWC_HOST_TIMER1MS);
for_each_set_bit(i, &port_map, AHCI_MAX_PORTS) {
@@ -283,10 +313,20 @@ static int ahci_dwc_reinit_host(struct ahci_host_priv *hpriv)
}
return 0;
+
+err_disable_resources:
+ ahci_platform_disable_resources(hpriv);
+
+ return rc;
}
static void ahci_dwc_clear_host(struct ahci_host_priv *hpriv)
{
+ struct ahci_dwc_host_priv *dpriv = hpriv->plat_data;
+
+ if (dpriv->pdata->clear)
+ dpriv->pdata->clear(hpriv);
+
ahci_platform_disable_resources(hpriv);
}
@@ -371,9 +411,13 @@ static int ahci_dwc_resume(struct device *dev)
static SIMPLE_DEV_PM_OPS(ahci_dwc_pm_ops, ahci_dwc_suspend, ahci_dwc_resume);
+struct ahci_dwc_plat_data ahci_dwc_plat = {
+ .pflags = AHCI_PLATFORM_GET_RESETS,
+};
+
static const struct of_device_id ahci_dwc_of_match[] = {
- { .compatible = "snps,dwc-ahci", },
- { .compatible = "snps,spear-ahci", },
+ { .compatible = "snps,dwc-ahci", &ahci_dwc_plat },
+ { .compatible = "snps,spear-ahci", &ahci_dwc_plat },
{},
};
MODULE_DEVICE_TABLE(of, ahci_dwc_of_match);
--
2.35.1
Currently not all of the Port-specific capabilities listed in the
PORT_CMD-enumeration. Let's extend that set with the Cold Presence
Detection and Mechanical Presence Switch attached to the Port flags [1] so
to closeup the set of the platform-specific port-capabilities flags. Note
these flags are supposed to be set by the platform firmware if there is
one. Alternatively as we are about to do they can be set by means of the
OF properties.
While at it replace PORT_IRQ_DEV_ILCK with PORT_IRQ_DEV_MPS and fix the
comment there. In accordance with [2] that IRQ flag is supposed to
indicate the state of the signal coming from the Mechanical Presence
Switch.
[1] Serial ATA AHCI 1.3.1 Specification, p.27
[2] Serial ATA AHCI 1.3.1 Specification, p.7
Signed-off-by: Serge Semin <[email protected]>
---
drivers/ata/ahci.h | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index 7d834deefeb9..f501531bd1b3 100644
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -138,7 +138,7 @@ enum {
PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
- PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
+ PORT_IRQ_DMPS = (1 << 7), /* mechanical presence status */
PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
@@ -166,6 +166,8 @@ enum {
PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
PORT_CMD_FBSCP = (1 << 22), /* FBS Capable Port */
PORT_CMD_ESP = (1 << 21), /* External Sata Port */
+ PORT_CMD_CPD = (1 << 20), /* Cold Presence Detection */
+ PORT_CMD_MPSP = (1 << 19), /* Mechanical Presence Switch */
PORT_CMD_HPCP = (1 << 18), /* HotPlug Capable Port */
PORT_CMD_PMP = (1 << 17), /* PMP attached */
PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
@@ -181,6 +183,9 @@ enum {
PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
+ PORT_CMD_CAP = PORT_CMD_HPCP | PORT_CMD_MPSP |
+ PORT_CMD_CPD | PORT_CMD_ESP | PORT_CMD_FBSCP,
+
/* PORT_FBS bits */
PORT_FBS_DWE_OFFSET = 16, /* FBS device with error offset */
PORT_FBS_ADO_OFFSET = 12, /* FBS active dev optimization offset */
--
2.35.1