This series converts all the CoreSight debug bindings to DT schema
format. These bindings are at the top of the list of occurrences of
bindings without a schema. For arm64 dts files:
702 ['arm,coresight-etm4x', 'arm,primecell']
536 ['arm,coresight-cpu-debug', 'arm,primecell']
509 ['arm,coresight-dynamic-funnel', 'arm,primecell']
213 ['arm,coresight-tmc', 'arm,primecell']
143 ['arm,coresight-dynamic-replicator', 'arm,primecell']
97 ['arm,coresight-stm', 'arm,primecell']
I'll send a reply to these with the errors in dts files that this
causes. I've reviewed them and they all look legit. Xilinx Zynq though
has 3 clocks instead of 2.
v2:
- Rename other Coresight bindings to use compatible string for filename
- Add missing arm,coresight-dynamic-replicator.yaml and
arm,coresight-static-funnel.yaml
- Update MAINTAINERS
- Fix coresight.txt references
Rob
Rob Herring (3):
dt-bindings: arm: Rename Coresight filenames to match compatible
dt-bindings: arm: Convert CoreSight bindings to DT schema
dt-bindings: arm: Convert CoreSight CPU debug to DT schema
.../bindings/arm/arm,coresight-catu.yaml | 101 +++++
.../bindings/arm/arm,coresight-cpu-debug.yaml | 81 ++++
...esight-cti.yaml => arm,coresight-cti.yaml} | 5 +-
.../arm/arm,coresight-dynamic-funnel.yaml | 126 ++++++
.../arm/arm,coresight-dynamic-replicator.yaml | 126 ++++++
.../bindings/arm/arm,coresight-etb10.yaml | 92 ++++
.../bindings/arm/arm,coresight-etm.yaml | 156 +++++++
.../arm/arm,coresight-static-funnel.yaml | 89 ++++
.../arm/arm,coresight-static-replicator.yaml | 90 ++++
.../bindings/arm/arm,coresight-stm.yaml | 101 +++++
.../bindings/arm/arm,coresight-tmc.yaml | 131 ++++++
.../bindings/arm/arm,coresight-tpiu.yaml | 91 ++++
...yaml => arm,embedded-trace-extension.yaml} | 3 +-
...e.yaml => arm,trace-buffer-extension.yaml} | 2 +-
.../bindings/arm/coresight-cpu-debug.txt | 49 ---
.../devicetree/bindings/arm/coresight.txt | 402 ------------------
Documentation/trace/coresight/coresight.rst | 2 +-
MAINTAINERS | 8 +-
18 files changed, 1192 insertions(+), 463 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml
create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml
rename Documentation/devicetree/bindings/arm/{coresight-cti.yaml => arm,coresight-cti.yaml} (98%)
create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml
create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml
create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml
create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml
create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml
create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml
create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml
create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml
rename Documentation/devicetree/bindings/arm/{ete.yaml => arm,embedded-trace-extension.yaml} (95%)
rename Documentation/devicetree/bindings/arm/{trbe.yaml => arm,trace-buffer-extension.yaml} (94%)
delete mode 100644 Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
delete mode 100644 Documentation/devicetree/bindings/arm/coresight.txt
--
2.34.1
Use the compatible strings for filenames as that is the preferred naming
convention for DT bindings.
Signed-off-by: Rob Herring <[email protected]>
---
.../arm/{coresight-cti.yaml => arm,coresight-cti.yaml} | 2 +-
.../arm/{ete.yaml => arm,embedded-trace-extension.yaml} | 2 +-
.../arm/{trbe.yaml => arm,trace-buffer-extension.yaml} | 2 +-
MAINTAINERS | 6 +++---
4 files changed, 6 insertions(+), 6 deletions(-)
rename Documentation/devicetree/bindings/arm/{coresight-cti.yaml => arm,coresight-cti.yaml} (99%)
rename Documentation/devicetree/bindings/arm/{ete.yaml => arm,embedded-trace-extension.yaml} (96%)
rename Documentation/devicetree/bindings/arm/{trbe.yaml => arm,trace-buffer-extension.yaml} (94%)
diff --git a/Documentation/devicetree/bindings/arm/coresight-cti.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml
similarity index 99%
rename from Documentation/devicetree/bindings/arm/coresight-cti.yaml
rename to Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml
index 21e3515491f4..d32d214ed64e 100644
--- a/Documentation/devicetree/bindings/arm/coresight-cti.yaml
+++ b/Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml
@@ -2,7 +2,7 @@
# Copyright 2019 Linaro Ltd.
%YAML 1.2
---
-$id: http://devicetree.org/schemas/arm/coresight-cti.yaml#
+$id: http://devicetree.org/schemas/arm/arm,coresight-cti.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Coresight Cross Trigger Interface (CTI) device.
diff --git a/Documentation/devicetree/bindings/arm/ete.yaml b/Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml
similarity index 96%
rename from Documentation/devicetree/bindings/arm/ete.yaml
rename to Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml
index 7f9b2d1e1147..2415beeb12ea 100644
--- a/Documentation/devicetree/bindings/arm/ete.yaml
+++ b/Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml
@@ -2,7 +2,7 @@
# Copyright 2021, Arm Ltd
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/arm/ete.yaml#"
+$id: "http://devicetree.org/schemas/arm/arm,embedded-trace-extension.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: ARM Embedded Trace Extensions
diff --git a/Documentation/devicetree/bindings/arm/trbe.yaml b/Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml
similarity index 94%
rename from Documentation/devicetree/bindings/arm/trbe.yaml
rename to Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml
index 4402d7bfd1fc..b1322658063a 100644
--- a/Documentation/devicetree/bindings/arm/trbe.yaml
+++ b/Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml
@@ -2,7 +2,7 @@
# Copyright 2021, Arm Ltd
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/arm/trbe.yaml#"
+$id: "http://devicetree.org/schemas/arm/arm,trace-buffer-extension.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
title: ARM Trace Buffer Extensions
diff --git a/MAINTAINERS b/MAINTAINERS
index 7dff84d95e5f..abfdc62abf98 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1972,10 +1972,10 @@ S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git
F: Documentation/ABI/testing/sysfs-bus-coresight-devices-*
F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
-F: Documentation/devicetree/bindings/arm/coresight-cti.yaml
+F: Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml
F: Documentation/devicetree/bindings/arm/coresight.txt
-F: Documentation/devicetree/bindings/arm/ete.yaml
-F: Documentation/devicetree/bindings/arm/trbe.yaml
+F: Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml
+F: Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml
F: Documentation/trace/coresight/*
F: drivers/hwtracing/coresight/*
F: include/dt-bindings/arm/coresight-cti-dt.h
--
2.34.1
Convert the CoreSight CPU debug binding to DT schema format.
Reviewed-by: Leo Yan <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Signed-off-by: Rob Herring <[email protected]>
---
v2:
- Update MAINTAINERS entry
---
.../bindings/arm/arm,coresight-cpu-debug.yaml | 81 +++++++++++++++++++
.../bindings/arm/coresight-cpu-debug.txt | 49 -----------
MAINTAINERS | 1 -
3 files changed, 81 insertions(+), 50 deletions(-)
create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml
delete mode 100644 Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
diff --git a/Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml b/Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml
new file mode 100644
index 000000000000..0a6bc03ebe00
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/arm/arm,coresight-cpu-debug.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: CoreSight CPU Debug Component
+
+maintainers:
+ - Mathieu Poirier <[email protected]>
+ - Mike Leach <[email protected]>
+ - Leo Yan <[email protected]>
+ - Suzuki K Poulose <[email protected]>
+
+description: |
+ CoreSight CPU debug component are compliant with the ARMv8 architecture
+ reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
+ external debug module is mainly used for two modes: self-hosted debug and
+ external debug, and it can be accessed from mmio region from Coresight and
+ eventually the debug module connects with CPU for debugging. And the debug
+ module provides sample-based profiling extension, which can be used to sample
+ CPU program counter, secure state and exception level, etc; usually every CPU
+ has one dedicated debug module to be connected.
+
+select:
+ properties:
+ compatible:
+ contains:
+ const: arm,coresight-cpu-debug
+ required:
+ - compatible
+
+allOf:
+ - $ref: /schemas/arm/primecell.yaml#
+
+properties:
+ compatible:
+ items:
+ - const: arm,coresight-cpu-debug
+ - const: arm,primecell
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ maxItems: 1
+
+ cpu:
+ description:
+ A phandle to the cpu this debug component is bound to.
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ power-domains:
+ maxItems: 1
+ description:
+ A phandle to the debug power domain if the debug logic has its own
+ dedicated power domain. CPU idle states may also need to be separately
+ constrained to keep CPU cores powered.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - cpu
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ debug@f6590000 {
+ compatible = "arm,coresight-cpu-debug", "arm,primecell";
+ reg = <0xf6590000 0x1000>;
+ clocks = <&sys_ctrl 1>;
+ clock-names = "apb_pclk";
+ cpu = <&cpu0>;
+ };
+...
diff --git a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt b/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
deleted file mode 100644
index f1de3247c1b7..000000000000
--- a/Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-* CoreSight CPU Debug Component:
-
-CoreSight CPU debug component are compliant with the ARMv8 architecture
-reference manual (ARM DDI 0487A.k) Chapter 'Part H: External debug'. The
-external debug module is mainly used for two modes: self-hosted debug and
-external debug, and it can be accessed from mmio region from Coresight
-and eventually the debug module connects with CPU for debugging. And the
-debug module provides sample-based profiling extension, which can be used
-to sample CPU program counter, secure state and exception level, etc;
-usually every CPU has one dedicated debug module to be connected.
-
-Required properties:
-
-- compatible : should be "arm,coresight-cpu-debug"; supplemented with
- "arm,primecell" since this driver is using the AMBA bus
- interface.
-
-- reg : physical base address and length of the register set.
-
-- clocks : the clock associated to this component.
-
-- clock-names : the name of the clock referenced by the code. Since we are
- using the AMBA framework, the name of the clock providing
- the interconnect should be "apb_pclk" and the clock is
- mandatory. The interface between the debug logic and the
- processor core is clocked by the internal CPU clock, so it
- is enabled with CPU clock by default.
-
-- cpu : the CPU phandle the debug module is affined to. Do not assume it
- to default to CPU0 if omitted.
-
-Optional properties:
-
-- power-domains: a phandle to the debug power domain. We use "power-domains"
- binding to turn on the debug logic if it has own dedicated
- power domain and if necessary to use "cpuidle.off=1" or
- "nohlt" in the kernel command line or sysfs node to
- constrain idle states to ensure registers in the CPU power
- domain are accessible.
-
-Example:
-
- debug@f6590000 {
- compatible = "arm,coresight-cpu-debug","arm,primecell";
- reg = <0 0xf6590000 0 0x1000>;
- clocks = <&sys_ctrl HI6220_DAPB_CLK>;
- clock-names = "apb_pclk";
- cpu = <&cpu0>;
- };
diff --git a/MAINTAINERS b/MAINTAINERS
index ac2e7163ab14..59042ecb3cbc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1971,7 +1971,6 @@ L: [email protected] (moderated for non-subscribers)
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git
F: Documentation/ABI/testing/sysfs-bus-coresight-devices-*
-F: Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
F: Documentation/devicetree/bindings/arm/arm,coresight-*.yaml
F: Documentation/devicetree/bindings/arm/arm,embedded-trace-extension.yaml
F: Documentation/devicetree/bindings/arm/arm,trace-buffer-extension.yaml
--
2.34.1
Hi Rob,
On Thu, Jun 02, 2022 at 08:19:30PM -0500, Rob Herring wrote:
> This series converts all the CoreSight debug bindings to DT schema
> format. These bindings are at the top of the list of occurrences of
> bindings without a schema. For arm64 dts files:
>
> 702 ['arm,coresight-etm4x', 'arm,primecell']
> 536 ['arm,coresight-cpu-debug', 'arm,primecell']
> 509 ['arm,coresight-dynamic-funnel', 'arm,primecell']
> 213 ['arm,coresight-tmc', 'arm,primecell']
> 143 ['arm,coresight-dynamic-replicator', 'arm,primecell']
> 97 ['arm,coresight-stm', 'arm,primecell']
>
> I'll send a reply to these with the errors in dts files that this
> causes. I've reviewed them and they all look legit. Xilinx Zynq though
> has 3 clocks instead of 2.
>
> v2:
> - Rename other Coresight bindings to use compatible string for filename
> - Add missing arm,coresight-dynamic-replicator.yaml and
> arm,coresight-static-funnel.yaml
> - Update MAINTAINERS
> - Fix coresight.txt references
What a massive undertaking... I have looked scrupulously and everything adds up.
Let me know if you were looking for me to pick this up. Otherwise:
Reviewed-by: Mathieu Poirier <[email protected]>
Thanks,
Mathieu
>
> Rob
>
> Rob Herring (3):
> dt-bindings: arm: Rename Coresight filenames to match compatible
> dt-bindings: arm: Convert CoreSight bindings to DT schema
> dt-bindings: arm: Convert CoreSight CPU debug to DT schema
>
> .../bindings/arm/arm,coresight-catu.yaml | 101 +++++
> .../bindings/arm/arm,coresight-cpu-debug.yaml | 81 ++++
> ...esight-cti.yaml => arm,coresight-cti.yaml} | 5 +-
> .../arm/arm,coresight-dynamic-funnel.yaml | 126 ++++++
> .../arm/arm,coresight-dynamic-replicator.yaml | 126 ++++++
> .../bindings/arm/arm,coresight-etb10.yaml | 92 ++++
> .../bindings/arm/arm,coresight-etm.yaml | 156 +++++++
> .../arm/arm,coresight-static-funnel.yaml | 89 ++++
> .../arm/arm,coresight-static-replicator.yaml | 90 ++++
> .../bindings/arm/arm,coresight-stm.yaml | 101 +++++
> .../bindings/arm/arm,coresight-tmc.yaml | 131 ++++++
> .../bindings/arm/arm,coresight-tpiu.yaml | 91 ++++
> ...yaml => arm,embedded-trace-extension.yaml} | 3 +-
> ...e.yaml => arm,trace-buffer-extension.yaml} | 2 +-
> .../bindings/arm/coresight-cpu-debug.txt | 49 ---
> .../devicetree/bindings/arm/coresight.txt | 402 ------------------
> Documentation/trace/coresight/coresight.rst | 2 +-
> MAINTAINERS | 8 +-
> 18 files changed, 1192 insertions(+), 463 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-catu.yaml
> create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-cpu-debug.yaml
> rename Documentation/devicetree/bindings/arm/{coresight-cti.yaml => arm,coresight-cti.yaml} (98%)
> create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-dynamic-funnel.yaml
> create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-dynamic-replicator.yaml
> create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-etb10.yaml
> create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-etm.yaml
> create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-static-funnel.yaml
> create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-static-replicator.yaml
> create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-stm.yaml
> create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-tmc.yaml
> create mode 100644 Documentation/devicetree/bindings/arm/arm,coresight-tpiu.yaml
> rename Documentation/devicetree/bindings/arm/{ete.yaml => arm,embedded-trace-extension.yaml} (95%)
> rename Documentation/devicetree/bindings/arm/{trbe.yaml => arm,trace-buffer-extension.yaml} (94%)
> delete mode 100644 Documentation/devicetree/bindings/arm/coresight-cpu-debug.txt
> delete mode 100644 Documentation/devicetree/bindings/arm/coresight.txt
>
> --
> 2.34.1
On 03/06/2022 02:19, Rob Herring wrote:
> Convert the CoreSight CPU debug binding to DT schema format.
>
> Reviewed-by: Leo Yan <[email protected]>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> Signed-off-by: Rob Herring <[email protected]>
Reviewed-by: Suzuki K Poulose <[email protected]>
On Mon, Jun 20, 2022 at 10:55:41AM -0600, Mathieu Poirier wrote:
> Hi Rob,
>
> On Thu, Jun 02, 2022 at 08:19:30PM -0500, Rob Herring wrote:
> > This series converts all the CoreSight debug bindings to DT schema
> > format. These bindings are at the top of the list of occurrences of
> > bindings without a schema. For arm64 dts files:
> >
> > 702 ['arm,coresight-etm4x', 'arm,primecell']
> > 536 ['arm,coresight-cpu-debug', 'arm,primecell']
> > 509 ['arm,coresight-dynamic-funnel', 'arm,primecell']
> > 213 ['arm,coresight-tmc', 'arm,primecell']
> > 143 ['arm,coresight-dynamic-replicator', 'arm,primecell']
> > 97 ['arm,coresight-stm', 'arm,primecell']
> >
> > I'll send a reply to these with the errors in dts files that this
> > causes. I've reviewed them and they all look legit. Xilinx Zynq though
> > has 3 clocks instead of 2.
> >
> > v2:
> > - Rename other Coresight bindings to use compatible string for filename
> > - Add missing arm,coresight-dynamic-replicator.yaml and
> > arm,coresight-static-funnel.yaml
> > - Update MAINTAINERS
> > - Fix coresight.txt references
>
> What a massive undertaking... I have looked scrupulously and everything adds up.
> Let me know if you were looking for me to pick this up. Otherwise:
>
> Reviewed-by: Mathieu Poirier <[email protected]>
Can you apply. I think there was another series from QCom touching
the MAINTAINERS entry that will conflict.
There's a couple of indentation fixups. Can you fix when applying or do
you want me to resend?
Rob
On Tue, Jun 28, 2022 at 12:01:18PM -0600, Rob Herring wrote:
> On Mon, Jun 20, 2022 at 10:55:41AM -0600, Mathieu Poirier wrote:
> > Hi Rob,
> >
> > On Thu, Jun 02, 2022 at 08:19:30PM -0500, Rob Herring wrote:
> > > This series converts all the CoreSight debug bindings to DT schema
> > > format. These bindings are at the top of the list of occurrences of
> > > bindings without a schema. For arm64 dts files:
> > >
> > > 702 ['arm,coresight-etm4x', 'arm,primecell']
> > > 536 ['arm,coresight-cpu-debug', 'arm,primecell']
> > > 509 ['arm,coresight-dynamic-funnel', 'arm,primecell']
> > > 213 ['arm,coresight-tmc', 'arm,primecell']
> > > 143 ['arm,coresight-dynamic-replicator', 'arm,primecell']
> > > 97 ['arm,coresight-stm', 'arm,primecell']
> > >
> > > I'll send a reply to these with the errors in dts files that this
> > > causes. I've reviewed them and they all look legit. Xilinx Zynq though
> > > has 3 clocks instead of 2.
> > >
> > > v2:
> > > - Rename other Coresight bindings to use compatible string for filename
> > > - Add missing arm,coresight-dynamic-replicator.yaml and
> > > arm,coresight-static-funnel.yaml
> > > - Update MAINTAINERS
> > > - Fix coresight.txt references
> >
> > What a massive undertaking... I have looked scrupulously and everything adds up.
> > Let me know if you were looking for me to pick this up. Otherwise:
> >
> > Reviewed-by: Mathieu Poirier <[email protected]>
>
> Can you apply. I think there was another series from QCom touching
> the MAINTAINERS entry that will conflict.
I just tried a rebased on today's linux-next and it didn't blow up.
>
> There's a couple of indentation fixups. Can you fix when applying or do
> you want me to resend?
Fixed and applied.
Thanks,
Mathieu
>
> Rob