Only low 9 bits of CPUID CSR represents coreid, higher bits
are marked as reserved. In case Loongson may define higher
bits in future, just mask them out for get_csr_cpuid.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/loongarch/include/asm/loongarch.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
index 3ba4f7e87cd2..7f3933f747f9 100644
--- a/arch/loongarch/include/asm/loongarch.h
+++ b/arch/loongarch/include/asm/loongarch.h
@@ -1200,7 +1200,7 @@ static inline u64 drdtime(void)
static inline unsigned int get_csr_cpuid(void)
{
- return csr_read32(LOONGARCH_CSR_CPUID);
+ return csr_read32(LOONGARCH_CSR_CPUID) & CSR_CPUID_COREID;
}
static inline void csr_any_send(unsigned int addr, unsigned int data,
--
2.25.1
Hi, Jiaxun,
On Sat, Jun 4, 2022 at 8:41 PM Jiaxun Yang <[email protected]> wrote:
>
> Only low 9 bits of CPUID CSR represents coreid, higher bits
> are marked as reserved. In case Loongson may define higher
> bits in future, just mask them out for get_csr_cpuid.
I think we needn't to modify, until the high bits actually get defined. :)
Huacai
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> ---
> arch/loongarch/include/asm/loongarch.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
> index 3ba4f7e87cd2..7f3933f747f9 100644
> --- a/arch/loongarch/include/asm/loongarch.h
> +++ b/arch/loongarch/include/asm/loongarch.h
> @@ -1200,7 +1200,7 @@ static inline u64 drdtime(void)
>
> static inline unsigned int get_csr_cpuid(void)
> {
> - return csr_read32(LOONGARCH_CSR_CPUID);
> + return csr_read32(LOONGARCH_CSR_CPUID) & CSR_CPUID_COREID;
> }
>
> static inline void csr_any_send(unsigned int addr, unsigned int data,
> --
> 2.25.1
>