2022-05-10 21:07:05

by Antonio Borneo

[permalink] [raw]
Subject: [PATCH 1/7] irqchip/stm32-exti: set_affinity return IRQ_SET_MASK_OK_DONE if no parent

From: Ludovic Barre <[email protected]>

If no parent, there is no specific action to do in
stm32 irqchip, and so return IRQ_SET_MASK_OK_DONE.

Signed-off-by: Ludovic Barre <[email protected]>
Signed-off-by: Antonio Borneo <[email protected]>
---
drivers/irqchip/irq-stm32-exti.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index 9d18f47040eb..10c9c742c216 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -614,7 +614,7 @@ static int stm32_exti_h_set_affinity(struct irq_data *d,
if (d->parent_data->chip)
return irq_chip_set_affinity_parent(d, dest, force);

- return -EINVAL;
+ return IRQ_SET_MASK_OK_DONE;
}

static int __maybe_unused stm32_exti_h_suspend(void)
--
2.36.0



2022-05-10 21:08:11

by Antonio Borneo

[permalink] [raw]
Subject: [PATCH 7/7] irqchip/stm32-exti: simplify irq description table

Having removed the event trigger type from struct stm32_desc_irq
makes worthless keep using a struct.

Replace the struct by a single dimension array and use 8 bit type
to reduce the overal memory footprint.
On armv7a this patch reduces by 7% the size of the driver, from
text data bss dec hex filename
7133 448 4 7585 1da1 irq-stm32-exti.o
to
6605 448 4 7057 1b91 irq-stm32-exti.o

Signed-off-by: Antonio Borneo <[email protected]>
---
drivers/irqchip/irq-stm32-exti.c | 220 ++++++++++++++-----------------
1 file changed, 101 insertions(+), 119 deletions(-)

diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index 2e00e78bf61e..f239895b00a8 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -39,16 +39,10 @@ struct stm32_exti_bank {

#define UNDEF_REG ~0

-struct stm32_desc_irq {
- u32 exti;
- u32 irq_parent;
-};
-
struct stm32_exti_drv_data {
const struct stm32_exti_bank **exti_banks;
- const struct stm32_desc_irq *desc_irqs;
+ const u8 *desc_irqs;
u32 bank_nr;
- u32 irq_nr;
};

struct stm32_exti_chip_data {
@@ -173,126 +167,114 @@ static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
static struct irq_chip stm32_exti_h_chip;
static struct irq_chip stm32_exti_h_chip_direct;

-static const struct stm32_desc_irq stm32mp1_desc_irq[] = {
- { .exti = 0, .irq_parent = 6 },
- { .exti = 1, .irq_parent = 7 },
- { .exti = 2, .irq_parent = 8 },
- { .exti = 3, .irq_parent = 9 },
- { .exti = 4, .irq_parent = 10 },
- { .exti = 5, .irq_parent = 23 },
- { .exti = 6, .irq_parent = 64 },
- { .exti = 7, .irq_parent = 65 },
- { .exti = 8, .irq_parent = 66 },
- { .exti = 9, .irq_parent = 67 },
- { .exti = 10, .irq_parent = 40 },
- { .exti = 11, .irq_parent = 42 },
- { .exti = 12, .irq_parent = 76 },
- { .exti = 13, .irq_parent = 77 },
- { .exti = 14, .irq_parent = 121 },
- { .exti = 15, .irq_parent = 127 },
- { .exti = 16, .irq_parent = 1 },
- { .exti = 19, .irq_parent = 3 },
- { .exti = 21, .irq_parent = 31 },
- { .exti = 22, .irq_parent = 33 },
- { .exti = 23, .irq_parent = 72 },
- { .exti = 24, .irq_parent = 95 },
- { .exti = 25, .irq_parent = 107 },
- { .exti = 26, .irq_parent = 37 },
- { .exti = 27, .irq_parent = 38 },
- { .exti = 28, .irq_parent = 39 },
- { .exti = 29, .irq_parent = 71 },
- { .exti = 30, .irq_parent = 52 },
- { .exti = 31, .irq_parent = 53 },
- { .exti = 32, .irq_parent = 82 },
- { .exti = 33, .irq_parent = 83 },
- { .exti = 47, .irq_parent = 93 },
- { .exti = 48, .irq_parent = 138 },
- { .exti = 50, .irq_parent = 139 },
- { .exti = 52, .irq_parent = 140 },
- { .exti = 53, .irq_parent = 141 },
- { .exti = 54, .irq_parent = 135 },
- { .exti = 61, .irq_parent = 100 },
- { .exti = 65, .irq_parent = 144 },
- { .exti = 68, .irq_parent = 143 },
- { .exti = 70, .irq_parent = 62 },
- { .exti = 73, .irq_parent = 129 },
+#define EXTI_INVALID_IRQ U8_MAX
+#define STM32MP1_DESC_IRQ_SIZE (ARRAY_SIZE(stm32mp1_exti_banks) * IRQS_PER_BANK)
+
+static const u8 stm32mp1_desc_irq[] = {
+ /* default value */
+ [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] = EXTI_INVALID_IRQ,
+
+ [0] = 6,
+ [1] = 7,
+ [2] = 8,
+ [3] = 9,
+ [4] = 10,
+ [5] = 23,
+ [6] = 64,
+ [7] = 65,
+ [8] = 66,
+ [9] = 67,
+ [10] = 40,
+ [11] = 42,
+ [12] = 76,
+ [13] = 77,
+ [14] = 121,
+ [15] = 127,
+ [16] = 1,
+ [19] = 3,
+ [21] = 31,
+ [22] = 33,
+ [23] = 72,
+ [24] = 95,
+ [25] = 107,
+ [26] = 37,
+ [27] = 38,
+ [28] = 39,
+ [29] = 71,
+ [30] = 52,
+ [31] = 53,
+ [32] = 82,
+ [33] = 83,
+ [47] = 93,
+ [48] = 138,
+ [50] = 139,
+ [52] = 140,
+ [53] = 141,
+ [54] = 135,
+ [61] = 100,
+ [65] = 144,
+ [68] = 143,
+ [70] = 62,
+ [73] = 129,
};

-static const struct stm32_desc_irq stm32mp13_desc_irq[] = {
- { .exti = 0, .irq_parent = 6 },
- { .exti = 1, .irq_parent = 7 },
- { .exti = 2, .irq_parent = 8 },
- { .exti = 3, .irq_parent = 9 },
- { .exti = 4, .irq_parent = 10 },
- { .exti = 5, .irq_parent = 24 },
- { .exti = 6, .irq_parent = 65 },
- { .exti = 7, .irq_parent = 66 },
- { .exti = 8, .irq_parent = 67 },
- { .exti = 9, .irq_parent = 68 },
- { .exti = 10, .irq_parent = 41 },
- { .exti = 11, .irq_parent = 43 },
- { .exti = 12, .irq_parent = 77 },
- { .exti = 13, .irq_parent = 78 },
- { .exti = 14, .irq_parent = 106 },
- { .exti = 15, .irq_parent = 109 },
- { .exti = 16, .irq_parent = 1 },
- { .exti = 19, .irq_parent = 3 },
- { .exti = 21, .irq_parent = 32 },
- { .exti = 22, .irq_parent = 34 },
- { .exti = 23, .irq_parent = 73 },
- { .exti = 24, .irq_parent = 93 },
- { .exti = 25, .irq_parent = 114 },
- { .exti = 26, .irq_parent = 38 },
- { .exti = 27, .irq_parent = 39 },
- { .exti = 28, .irq_parent = 40 },
- { .exti = 29, .irq_parent = 72 },
- { .exti = 30, .irq_parent = 53 },
- { .exti = 31, .irq_parent = 54 },
- { .exti = 32, .irq_parent = 83 },
- { .exti = 33, .irq_parent = 84 },
- { .exti = 44, .irq_parent = 96 },
- { .exti = 47, .irq_parent = 92 },
- { .exti = 48, .irq_parent = 116 },
- { .exti = 50, .irq_parent = 117 },
- { .exti = 52, .irq_parent = 118 },
- { .exti = 53, .irq_parent = 119 },
- { .exti = 68, .irq_parent = 63 },
- { .exti = 70, .irq_parent = 98 },
+static const u8 stm32mp13_desc_irq[] = {
+ /* default value */
+ [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] = EXTI_INVALID_IRQ,
+
+ [0] = 6,
+ [1] = 7,
+ [2] = 8,
+ [3] = 9,
+ [4] = 10,
+ [5] = 24,
+ [6] = 65,
+ [7] = 66,
+ [8] = 67,
+ [9] = 68,
+ [10] = 41,
+ [11] = 43,
+ [12] = 77,
+ [13] = 78,
+ [14] = 106,
+ [15] = 109,
+ [16] = 1,
+ [19] = 3,
+ [21] = 32,
+ [22] = 34,
+ [23] = 73,
+ [24] = 93,
+ [25] = 114,
+ [26] = 38,
+ [27] = 39,
+ [28] = 40,
+ [29] = 72,
+ [30] = 53,
+ [31] = 54,
+ [32] = 83,
+ [33] = 84,
+ [44] = 96,
+ [47] = 92,
+ [48] = 116,
+ [50] = 117,
+ [52] = 118,
+ [53] = 119,
+ [68] = 63,
+ [70] = 98,
};

static const struct stm32_exti_drv_data stm32mp1_drv_data = {
.exti_banks = stm32mp1_exti_banks,
.bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
.desc_irqs = stm32mp1_desc_irq,
- .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq),
};

static const struct stm32_exti_drv_data stm32mp13_drv_data = {
.exti_banks = stm32mp1_exti_banks,
.bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
.desc_irqs = stm32mp13_desc_irq,
- .irq_nr = ARRAY_SIZE(stm32mp13_desc_irq),
};

-static const struct
-stm32_desc_irq *stm32_exti_get_desc(const struct stm32_exti_drv_data *drv_data,
- irq_hw_number_t hwirq)
-{
- const struct stm32_desc_irq *desc = NULL;
- int i;
-
- if (!drv_data->desc_irqs)
- return NULL;
-
- for (i = 0; i < drv_data->irq_nr; i++) {
- desc = &drv_data->desc_irqs[i];
- if (desc->exti == hwirq)
- break;
- }
-
- return desc;
-}
-
static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
{
struct stm32_exti_chip_data *chip_data = gc->private;
@@ -724,7 +706,7 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
{
struct stm32_exti_host_data *host_data = dm->host_data;
struct stm32_exti_chip_data *chip_data;
- const struct stm32_desc_irq *desc;
+ u8 desc_irq;
struct irq_fwspec *fwspec = data;
struct irq_fwspec p_fwspec;
irq_hw_number_t hwirq;
@@ -739,21 +721,21 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
bank = hwirq / IRQS_PER_BANK;
chip_data = &host_data->chips_data[bank];

-
- desc = stm32_exti_get_desc(host_data->drv_data, hwirq);
- if (!desc)
- return -EINVAL;
-
event_trg = readl_relaxed(host_data->base + chip_data->reg_bank->trg_ofst);
chip = (event_trg & BIT(hwirq % IRQS_PER_BANK)) ?
&stm32_exti_h_chip : &stm32_exti_h_chip_direct;

irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data);
- if (desc->irq_parent) {
+
+ if (!host_data->drv_data || !host_data->drv_data->desc_irqs)
+ return -EINVAL;
+
+ desc_irq = host_data->drv_data->desc_irqs[hwirq];
+ if (desc_irq != EXTI_INVALID_IRQ) {
p_fwspec.fwnode = dm->parent->fwnode;
p_fwspec.param_count = 3;
p_fwspec.param[0] = GIC_SPI;
- p_fwspec.param[1] = desc->irq_parent;
+ p_fwspec.param[1] = desc_irq;
p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;

return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);
--
2.36.0


2022-05-10 21:27:15

by Antonio Borneo

[permalink] [raw]
Subject: [PATCH 6/7] irqchip/stm32-exti: read event trigger type from event_trg register

The flag reporting whether an event is 'direct' or 'configurable'
is available in the read-only registers EVENT_TRG.

Drop this redundant information from the struct stm32_desc_irq and
use the proper bit from EVENT_TRG register.

Signed-off-by: Antonio Borneo <[email protected]>
---
drivers/irqchip/irq-stm32-exti.c | 180 ++++++++++++++++---------------
1 file changed, 96 insertions(+), 84 deletions(-)

diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index 509a4a96a99b..2e00e78bf61e 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -34,6 +34,7 @@ struct stm32_exti_bank {
u32 swier_ofst;
u32 rpr_ofst;
u32 fpr_ofst;
+ u32 trg_ofst;
};

#define UNDEF_REG ~0
@@ -41,7 +42,6 @@ struct stm32_exti_bank {
struct stm32_desc_irq {
u32 exti;
u32 irq_parent;
- struct irq_chip *chip;
};

struct stm32_exti_drv_data {
@@ -78,6 +78,7 @@ static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
.swier_ofst = 0x10,
.rpr_ofst = 0x14,
.fpr_ofst = UNDEF_REG,
+ .trg_ofst = UNDEF_REG,
};

static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
@@ -97,6 +98,7 @@ static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
.swier_ofst = 0x08,
.rpr_ofst = 0x88,
.fpr_ofst = UNDEF_REG,
+ .trg_ofst = UNDEF_REG,
};

static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
@@ -107,6 +109,7 @@ static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
.swier_ofst = 0x28,
.rpr_ofst = 0x98,
.fpr_ofst = UNDEF_REG,
+ .trg_ofst = UNDEF_REG,
};

static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
@@ -117,6 +120,7 @@ static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
.swier_ofst = 0x48,
.rpr_ofst = 0xA8,
.fpr_ofst = UNDEF_REG,
+ .trg_ofst = UNDEF_REG,
};

static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
@@ -137,6 +141,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b1 = {
.swier_ofst = 0x08,
.rpr_ofst = 0x0C,
.fpr_ofst = 0x10,
+ .trg_ofst = 0x3EC,
};

static const struct stm32_exti_bank stm32mp1_exti_b2 = {
@@ -146,6 +151,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b2 = {
.swier_ofst = 0x28,
.rpr_ofst = 0x2C,
.fpr_ofst = 0x30,
+ .trg_ofst = 0x3E8,
};

static const struct stm32_exti_bank stm32mp1_exti_b3 = {
@@ -155,6 +161,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b3 = {
.swier_ofst = 0x48,
.rpr_ofst = 0x4C,
.fpr_ofst = 0x50,
+ .trg_ofst = 0x3E4,
};

static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
@@ -167,90 +174,90 @@ static struct irq_chip stm32_exti_h_chip;
static struct irq_chip stm32_exti_h_chip_direct;

static const struct stm32_desc_irq stm32mp1_desc_irq[] = {
- { .exti = 0, .irq_parent = 6, .chip = &stm32_exti_h_chip },
- { .exti = 1, .irq_parent = 7, .chip = &stm32_exti_h_chip },
- { .exti = 2, .irq_parent = 8, .chip = &stm32_exti_h_chip },
- { .exti = 3, .irq_parent = 9, .chip = &stm32_exti_h_chip },
- { .exti = 4, .irq_parent = 10, .chip = &stm32_exti_h_chip },
- { .exti = 5, .irq_parent = 23, .chip = &stm32_exti_h_chip },
- { .exti = 6, .irq_parent = 64, .chip = &stm32_exti_h_chip },
- { .exti = 7, .irq_parent = 65, .chip = &stm32_exti_h_chip },
- { .exti = 8, .irq_parent = 66, .chip = &stm32_exti_h_chip },
- { .exti = 9, .irq_parent = 67, .chip = &stm32_exti_h_chip },
- { .exti = 10, .irq_parent = 40, .chip = &stm32_exti_h_chip },
- { .exti = 11, .irq_parent = 42, .chip = &stm32_exti_h_chip },
- { .exti = 12, .irq_parent = 76, .chip = &stm32_exti_h_chip },
- { .exti = 13, .irq_parent = 77, .chip = &stm32_exti_h_chip },
- { .exti = 14, .irq_parent = 121, .chip = &stm32_exti_h_chip },
- { .exti = 15, .irq_parent = 127, .chip = &stm32_exti_h_chip },
- { .exti = 16, .irq_parent = 1, .chip = &stm32_exti_h_chip },
- { .exti = 19, .irq_parent = 3, .chip = &stm32_exti_h_chip_direct },
- { .exti = 21, .irq_parent = 31, .chip = &stm32_exti_h_chip_direct },
- { .exti = 22, .irq_parent = 33, .chip = &stm32_exti_h_chip_direct },
- { .exti = 23, .irq_parent = 72, .chip = &stm32_exti_h_chip_direct },
- { .exti = 24, .irq_parent = 95, .chip = &stm32_exti_h_chip_direct },
- { .exti = 25, .irq_parent = 107, .chip = &stm32_exti_h_chip_direct },
- { .exti = 26, .irq_parent = 37, .chip = &stm32_exti_h_chip_direct },
- { .exti = 27, .irq_parent = 38, .chip = &stm32_exti_h_chip_direct },
- { .exti = 28, .irq_parent = 39, .chip = &stm32_exti_h_chip_direct },
- { .exti = 29, .irq_parent = 71, .chip = &stm32_exti_h_chip_direct },
- { .exti = 30, .irq_parent = 52, .chip = &stm32_exti_h_chip_direct },
- { .exti = 31, .irq_parent = 53, .chip = &stm32_exti_h_chip_direct },
- { .exti = 32, .irq_parent = 82, .chip = &stm32_exti_h_chip_direct },
- { .exti = 33, .irq_parent = 83, .chip = &stm32_exti_h_chip_direct },
- { .exti = 47, .irq_parent = 93, .chip = &stm32_exti_h_chip_direct },
- { .exti = 48, .irq_parent = 138, .chip = &stm32_exti_h_chip_direct },
- { .exti = 50, .irq_parent = 139, .chip = &stm32_exti_h_chip_direct },
- { .exti = 52, .irq_parent = 140, .chip = &stm32_exti_h_chip_direct },
- { .exti = 53, .irq_parent = 141, .chip = &stm32_exti_h_chip_direct },
- { .exti = 54, .irq_parent = 135, .chip = &stm32_exti_h_chip_direct },
- { .exti = 61, .irq_parent = 100, .chip = &stm32_exti_h_chip_direct },
- { .exti = 65, .irq_parent = 144, .chip = &stm32_exti_h_chip },
- { .exti = 68, .irq_parent = 143, .chip = &stm32_exti_h_chip },
- { .exti = 70, .irq_parent = 62, .chip = &stm32_exti_h_chip_direct },
- { .exti = 73, .irq_parent = 129, .chip = &stm32_exti_h_chip },
+ { .exti = 0, .irq_parent = 6 },
+ { .exti = 1, .irq_parent = 7 },
+ { .exti = 2, .irq_parent = 8 },
+ { .exti = 3, .irq_parent = 9 },
+ { .exti = 4, .irq_parent = 10 },
+ { .exti = 5, .irq_parent = 23 },
+ { .exti = 6, .irq_parent = 64 },
+ { .exti = 7, .irq_parent = 65 },
+ { .exti = 8, .irq_parent = 66 },
+ { .exti = 9, .irq_parent = 67 },
+ { .exti = 10, .irq_parent = 40 },
+ { .exti = 11, .irq_parent = 42 },
+ { .exti = 12, .irq_parent = 76 },
+ { .exti = 13, .irq_parent = 77 },
+ { .exti = 14, .irq_parent = 121 },
+ { .exti = 15, .irq_parent = 127 },
+ { .exti = 16, .irq_parent = 1 },
+ { .exti = 19, .irq_parent = 3 },
+ { .exti = 21, .irq_parent = 31 },
+ { .exti = 22, .irq_parent = 33 },
+ { .exti = 23, .irq_parent = 72 },
+ { .exti = 24, .irq_parent = 95 },
+ { .exti = 25, .irq_parent = 107 },
+ { .exti = 26, .irq_parent = 37 },
+ { .exti = 27, .irq_parent = 38 },
+ { .exti = 28, .irq_parent = 39 },
+ { .exti = 29, .irq_parent = 71 },
+ { .exti = 30, .irq_parent = 52 },
+ { .exti = 31, .irq_parent = 53 },
+ { .exti = 32, .irq_parent = 82 },
+ { .exti = 33, .irq_parent = 83 },
+ { .exti = 47, .irq_parent = 93 },
+ { .exti = 48, .irq_parent = 138 },
+ { .exti = 50, .irq_parent = 139 },
+ { .exti = 52, .irq_parent = 140 },
+ { .exti = 53, .irq_parent = 141 },
+ { .exti = 54, .irq_parent = 135 },
+ { .exti = 61, .irq_parent = 100 },
+ { .exti = 65, .irq_parent = 144 },
+ { .exti = 68, .irq_parent = 143 },
+ { .exti = 70, .irq_parent = 62 },
+ { .exti = 73, .irq_parent = 129 },
};

static const struct stm32_desc_irq stm32mp13_desc_irq[] = {
- { .exti = 0, .irq_parent = 6, .chip = &stm32_exti_h_chip },
- { .exti = 1, .irq_parent = 7, .chip = &stm32_exti_h_chip },
- { .exti = 2, .irq_parent = 8, .chip = &stm32_exti_h_chip },
- { .exti = 3, .irq_parent = 9, .chip = &stm32_exti_h_chip },
- { .exti = 4, .irq_parent = 10, .chip = &stm32_exti_h_chip },
- { .exti = 5, .irq_parent = 24, .chip = &stm32_exti_h_chip },
- { .exti = 6, .irq_parent = 65, .chip = &stm32_exti_h_chip },
- { .exti = 7, .irq_parent = 66, .chip = &stm32_exti_h_chip },
- { .exti = 8, .irq_parent = 67, .chip = &stm32_exti_h_chip },
- { .exti = 9, .irq_parent = 68, .chip = &stm32_exti_h_chip },
- { .exti = 10, .irq_parent = 41, .chip = &stm32_exti_h_chip },
- { .exti = 11, .irq_parent = 43, .chip = &stm32_exti_h_chip },
- { .exti = 12, .irq_parent = 77, .chip = &stm32_exti_h_chip },
- { .exti = 13, .irq_parent = 78, .chip = &stm32_exti_h_chip },
- { .exti = 14, .irq_parent = 106, .chip = &stm32_exti_h_chip },
- { .exti = 15, .irq_parent = 109, .chip = &stm32_exti_h_chip },
- { .exti = 16, .irq_parent = 1, .chip = &stm32_exti_h_chip },
- { .exti = 19, .irq_parent = 3, .chip = &stm32_exti_h_chip_direct },
- { .exti = 21, .irq_parent = 32, .chip = &stm32_exti_h_chip_direct },
- { .exti = 22, .irq_parent = 34, .chip = &stm32_exti_h_chip_direct },
- { .exti = 23, .irq_parent = 73, .chip = &stm32_exti_h_chip_direct },
- { .exti = 24, .irq_parent = 93, .chip = &stm32_exti_h_chip_direct },
- { .exti = 25, .irq_parent = 114, .chip = &stm32_exti_h_chip_direct },
- { .exti = 26, .irq_parent = 38, .chip = &stm32_exti_h_chip_direct },
- { .exti = 27, .irq_parent = 39, .chip = &stm32_exti_h_chip_direct },
- { .exti = 28, .irq_parent = 40, .chip = &stm32_exti_h_chip_direct },
- { .exti = 29, .irq_parent = 72, .chip = &stm32_exti_h_chip_direct },
- { .exti = 30, .irq_parent = 53, .chip = &stm32_exti_h_chip_direct },
- { .exti = 31, .irq_parent = 54, .chip = &stm32_exti_h_chip_direct },
- { .exti = 32, .irq_parent = 83, .chip = &stm32_exti_h_chip_direct },
- { .exti = 33, .irq_parent = 84, .chip = &stm32_exti_h_chip_direct },
- { .exti = 44, .irq_parent = 96, .chip = &stm32_exti_h_chip_direct },
- { .exti = 47, .irq_parent = 92, .chip = &stm32_exti_h_chip_direct },
- { .exti = 48, .irq_parent = 116, .chip = &stm32_exti_h_chip_direct },
- { .exti = 50, .irq_parent = 117, .chip = &stm32_exti_h_chip_direct },
- { .exti = 52, .irq_parent = 118, .chip = &stm32_exti_h_chip_direct },
- { .exti = 53, .irq_parent = 119, .chip = &stm32_exti_h_chip_direct },
- { .exti = 68, .irq_parent = 63, .chip = &stm32_exti_h_chip_direct },
- { .exti = 70, .irq_parent = 98, .chip = &stm32_exti_h_chip_direct },
+ { .exti = 0, .irq_parent = 6 },
+ { .exti = 1, .irq_parent = 7 },
+ { .exti = 2, .irq_parent = 8 },
+ { .exti = 3, .irq_parent = 9 },
+ { .exti = 4, .irq_parent = 10 },
+ { .exti = 5, .irq_parent = 24 },
+ { .exti = 6, .irq_parent = 65 },
+ { .exti = 7, .irq_parent = 66 },
+ { .exti = 8, .irq_parent = 67 },
+ { .exti = 9, .irq_parent = 68 },
+ { .exti = 10, .irq_parent = 41 },
+ { .exti = 11, .irq_parent = 43 },
+ { .exti = 12, .irq_parent = 77 },
+ { .exti = 13, .irq_parent = 78 },
+ { .exti = 14, .irq_parent = 106 },
+ { .exti = 15, .irq_parent = 109 },
+ { .exti = 16, .irq_parent = 1 },
+ { .exti = 19, .irq_parent = 3 },
+ { .exti = 21, .irq_parent = 32 },
+ { .exti = 22, .irq_parent = 34 },
+ { .exti = 23, .irq_parent = 73 },
+ { .exti = 24, .irq_parent = 93 },
+ { .exti = 25, .irq_parent = 114 },
+ { .exti = 26, .irq_parent = 38 },
+ { .exti = 27, .irq_parent = 39 },
+ { .exti = 28, .irq_parent = 40 },
+ { .exti = 29, .irq_parent = 72 },
+ { .exti = 30, .irq_parent = 53 },
+ { .exti = 31, .irq_parent = 54 },
+ { .exti = 32, .irq_parent = 83 },
+ { .exti = 33, .irq_parent = 84 },
+ { .exti = 44, .irq_parent = 96 },
+ { .exti = 47, .irq_parent = 92 },
+ { .exti = 48, .irq_parent = 116 },
+ { .exti = 50, .irq_parent = 117 },
+ { .exti = 52, .irq_parent = 118 },
+ { .exti = 53, .irq_parent = 119 },
+ { .exti = 68, .irq_parent = 63 },
+ { .exti = 70, .irq_parent = 98 },
};

static const struct stm32_exti_drv_data stm32mp1_drv_data = {
@@ -722,6 +729,8 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
struct irq_fwspec p_fwspec;
irq_hw_number_t hwirq;
int bank;
+ u32 event_trg;
+ struct irq_chip *chip;

hwirq = fwspec->param[0];
if (hwirq >= host_data->drv_data->bank_nr * IRQS_PER_BANK)
@@ -735,8 +744,11 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
if (!desc)
return -EINVAL;

- irq_domain_set_hwirq_and_chip(dm, virq, hwirq, desc->chip,
- chip_data);
+ event_trg = readl_relaxed(host_data->base + chip_data->reg_bank->trg_ofst);
+ chip = (event_trg & BIT(hwirq % IRQS_PER_BANK)) ?
+ &stm32_exti_h_chip : &stm32_exti_h_chip_direct;
+
+ irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data);
if (desc->irq_parent) {
p_fwspec.fwnode = dm->parent->fwnode;
p_fwspec.param_count = 3;
--
2.36.0


2022-05-10 21:44:47

by Antonio Borneo

[permalink] [raw]
Subject: [PATCH 2/7] irqchip/stm32-exti: manage IMR at each mask/unmask for direct event

From: Loic Pallardy <[email protected]>

Enable EXTI line through IMR also on direct event.

Signed-off-by: Loic Pallardy <[email protected]>
Signed-off-by: Antonio Borneo <[email protected]>
---
drivers/irqchip/irq-stm32-exti.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index 10c9c742c216..1145f064faa8 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -691,8 +691,8 @@ static struct irq_chip stm32_exti_h_chip_direct = {
.name = "stm32-exti-h-direct",
.irq_eoi = irq_chip_eoi_parent,
.irq_ack = irq_chip_ack_parent,
- .irq_mask = irq_chip_mask_parent,
- .irq_unmask = irq_chip_unmask_parent,
+ .irq_mask = stm32_exti_h_mask,
+ .irq_unmask = stm32_exti_h_unmask,
.irq_retrigger = irq_chip_retrigger_hierarchy,
.irq_set_type = irq_chip_set_type_parent,
.irq_set_wake = stm32_exti_h_set_wake,
--
2.36.0


2022-05-11 09:49:43

by Marc Zyngier

[permalink] [raw]
Subject: Re: [PATCH 1/7] irqchip/stm32-exti: set_affinity return IRQ_SET_MASK_OK_DONE if no parent

On Wed, 11 May 2022 07:39:43 +0100,
Antonio Borneo <[email protected]> wrote:
>
> Hi Marc,
>
> On Tue, 2022-05-10 at 19:34 +0100, Marc Zyngier wrote:
> > Antonio,
> >
> > On Tue, 10 May 2022 17:41:17 +0100,
> > Antonio Borneo <[email protected]> wrote:
> > >
> > > From: Ludovic Barre <[email protected]>
> > >
> > > If no parent, there is no specific action to do in
> > > stm32 irqchip, and so return IRQ_SET_MASK_OK_DONE.
> > >
> > > Signed-off-by: Ludovic Barre <[email protected]>
> > > Signed-off-by: Antonio Borneo <[email protected]>
> > > ---
> > >  drivers/irqchip/irq-stm32-exti.c | 2 +-
> > >  1 file changed, 1 insertion(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/irqchip/irq-stm32-exti.c
> > > b/drivers/irqchip/irq-stm32-exti.c
> > > index 9d18f47040eb..10c9c742c216 100644
> > > --- a/drivers/irqchip/irq-stm32-exti.c
> > > +++ b/drivers/irqchip/irq-stm32-exti.c
> > > @@ -614,7 +614,7 @@ static int stm32_exti_h_set_affinity(struct
> > > irq_data *d,
> > >         if (d->parent_data->chip)
> > >                 return irq_chip_set_affinity_parent(d, dest,
> > > force);
> > >  
> > > -       return -EINVAL;
> > > +       return IRQ_SET_MASK_OK_DONE;
> > >  }
> > >  
> > >  static int __maybe_unused stm32_exti_h_suspend(void)
> >
> > <rant>
> > Can you *please* use a cover-letter when sending more that a single
> > patch? I expect there is an overarching motive to this series. Where
> > is it described?
> >
> > Also, please look at the way the subject lines are written for most
> > irqchip patches:
> >
> > irqchip/foo: Frobify the bar callback return value
> >
> > Note the capital letter after the ':', and the fact that it starts
> > with a verb. Here, I would have liked to see:
> >
> > irqchip/stm32-exti: Fix set_affinity() return value
> >
> > and leave the meat of the description to the commit log (instead of
> > saying the exact same thing twice).
> > </rant>
>
> thanks for your review and the hints on this series.
> I will shortly send a V2.

No rush. I'm about to close the 5.19 irqchip tree.

Thanks,

M.

--
Without deviation from the norm, progress is not possible.

2022-05-11 10:42:49

by Marc Zyngier

[permalink] [raw]
Subject: Re: [PATCH 2/7] irqchip/stm32-exti: manage IMR at each mask/unmask for direct event

On Tue, 10 May 2022 17:41:18 +0100,
Antonio Borneo <[email protected]> wrote:
>
> From: Loic Pallardy <[email protected]>
>
> Enable EXTI line through IMR also on direct event.

Notice how none of the words above say *anything* about mask/unmask?
What happens? What breaks? Is it a fix? If so, what does it fix?

M.

>
> Signed-off-by: Loic Pallardy <[email protected]>
> Signed-off-by: Antonio Borneo <[email protected]>
> ---
> drivers/irqchip/irq-stm32-exti.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
> index 10c9c742c216..1145f064faa8 100644
> --- a/drivers/irqchip/irq-stm32-exti.c
> +++ b/drivers/irqchip/irq-stm32-exti.c
> @@ -691,8 +691,8 @@ static struct irq_chip stm32_exti_h_chip_direct = {
> .name = "stm32-exti-h-direct",
> .irq_eoi = irq_chip_eoi_parent,
> .irq_ack = irq_chip_ack_parent,
> - .irq_mask = irq_chip_mask_parent,
> - .irq_unmask = irq_chip_unmask_parent,
> + .irq_mask = stm32_exti_h_mask,
> + .irq_unmask = stm32_exti_h_unmask,
> .irq_retrigger = irq_chip_retrigger_hierarchy,
> .irq_set_type = irq_chip_set_type_parent,
> .irq_set_wake = stm32_exti_h_set_wake,
> --
> 2.36.0
>
>

--
Without deviation from the norm, progress is not possible.

2022-06-06 16:47:22

by Antonio Borneo

[permalink] [raw]
Subject: [PATCH v2 1/6] irqchip/stm32-exti: Fix irq_set_affinity return value

From: Ludovic Barre <[email protected]>

When there is no parent, there is no specific action to do in
stm32-exti irqchip. In such case, it's incorrect returning an
error.

Let irq_set_affinity to return IRQ_SET_MASK_OK_DONE when there is
no parent.

Signed-off-by: Ludovic Barre <[email protected]>
Signed-off-by: Antonio Borneo <[email protected]>
---
drivers/irqchip/irq-stm32-exti.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index 9d18f47040eb..10c9c742c216 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -614,7 +614,7 @@ static int stm32_exti_h_set_affinity(struct irq_data *d,
if (d->parent_data->chip)
return irq_chip_set_affinity_parent(d, dest, force);

- return -EINVAL;
+ return IRQ_SET_MASK_OK_DONE;
}

static int __maybe_unused stm32_exti_h_suspend(void)
--
2.36.1

2022-06-06 16:47:26

by Antonio Borneo

[permalink] [raw]
Subject: [PATCH v2 0/6] irqchip/stm32-exti: Fixes and simplifications

This series address some code fix for irq-stm32-exti driver and
simplifies the table that remaps the interrupts from exti to gic.


v1->v2
- Properly format the commit title and expand the commit msg;
- drop the patch v1 4/7:
"irqchip/stm32-exti: forward irq_request_resources to parent"
in favor of the generic:
https://lore.kernel.org/lkml/[email protected]/
"genirq: Don't return error on missing optional
irq_request_resources()";
- use consistently UNDEF_REG for non existing EMR registers;
- rebase on v5.19-rc1.


Alexandre Torgue (1):
irqchip/stm32-exti: Tag emr register as undefined for stm32mp15

Antonio Borneo (3):
irqchip/stm32-exti: Prevent illegal read due to unbounded DT value
irqchip/stm32-exti: Read event trigger type from event_trg register
irqchip/stm32-exti: Simplify irq description table

Loic Pallardy (1):
irqchip/stm32-exti: Fix irq_mask/irq_unmask for direct events

Ludovic Barre (1):
irqchip/stm32-exti: Fix irq_set_affinity return value

drivers/irqchip/irq-stm32-exti.c | 250 +++++++++++++++----------------
1 file changed, 124 insertions(+), 126 deletions(-)


base-commit: f2906aa863381afb0015a9eb7fefad885d4e5a56
--
2.36.1

2022-06-06 16:47:28

by Antonio Borneo

[permalink] [raw]
Subject: [PATCH v2 2/6] irqchip/stm32-exti: Fix irq_mask/irq_unmask for direct events

From: Loic Pallardy <[email protected]>

The driver has to mask/unmask the corresponding flag in the
Interrupt Mask Register (IMR).
This is already done for configurable event, while direct events
only forward the mask/unmask request to the parent.

Use the existing stm32_exti_h_mask()/stm32_exti_h_unmask() for
direct events too.

Signed-off-by: Loic Pallardy <[email protected]>
Signed-off-by: Antonio Borneo <[email protected]>
---
drivers/irqchip/irq-stm32-exti.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index 10c9c742c216..1145f064faa8 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -691,8 +691,8 @@ static struct irq_chip stm32_exti_h_chip_direct = {
.name = "stm32-exti-h-direct",
.irq_eoi = irq_chip_eoi_parent,
.irq_ack = irq_chip_ack_parent,
- .irq_mask = irq_chip_mask_parent,
- .irq_unmask = irq_chip_unmask_parent,
+ .irq_mask = stm32_exti_h_mask,
+ .irq_unmask = stm32_exti_h_unmask,
.irq_retrigger = irq_chip_retrigger_hierarchy,
.irq_set_type = irq_chip_set_type_parent,
.irq_set_wake = stm32_exti_h_set_wake,
--
2.36.1

2022-06-06 16:47:30

by Antonio Borneo

[permalink] [raw]
Subject: [PATCH v2 3/6] irqchip/stm32-exti: Prevent illegal read due to unbounded DT value

The value hwirq is received from DT. If it exceeds the maximum
valid value it causes the code to address unexisting irq chips
reading outside the array boundary.

Check the value of hwirq before using it.

Signed-off-by: Antonio Borneo <[email protected]>
---
drivers/irqchip/irq-stm32-exti.c | 3 +++
1 file changed, 3 insertions(+)

diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index 1145f064faa8..e2722e499ae5 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -713,6 +713,9 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
int bank;

hwirq = fwspec->param[0];
+ if (hwirq >= host_data->drv_data->bank_nr * IRQS_PER_BANK)
+ return -EINVAL;
+
bank = hwirq / IRQS_PER_BANK;
chip_data = &host_data->chips_data[bank];

--
2.36.1

2022-06-06 16:47:34

by Antonio Borneo

[permalink] [raw]
Subject: [PATCH v2 4/6] irqchip/stm32-exti: Tag emr register as undefined for stm32mp15

From: Alexandre Torgue <[email protected]>

The reference manual RM0436 of stm32mp15 till version v4.0 was
erroneously reporting the Event Mask Registers (EMR) for the
Cortex-A CPUs.
These registers have been removed from v5.0 of the manual and the
corresponding offsets have been marked as 'Reserved'.

Prevent accessing these reserved addresses by tagging the EMR
offsets as UNDEF_REG and modifying the code to handle this case.

Signed-off-by: Alexandre Torgue <[email protected]>
Signed-off-by: Antonio Borneo <[email protected]>
---
drivers/irqchip/irq-stm32-exti.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index e2722e499ae5..e8fa91bda4ba 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -132,7 +132,7 @@ static const struct stm32_exti_drv_data stm32h7xx_drv_data = {

static const struct stm32_exti_bank stm32mp1_exti_b1 = {
.imr_ofst = 0x80,
- .emr_ofst = 0x84,
+ .emr_ofst = UNDEF_REG,
.rtsr_ofst = 0x00,
.ftsr_ofst = 0x04,
.swier_ofst = 0x08,
@@ -142,7 +142,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b1 = {

static const struct stm32_exti_bank stm32mp1_exti_b2 = {
.imr_ofst = 0x90,
- .emr_ofst = 0x94,
+ .emr_ofst = UNDEF_REG,
.rtsr_ofst = 0x20,
.ftsr_ofst = 0x24,
.swier_ofst = 0x28,
@@ -152,7 +152,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b2 = {

static const struct stm32_exti_bank stm32mp1_exti_b3 = {
.imr_ofst = 0xA0,
- .emr_ofst = 0xA4,
+ .emr_ofst = UNDEF_REG,
.rtsr_ofst = 0x40,
.ftsr_ofst = 0x44,
.swier_ofst = 0x48,
@@ -795,7 +795,8 @@ stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
* clear registers to avoid residue
*/
writel_relaxed(0, base + stm32_bank->imr_ofst);
- writel_relaxed(0, base + stm32_bank->emr_ofst);
+ if (stm32_bank->emr_ofst != UNDEF_REG)
+ writel_relaxed(0, base + stm32_bank->emr_ofst);

pr_info("%pOF: bank%d\n", node, bank_idx);

--
2.36.1

2022-06-06 16:47:42

by Antonio Borneo

[permalink] [raw]
Subject: [PATCH v2 6/6] irqchip/stm32-exti: Simplify irq description table

Having removed the event trigger type from struct stm32_desc_irq
makes worthless keep using a struct.

Replace the struct by a single dimension array and use 8 bit type
to reduce the overal memory footprint.
On armv7a this patch reduces by 7% the size of the driver, from
text data bss dec hex filename
6977 424 4 7405 1ced irq-stm32-exti.o
to
6449 424 4 6877 1add irq-stm32-exti.o

Signed-off-by: Antonio Borneo <[email protected]>
---
drivers/irqchip/irq-stm32-exti.c | 220 ++++++++++++++-----------------
1 file changed, 101 insertions(+), 119 deletions(-)

diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index 045589627e67..a73763d475f0 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -39,16 +39,10 @@ struct stm32_exti_bank {

#define UNDEF_REG ~0

-struct stm32_desc_irq {
- u32 exti;
- u32 irq_parent;
-};
-
struct stm32_exti_drv_data {
const struct stm32_exti_bank **exti_banks;
- const struct stm32_desc_irq *desc_irqs;
+ const u8 *desc_irqs;
u32 bank_nr;
- u32 irq_nr;
};

struct stm32_exti_chip_data {
@@ -176,126 +170,114 @@ static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
static struct irq_chip stm32_exti_h_chip;
static struct irq_chip stm32_exti_h_chip_direct;

-static const struct stm32_desc_irq stm32mp1_desc_irq[] = {
- { .exti = 0, .irq_parent = 6 },
- { .exti = 1, .irq_parent = 7 },
- { .exti = 2, .irq_parent = 8 },
- { .exti = 3, .irq_parent = 9 },
- { .exti = 4, .irq_parent = 10 },
- { .exti = 5, .irq_parent = 23 },
- { .exti = 6, .irq_parent = 64 },
- { .exti = 7, .irq_parent = 65 },
- { .exti = 8, .irq_parent = 66 },
- { .exti = 9, .irq_parent = 67 },
- { .exti = 10, .irq_parent = 40 },
- { .exti = 11, .irq_parent = 42 },
- { .exti = 12, .irq_parent = 76 },
- { .exti = 13, .irq_parent = 77 },
- { .exti = 14, .irq_parent = 121 },
- { .exti = 15, .irq_parent = 127 },
- { .exti = 16, .irq_parent = 1 },
- { .exti = 19, .irq_parent = 3 },
- { .exti = 21, .irq_parent = 31 },
- { .exti = 22, .irq_parent = 33 },
- { .exti = 23, .irq_parent = 72 },
- { .exti = 24, .irq_parent = 95 },
- { .exti = 25, .irq_parent = 107 },
- { .exti = 26, .irq_parent = 37 },
- { .exti = 27, .irq_parent = 38 },
- { .exti = 28, .irq_parent = 39 },
- { .exti = 29, .irq_parent = 71 },
- { .exti = 30, .irq_parent = 52 },
- { .exti = 31, .irq_parent = 53 },
- { .exti = 32, .irq_parent = 82 },
- { .exti = 33, .irq_parent = 83 },
- { .exti = 47, .irq_parent = 93 },
- { .exti = 48, .irq_parent = 138 },
- { .exti = 50, .irq_parent = 139 },
- { .exti = 52, .irq_parent = 140 },
- { .exti = 53, .irq_parent = 141 },
- { .exti = 54, .irq_parent = 135 },
- { .exti = 61, .irq_parent = 100 },
- { .exti = 65, .irq_parent = 144 },
- { .exti = 68, .irq_parent = 143 },
- { .exti = 70, .irq_parent = 62 },
- { .exti = 73, .irq_parent = 129 },
+#define EXTI_INVALID_IRQ U8_MAX
+#define STM32MP1_DESC_IRQ_SIZE (ARRAY_SIZE(stm32mp1_exti_banks) * IRQS_PER_BANK)
+
+static const u8 stm32mp1_desc_irq[] = {
+ /* default value */
+ [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] = EXTI_INVALID_IRQ,
+
+ [0] = 6,
+ [1] = 7,
+ [2] = 8,
+ [3] = 9,
+ [4] = 10,
+ [5] = 23,
+ [6] = 64,
+ [7] = 65,
+ [8] = 66,
+ [9] = 67,
+ [10] = 40,
+ [11] = 42,
+ [12] = 76,
+ [13] = 77,
+ [14] = 121,
+ [15] = 127,
+ [16] = 1,
+ [19] = 3,
+ [21] = 31,
+ [22] = 33,
+ [23] = 72,
+ [24] = 95,
+ [25] = 107,
+ [26] = 37,
+ [27] = 38,
+ [28] = 39,
+ [29] = 71,
+ [30] = 52,
+ [31] = 53,
+ [32] = 82,
+ [33] = 83,
+ [47] = 93,
+ [48] = 138,
+ [50] = 139,
+ [52] = 140,
+ [53] = 141,
+ [54] = 135,
+ [61] = 100,
+ [65] = 144,
+ [68] = 143,
+ [70] = 62,
+ [73] = 129,
};

-static const struct stm32_desc_irq stm32mp13_desc_irq[] = {
- { .exti = 0, .irq_parent = 6 },
- { .exti = 1, .irq_parent = 7 },
- { .exti = 2, .irq_parent = 8 },
- { .exti = 3, .irq_parent = 9 },
- { .exti = 4, .irq_parent = 10 },
- { .exti = 5, .irq_parent = 24 },
- { .exti = 6, .irq_parent = 65 },
- { .exti = 7, .irq_parent = 66 },
- { .exti = 8, .irq_parent = 67 },
- { .exti = 9, .irq_parent = 68 },
- { .exti = 10, .irq_parent = 41 },
- { .exti = 11, .irq_parent = 43 },
- { .exti = 12, .irq_parent = 77 },
- { .exti = 13, .irq_parent = 78 },
- { .exti = 14, .irq_parent = 106 },
- { .exti = 15, .irq_parent = 109 },
- { .exti = 16, .irq_parent = 1 },
- { .exti = 19, .irq_parent = 3 },
- { .exti = 21, .irq_parent = 32 },
- { .exti = 22, .irq_parent = 34 },
- { .exti = 23, .irq_parent = 73 },
- { .exti = 24, .irq_parent = 93 },
- { .exti = 25, .irq_parent = 114 },
- { .exti = 26, .irq_parent = 38 },
- { .exti = 27, .irq_parent = 39 },
- { .exti = 28, .irq_parent = 40 },
- { .exti = 29, .irq_parent = 72 },
- { .exti = 30, .irq_parent = 53 },
- { .exti = 31, .irq_parent = 54 },
- { .exti = 32, .irq_parent = 83 },
- { .exti = 33, .irq_parent = 84 },
- { .exti = 44, .irq_parent = 96 },
- { .exti = 47, .irq_parent = 92 },
- { .exti = 48, .irq_parent = 116 },
- { .exti = 50, .irq_parent = 117 },
- { .exti = 52, .irq_parent = 118 },
- { .exti = 53, .irq_parent = 119 },
- { .exti = 68, .irq_parent = 63 },
- { .exti = 70, .irq_parent = 98 },
+static const u8 stm32mp13_desc_irq[] = {
+ /* default value */
+ [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] = EXTI_INVALID_IRQ,
+
+ [0] = 6,
+ [1] = 7,
+ [2] = 8,
+ [3] = 9,
+ [4] = 10,
+ [5] = 24,
+ [6] = 65,
+ [7] = 66,
+ [8] = 67,
+ [9] = 68,
+ [10] = 41,
+ [11] = 43,
+ [12] = 77,
+ [13] = 78,
+ [14] = 106,
+ [15] = 109,
+ [16] = 1,
+ [19] = 3,
+ [21] = 32,
+ [22] = 34,
+ [23] = 73,
+ [24] = 93,
+ [25] = 114,
+ [26] = 38,
+ [27] = 39,
+ [28] = 40,
+ [29] = 72,
+ [30] = 53,
+ [31] = 54,
+ [32] = 83,
+ [33] = 84,
+ [44] = 96,
+ [47] = 92,
+ [48] = 116,
+ [50] = 117,
+ [52] = 118,
+ [53] = 119,
+ [68] = 63,
+ [70] = 98,
};

static const struct stm32_exti_drv_data stm32mp1_drv_data = {
.exti_banks = stm32mp1_exti_banks,
.bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
.desc_irqs = stm32mp1_desc_irq,
- .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq),
};

static const struct stm32_exti_drv_data stm32mp13_drv_data = {
.exti_banks = stm32mp1_exti_banks,
.bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
.desc_irqs = stm32mp13_desc_irq,
- .irq_nr = ARRAY_SIZE(stm32mp13_desc_irq),
};

-static const struct
-stm32_desc_irq *stm32_exti_get_desc(const struct stm32_exti_drv_data *drv_data,
- irq_hw_number_t hwirq)
-{
- const struct stm32_desc_irq *desc = NULL;
- int i;
-
- if (!drv_data->desc_irqs)
- return NULL;
-
- for (i = 0; i < drv_data->irq_nr; i++) {
- desc = &drv_data->desc_irqs[i];
- if (desc->exti == hwirq)
- break;
- }
-
- return desc;
-}
-
static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
{
struct stm32_exti_chip_data *chip_data = gc->private;
@@ -713,7 +695,7 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
{
struct stm32_exti_host_data *host_data = dm->host_data;
struct stm32_exti_chip_data *chip_data;
- const struct stm32_desc_irq *desc;
+ u8 desc_irq;
struct irq_fwspec *fwspec = data;
struct irq_fwspec p_fwspec;
irq_hw_number_t hwirq;
@@ -728,21 +710,21 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
bank = hwirq / IRQS_PER_BANK;
chip_data = &host_data->chips_data[bank];

-
- desc = stm32_exti_get_desc(host_data->drv_data, hwirq);
- if (!desc)
- return -EINVAL;
-
event_trg = readl_relaxed(host_data->base + chip_data->reg_bank->trg_ofst);
chip = (event_trg & BIT(hwirq % IRQS_PER_BANK)) ?
&stm32_exti_h_chip : &stm32_exti_h_chip_direct;

irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data);
- if (desc->irq_parent) {
+
+ if (!host_data->drv_data || !host_data->drv_data->desc_irqs)
+ return -EINVAL;
+
+ desc_irq = host_data->drv_data->desc_irqs[hwirq];
+ if (desc_irq != EXTI_INVALID_IRQ) {
p_fwspec.fwnode = dm->parent->fwnode;
p_fwspec.param_count = 3;
p_fwspec.param[0] = GIC_SPI;
- p_fwspec.param[1] = desc->irq_parent;
+ p_fwspec.param[1] = desc_irq;
p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;

return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);
--
2.36.1

2022-06-06 16:47:53

by Antonio Borneo

[permalink] [raw]
Subject: [PATCH v2 5/6] irqchip/stm32-exti: Read event trigger type from event_trg register

The flag reporting whether an event is 'direct' or 'configurable'
is available in the read-only registers EVENT_TRG.

Drop this redundant information from the struct stm32_desc_irq and
use the proper bit from EVENT_TRG register.
On armv7a this patch reduces by 3% the size of the driver, from
text data bss dec hex filename
7233 424 4 7661 1ded irq-stm32-exti.o
to
6977 424 4 7405 1ced irq-stm32-exti.o

Signed-off-by: Antonio Borneo <[email protected]>
---
drivers/irqchip/irq-stm32-exti.c | 180 ++++++++++++++++---------------
1 file changed, 96 insertions(+), 84 deletions(-)

diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index e8fa91bda4ba..045589627e67 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -34,6 +34,7 @@ struct stm32_exti_bank {
u32 swier_ofst;
u32 rpr_ofst;
u32 fpr_ofst;
+ u32 trg_ofst;
};

#define UNDEF_REG ~0
@@ -41,7 +42,6 @@ struct stm32_exti_bank {
struct stm32_desc_irq {
u32 exti;
u32 irq_parent;
- struct irq_chip *chip;
};

struct stm32_exti_drv_data {
@@ -78,6 +78,7 @@ static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
.swier_ofst = 0x10,
.rpr_ofst = 0x14,
.fpr_ofst = UNDEF_REG,
+ .trg_ofst = UNDEF_REG,
};

static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
@@ -97,6 +98,7 @@ static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
.swier_ofst = 0x08,
.rpr_ofst = 0x88,
.fpr_ofst = UNDEF_REG,
+ .trg_ofst = UNDEF_REG,
};

static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
@@ -107,6 +109,7 @@ static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
.swier_ofst = 0x28,
.rpr_ofst = 0x98,
.fpr_ofst = UNDEF_REG,
+ .trg_ofst = UNDEF_REG,
};

static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
@@ -117,6 +120,7 @@ static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
.swier_ofst = 0x48,
.rpr_ofst = 0xA8,
.fpr_ofst = UNDEF_REG,
+ .trg_ofst = UNDEF_REG,
};

static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
@@ -138,6 +142,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b1 = {
.swier_ofst = 0x08,
.rpr_ofst = 0x0C,
.fpr_ofst = 0x10,
+ .trg_ofst = 0x3EC,
};

static const struct stm32_exti_bank stm32mp1_exti_b2 = {
@@ -148,6 +153,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b2 = {
.swier_ofst = 0x28,
.rpr_ofst = 0x2C,
.fpr_ofst = 0x30,
+ .trg_ofst = 0x3E8,
};

static const struct stm32_exti_bank stm32mp1_exti_b3 = {
@@ -158,6 +164,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b3 = {
.swier_ofst = 0x48,
.rpr_ofst = 0x4C,
.fpr_ofst = 0x50,
+ .trg_ofst = 0x3E4,
};

static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
@@ -170,90 +177,90 @@ static struct irq_chip stm32_exti_h_chip;
static struct irq_chip stm32_exti_h_chip_direct;

static const struct stm32_desc_irq stm32mp1_desc_irq[] = {
- { .exti = 0, .irq_parent = 6, .chip = &stm32_exti_h_chip },
- { .exti = 1, .irq_parent = 7, .chip = &stm32_exti_h_chip },
- { .exti = 2, .irq_parent = 8, .chip = &stm32_exti_h_chip },
- { .exti = 3, .irq_parent = 9, .chip = &stm32_exti_h_chip },
- { .exti = 4, .irq_parent = 10, .chip = &stm32_exti_h_chip },
- { .exti = 5, .irq_parent = 23, .chip = &stm32_exti_h_chip },
- { .exti = 6, .irq_parent = 64, .chip = &stm32_exti_h_chip },
- { .exti = 7, .irq_parent = 65, .chip = &stm32_exti_h_chip },
- { .exti = 8, .irq_parent = 66, .chip = &stm32_exti_h_chip },
- { .exti = 9, .irq_parent = 67, .chip = &stm32_exti_h_chip },
- { .exti = 10, .irq_parent = 40, .chip = &stm32_exti_h_chip },
- { .exti = 11, .irq_parent = 42, .chip = &stm32_exti_h_chip },
- { .exti = 12, .irq_parent = 76, .chip = &stm32_exti_h_chip },
- { .exti = 13, .irq_parent = 77, .chip = &stm32_exti_h_chip },
- { .exti = 14, .irq_parent = 121, .chip = &stm32_exti_h_chip },
- { .exti = 15, .irq_parent = 127, .chip = &stm32_exti_h_chip },
- { .exti = 16, .irq_parent = 1, .chip = &stm32_exti_h_chip },
- { .exti = 19, .irq_parent = 3, .chip = &stm32_exti_h_chip_direct },
- { .exti = 21, .irq_parent = 31, .chip = &stm32_exti_h_chip_direct },
- { .exti = 22, .irq_parent = 33, .chip = &stm32_exti_h_chip_direct },
- { .exti = 23, .irq_parent = 72, .chip = &stm32_exti_h_chip_direct },
- { .exti = 24, .irq_parent = 95, .chip = &stm32_exti_h_chip_direct },
- { .exti = 25, .irq_parent = 107, .chip = &stm32_exti_h_chip_direct },
- { .exti = 26, .irq_parent = 37, .chip = &stm32_exti_h_chip_direct },
- { .exti = 27, .irq_parent = 38, .chip = &stm32_exti_h_chip_direct },
- { .exti = 28, .irq_parent = 39, .chip = &stm32_exti_h_chip_direct },
- { .exti = 29, .irq_parent = 71, .chip = &stm32_exti_h_chip_direct },
- { .exti = 30, .irq_parent = 52, .chip = &stm32_exti_h_chip_direct },
- { .exti = 31, .irq_parent = 53, .chip = &stm32_exti_h_chip_direct },
- { .exti = 32, .irq_parent = 82, .chip = &stm32_exti_h_chip_direct },
- { .exti = 33, .irq_parent = 83, .chip = &stm32_exti_h_chip_direct },
- { .exti = 47, .irq_parent = 93, .chip = &stm32_exti_h_chip_direct },
- { .exti = 48, .irq_parent = 138, .chip = &stm32_exti_h_chip_direct },
- { .exti = 50, .irq_parent = 139, .chip = &stm32_exti_h_chip_direct },
- { .exti = 52, .irq_parent = 140, .chip = &stm32_exti_h_chip_direct },
- { .exti = 53, .irq_parent = 141, .chip = &stm32_exti_h_chip_direct },
- { .exti = 54, .irq_parent = 135, .chip = &stm32_exti_h_chip_direct },
- { .exti = 61, .irq_parent = 100, .chip = &stm32_exti_h_chip_direct },
- { .exti = 65, .irq_parent = 144, .chip = &stm32_exti_h_chip },
- { .exti = 68, .irq_parent = 143, .chip = &stm32_exti_h_chip },
- { .exti = 70, .irq_parent = 62, .chip = &stm32_exti_h_chip_direct },
- { .exti = 73, .irq_parent = 129, .chip = &stm32_exti_h_chip },
+ { .exti = 0, .irq_parent = 6 },
+ { .exti = 1, .irq_parent = 7 },
+ { .exti = 2, .irq_parent = 8 },
+ { .exti = 3, .irq_parent = 9 },
+ { .exti = 4, .irq_parent = 10 },
+ { .exti = 5, .irq_parent = 23 },
+ { .exti = 6, .irq_parent = 64 },
+ { .exti = 7, .irq_parent = 65 },
+ { .exti = 8, .irq_parent = 66 },
+ { .exti = 9, .irq_parent = 67 },
+ { .exti = 10, .irq_parent = 40 },
+ { .exti = 11, .irq_parent = 42 },
+ { .exti = 12, .irq_parent = 76 },
+ { .exti = 13, .irq_parent = 77 },
+ { .exti = 14, .irq_parent = 121 },
+ { .exti = 15, .irq_parent = 127 },
+ { .exti = 16, .irq_parent = 1 },
+ { .exti = 19, .irq_parent = 3 },
+ { .exti = 21, .irq_parent = 31 },
+ { .exti = 22, .irq_parent = 33 },
+ { .exti = 23, .irq_parent = 72 },
+ { .exti = 24, .irq_parent = 95 },
+ { .exti = 25, .irq_parent = 107 },
+ { .exti = 26, .irq_parent = 37 },
+ { .exti = 27, .irq_parent = 38 },
+ { .exti = 28, .irq_parent = 39 },
+ { .exti = 29, .irq_parent = 71 },
+ { .exti = 30, .irq_parent = 52 },
+ { .exti = 31, .irq_parent = 53 },
+ { .exti = 32, .irq_parent = 82 },
+ { .exti = 33, .irq_parent = 83 },
+ { .exti = 47, .irq_parent = 93 },
+ { .exti = 48, .irq_parent = 138 },
+ { .exti = 50, .irq_parent = 139 },
+ { .exti = 52, .irq_parent = 140 },
+ { .exti = 53, .irq_parent = 141 },
+ { .exti = 54, .irq_parent = 135 },
+ { .exti = 61, .irq_parent = 100 },
+ { .exti = 65, .irq_parent = 144 },
+ { .exti = 68, .irq_parent = 143 },
+ { .exti = 70, .irq_parent = 62 },
+ { .exti = 73, .irq_parent = 129 },
};

static const struct stm32_desc_irq stm32mp13_desc_irq[] = {
- { .exti = 0, .irq_parent = 6, .chip = &stm32_exti_h_chip },
- { .exti = 1, .irq_parent = 7, .chip = &stm32_exti_h_chip },
- { .exti = 2, .irq_parent = 8, .chip = &stm32_exti_h_chip },
- { .exti = 3, .irq_parent = 9, .chip = &stm32_exti_h_chip },
- { .exti = 4, .irq_parent = 10, .chip = &stm32_exti_h_chip },
- { .exti = 5, .irq_parent = 24, .chip = &stm32_exti_h_chip },
- { .exti = 6, .irq_parent = 65, .chip = &stm32_exti_h_chip },
- { .exti = 7, .irq_parent = 66, .chip = &stm32_exti_h_chip },
- { .exti = 8, .irq_parent = 67, .chip = &stm32_exti_h_chip },
- { .exti = 9, .irq_parent = 68, .chip = &stm32_exti_h_chip },
- { .exti = 10, .irq_parent = 41, .chip = &stm32_exti_h_chip },
- { .exti = 11, .irq_parent = 43, .chip = &stm32_exti_h_chip },
- { .exti = 12, .irq_parent = 77, .chip = &stm32_exti_h_chip },
- { .exti = 13, .irq_parent = 78, .chip = &stm32_exti_h_chip },
- { .exti = 14, .irq_parent = 106, .chip = &stm32_exti_h_chip },
- { .exti = 15, .irq_parent = 109, .chip = &stm32_exti_h_chip },
- { .exti = 16, .irq_parent = 1, .chip = &stm32_exti_h_chip },
- { .exti = 19, .irq_parent = 3, .chip = &stm32_exti_h_chip_direct },
- { .exti = 21, .irq_parent = 32, .chip = &stm32_exti_h_chip_direct },
- { .exti = 22, .irq_parent = 34, .chip = &stm32_exti_h_chip_direct },
- { .exti = 23, .irq_parent = 73, .chip = &stm32_exti_h_chip_direct },
- { .exti = 24, .irq_parent = 93, .chip = &stm32_exti_h_chip_direct },
- { .exti = 25, .irq_parent = 114, .chip = &stm32_exti_h_chip_direct },
- { .exti = 26, .irq_parent = 38, .chip = &stm32_exti_h_chip_direct },
- { .exti = 27, .irq_parent = 39, .chip = &stm32_exti_h_chip_direct },
- { .exti = 28, .irq_parent = 40, .chip = &stm32_exti_h_chip_direct },
- { .exti = 29, .irq_parent = 72, .chip = &stm32_exti_h_chip_direct },
- { .exti = 30, .irq_parent = 53, .chip = &stm32_exti_h_chip_direct },
- { .exti = 31, .irq_parent = 54, .chip = &stm32_exti_h_chip_direct },
- { .exti = 32, .irq_parent = 83, .chip = &stm32_exti_h_chip_direct },
- { .exti = 33, .irq_parent = 84, .chip = &stm32_exti_h_chip_direct },
- { .exti = 44, .irq_parent = 96, .chip = &stm32_exti_h_chip_direct },
- { .exti = 47, .irq_parent = 92, .chip = &stm32_exti_h_chip_direct },
- { .exti = 48, .irq_parent = 116, .chip = &stm32_exti_h_chip_direct },
- { .exti = 50, .irq_parent = 117, .chip = &stm32_exti_h_chip_direct },
- { .exti = 52, .irq_parent = 118, .chip = &stm32_exti_h_chip_direct },
- { .exti = 53, .irq_parent = 119, .chip = &stm32_exti_h_chip_direct },
- { .exti = 68, .irq_parent = 63, .chip = &stm32_exti_h_chip_direct },
- { .exti = 70, .irq_parent = 98, .chip = &stm32_exti_h_chip_direct },
+ { .exti = 0, .irq_parent = 6 },
+ { .exti = 1, .irq_parent = 7 },
+ { .exti = 2, .irq_parent = 8 },
+ { .exti = 3, .irq_parent = 9 },
+ { .exti = 4, .irq_parent = 10 },
+ { .exti = 5, .irq_parent = 24 },
+ { .exti = 6, .irq_parent = 65 },
+ { .exti = 7, .irq_parent = 66 },
+ { .exti = 8, .irq_parent = 67 },
+ { .exti = 9, .irq_parent = 68 },
+ { .exti = 10, .irq_parent = 41 },
+ { .exti = 11, .irq_parent = 43 },
+ { .exti = 12, .irq_parent = 77 },
+ { .exti = 13, .irq_parent = 78 },
+ { .exti = 14, .irq_parent = 106 },
+ { .exti = 15, .irq_parent = 109 },
+ { .exti = 16, .irq_parent = 1 },
+ { .exti = 19, .irq_parent = 3 },
+ { .exti = 21, .irq_parent = 32 },
+ { .exti = 22, .irq_parent = 34 },
+ { .exti = 23, .irq_parent = 73 },
+ { .exti = 24, .irq_parent = 93 },
+ { .exti = 25, .irq_parent = 114 },
+ { .exti = 26, .irq_parent = 38 },
+ { .exti = 27, .irq_parent = 39 },
+ { .exti = 28, .irq_parent = 40 },
+ { .exti = 29, .irq_parent = 72 },
+ { .exti = 30, .irq_parent = 53 },
+ { .exti = 31, .irq_parent = 54 },
+ { .exti = 32, .irq_parent = 83 },
+ { .exti = 33, .irq_parent = 84 },
+ { .exti = 44, .irq_parent = 96 },
+ { .exti = 47, .irq_parent = 92 },
+ { .exti = 48, .irq_parent = 116 },
+ { .exti = 50, .irq_parent = 117 },
+ { .exti = 52, .irq_parent = 118 },
+ { .exti = 53, .irq_parent = 119 },
+ { .exti = 68, .irq_parent = 63 },
+ { .exti = 70, .irq_parent = 98 },
};

static const struct stm32_exti_drv_data stm32mp1_drv_data = {
@@ -711,6 +718,8 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
struct irq_fwspec p_fwspec;
irq_hw_number_t hwirq;
int bank;
+ u32 event_trg;
+ struct irq_chip *chip;

hwirq = fwspec->param[0];
if (hwirq >= host_data->drv_data->bank_nr * IRQS_PER_BANK)
@@ -724,8 +733,11 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
if (!desc)
return -EINVAL;

- irq_domain_set_hwirq_and_chip(dm, virq, hwirq, desc->chip,
- chip_data);
+ event_trg = readl_relaxed(host_data->base + chip_data->reg_bank->trg_ofst);
+ chip = (event_trg & BIT(hwirq % IRQS_PER_BANK)) ?
+ &stm32_exti_h_chip : &stm32_exti_h_chip_direct;
+
+ irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data);
if (desc->irq_parent) {
p_fwspec.fwnode = dm->parent->fwnode;
p_fwspec.param_count = 3;
--
2.36.1

2022-07-04 13:47:13

by Antonio Borneo

[permalink] [raw]
Subject: Re: [PATCH v2 0/6] irqchip/stm32-exti: Fixes and simplifications

On Mon, 2022-06-06 at 18:27 +0200, Antonio Borneo wrote:
> This series address some code fix for irq-stm32-exti driver and
> simplifies the table that remaps the interrupts from exti to gic.
>

Gentle ping for this series.
If there is anything I can do to let this series proceed, please let me
know.

Thanks,
Antonio

> v1->v2
>  - Properly format the commit title and expand the commit msg;
>  - drop the patch v1 4/7:
>    "irqchip/stm32-exti: forward irq_request_resources to parent"
>    in favor of the generic:
>   
> https://lore.kernel.org/lkml/[email protected]/
>    "genirq: Don't return error on missing optional
>    irq_request_resources()";
>  - use consistently UNDEF_REG for non existing EMR registers;
>  - rebase on v5.19-rc1.
>
>
> Alexandre Torgue (1):
>   irqchip/stm32-exti: Tag emr register as undefined for stm32mp15
>
> Antonio Borneo (3):
>   irqchip/stm32-exti: Prevent illegal read due to unbounded DT value
>   irqchip/stm32-exti: Read event trigger type from event_trg register
>   irqchip/stm32-exti: Simplify irq description table
>
> Loic Pallardy (1):
>   irqchip/stm32-exti: Fix irq_mask/irq_unmask for direct events
>
> Ludovic Barre (1):
>   irqchip/stm32-exti: Fix irq_set_affinity return value
>
>  drivers/irqchip/irq-stm32-exti.c | 250 +++++++++++++++--------------
> --
>  1 file changed, 124 insertions(+), 126 deletions(-)
>
>
> base-commit: f2906aa863381afb0015a9eb7fefad885d4e5a56

Subject: [irqchip: irq/irqchip-next] irqchip/stm32-exti: Tag emr register as undefined for stm32mp15

The following commit has been merged into the irq/irqchip-next branch of irqchip:

Commit-ID: b38040f0167d25092e813c8d1a70cf2708c1720b
Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/b38040f0167d25092e813c8d1a70cf2708c1720b
Author: Alexandre Torgue <[email protected]>
AuthorDate: Mon, 06 Jun 2022 18:27:55 +02:00
Committer: Marc Zyngier <[email protected]>
CommitterDate: Thu, 07 Jul 2022 09:07:44 +01:00

irqchip/stm32-exti: Tag emr register as undefined for stm32mp15

The reference manual RM0436 of stm32mp15 till version v4.0 was
erroneously reporting the Event Mask Registers (EMR) for the
Cortex-A CPUs.
These registers have been removed from v5.0 of the manual and the
corresponding offsets have been marked as 'Reserved'.

Prevent accessing these reserved addresses by tagging the EMR
offsets as UNDEF_REG and modifying the code to handle this case.

Signed-off-by: Alexandre Torgue <[email protected]>
Signed-off-by: Antonio Borneo <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
---
drivers/irqchip/irq-stm32-exti.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index e2722e4..e8fa91b 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -132,7 +132,7 @@ static const struct stm32_exti_drv_data stm32h7xx_drv_data = {

static const struct stm32_exti_bank stm32mp1_exti_b1 = {
.imr_ofst = 0x80,
- .emr_ofst = 0x84,
+ .emr_ofst = UNDEF_REG,
.rtsr_ofst = 0x00,
.ftsr_ofst = 0x04,
.swier_ofst = 0x08,
@@ -142,7 +142,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b1 = {

static const struct stm32_exti_bank stm32mp1_exti_b2 = {
.imr_ofst = 0x90,
- .emr_ofst = 0x94,
+ .emr_ofst = UNDEF_REG,
.rtsr_ofst = 0x20,
.ftsr_ofst = 0x24,
.swier_ofst = 0x28,
@@ -152,7 +152,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b2 = {

static const struct stm32_exti_bank stm32mp1_exti_b3 = {
.imr_ofst = 0xA0,
- .emr_ofst = 0xA4,
+ .emr_ofst = UNDEF_REG,
.rtsr_ofst = 0x40,
.ftsr_ofst = 0x44,
.swier_ofst = 0x48,
@@ -795,7 +795,8 @@ stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data,
* clear registers to avoid residue
*/
writel_relaxed(0, base + stm32_bank->imr_ofst);
- writel_relaxed(0, base + stm32_bank->emr_ofst);
+ if (stm32_bank->emr_ofst != UNDEF_REG)
+ writel_relaxed(0, base + stm32_bank->emr_ofst);

pr_info("%pOF: bank%d\n", node, bank_idx);

Subject: [irqchip: irq/irqchip-next] irqchip/stm32-exti: Fix irq_set_affinity return value

The following commit has been merged into the irq/irqchip-next branch of irqchip:

Commit-ID: 3e17683ff4a870ed99e989425bc976a944978711
Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/3e17683ff4a870ed99e989425bc976a944978711
Author: Ludovic Barre <[email protected]>
AuthorDate: Mon, 06 Jun 2022 18:27:52 +02:00
Committer: Marc Zyngier <[email protected]>
CommitterDate: Thu, 07 Jul 2022 09:07:44 +01:00

irqchip/stm32-exti: Fix irq_set_affinity return value

When there is no parent, there is no specific action to do in
stm32-exti irqchip. In such case, it's incorrect returning an
error.

Let irq_set_affinity to return IRQ_SET_MASK_OK_DONE when there is
no parent.

Signed-off-by: Ludovic Barre <[email protected]>
Signed-off-by: Antonio Borneo <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
---
drivers/irqchip/irq-stm32-exti.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index 9d18f47..10c9c74 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -614,7 +614,7 @@ static int stm32_exti_h_set_affinity(struct irq_data *d,
if (d->parent_data->chip)
return irq_chip_set_affinity_parent(d, dest, force);

- return -EINVAL;
+ return IRQ_SET_MASK_OK_DONE;
}

static int __maybe_unused stm32_exti_h_suspend(void)

Subject: [irqchip: irq/irqchip-next] irqchip/stm32-exti: Fix irq_mask/irq_unmask for direct events

The following commit has been merged into the irq/irqchip-next branch of irqchip:

Commit-ID: f8b3eb4245113c8a9156d5db8e80c6134127bcc1
Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/f8b3eb4245113c8a9156d5db8e80c6134127bcc1
Author: Loic Pallardy <[email protected]>
AuthorDate: Mon, 06 Jun 2022 18:27:53 +02:00
Committer: Marc Zyngier <[email protected]>
CommitterDate: Thu, 07 Jul 2022 09:07:44 +01:00

irqchip/stm32-exti: Fix irq_mask/irq_unmask for direct events

The driver has to mask/unmask the corresponding flag in the
Interrupt Mask Register (IMR).
This is already done for configurable event, while direct events
only forward the mask/unmask request to the parent.

Use the existing stm32_exti_h_mask()/stm32_exti_h_unmask() for
direct events too.

Signed-off-by: Loic Pallardy <[email protected]>
Signed-off-by: Antonio Borneo <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
---
drivers/irqchip/irq-stm32-exti.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index 10c9c74..1145f06 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -691,8 +691,8 @@ static struct irq_chip stm32_exti_h_chip_direct = {
.name = "stm32-exti-h-direct",
.irq_eoi = irq_chip_eoi_parent,
.irq_ack = irq_chip_ack_parent,
- .irq_mask = irq_chip_mask_parent,
- .irq_unmask = irq_chip_unmask_parent,
+ .irq_mask = stm32_exti_h_mask,
+ .irq_unmask = stm32_exti_h_unmask,
.irq_retrigger = irq_chip_retrigger_hierarchy,
.irq_set_type = irq_chip_set_type_parent,
.irq_set_wake = stm32_exti_h_set_wake,

Subject: [irqchip: irq/irqchip-next] irqchip/stm32-exti: Read event trigger type from event_trg register

The following commit has been merged into the irq/irqchip-next branch of irqchip:

Commit-ID: ce4ef8f9f2abcf104a5417225cbfe3560e779093
Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/ce4ef8f9f2abcf104a5417225cbfe3560e779093
Author: Antonio Borneo <[email protected]>
AuthorDate: Mon, 06 Jun 2022 18:27:56 +02:00
Committer: Marc Zyngier <[email protected]>
CommitterDate: Thu, 07 Jul 2022 09:07:44 +01:00

irqchip/stm32-exti: Read event trigger type from event_trg register

The flag reporting whether an event is 'direct' or 'configurable'
is available in the read-only registers EVENT_TRG.

Drop this redundant information from the struct stm32_desc_irq and
use the proper bit from EVENT_TRG register.
On armv7a this patch reduces by 3% the size of the driver, from
text data bss dec hex filename
7233 424 4 7661 1ded irq-stm32-exti.o
to
6977 424 4 7405 1ced irq-stm32-exti.o

Signed-off-by: Antonio Borneo <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
---
drivers/irqchip/irq-stm32-exti.c | 180 ++++++++++++++++--------------
1 file changed, 96 insertions(+), 84 deletions(-)

diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index e8fa91b..0455896 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -34,6 +34,7 @@ struct stm32_exti_bank {
u32 swier_ofst;
u32 rpr_ofst;
u32 fpr_ofst;
+ u32 trg_ofst;
};

#define UNDEF_REG ~0
@@ -41,7 +42,6 @@ struct stm32_exti_bank {
struct stm32_desc_irq {
u32 exti;
u32 irq_parent;
- struct irq_chip *chip;
};

struct stm32_exti_drv_data {
@@ -78,6 +78,7 @@ static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
.swier_ofst = 0x10,
.rpr_ofst = 0x14,
.fpr_ofst = UNDEF_REG,
+ .trg_ofst = UNDEF_REG,
};

static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
@@ -97,6 +98,7 @@ static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
.swier_ofst = 0x08,
.rpr_ofst = 0x88,
.fpr_ofst = UNDEF_REG,
+ .trg_ofst = UNDEF_REG,
};

static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
@@ -107,6 +109,7 @@ static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
.swier_ofst = 0x28,
.rpr_ofst = 0x98,
.fpr_ofst = UNDEF_REG,
+ .trg_ofst = UNDEF_REG,
};

static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
@@ -117,6 +120,7 @@ static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
.swier_ofst = 0x48,
.rpr_ofst = 0xA8,
.fpr_ofst = UNDEF_REG,
+ .trg_ofst = UNDEF_REG,
};

static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
@@ -138,6 +142,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b1 = {
.swier_ofst = 0x08,
.rpr_ofst = 0x0C,
.fpr_ofst = 0x10,
+ .trg_ofst = 0x3EC,
};

static const struct stm32_exti_bank stm32mp1_exti_b2 = {
@@ -148,6 +153,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b2 = {
.swier_ofst = 0x28,
.rpr_ofst = 0x2C,
.fpr_ofst = 0x30,
+ .trg_ofst = 0x3E8,
};

static const struct stm32_exti_bank stm32mp1_exti_b3 = {
@@ -158,6 +164,7 @@ static const struct stm32_exti_bank stm32mp1_exti_b3 = {
.swier_ofst = 0x48,
.rpr_ofst = 0x4C,
.fpr_ofst = 0x50,
+ .trg_ofst = 0x3E4,
};

static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
@@ -170,90 +177,90 @@ static struct irq_chip stm32_exti_h_chip;
static struct irq_chip stm32_exti_h_chip_direct;

static const struct stm32_desc_irq stm32mp1_desc_irq[] = {
- { .exti = 0, .irq_parent = 6, .chip = &stm32_exti_h_chip },
- { .exti = 1, .irq_parent = 7, .chip = &stm32_exti_h_chip },
- { .exti = 2, .irq_parent = 8, .chip = &stm32_exti_h_chip },
- { .exti = 3, .irq_parent = 9, .chip = &stm32_exti_h_chip },
- { .exti = 4, .irq_parent = 10, .chip = &stm32_exti_h_chip },
- { .exti = 5, .irq_parent = 23, .chip = &stm32_exti_h_chip },
- { .exti = 6, .irq_parent = 64, .chip = &stm32_exti_h_chip },
- { .exti = 7, .irq_parent = 65, .chip = &stm32_exti_h_chip },
- { .exti = 8, .irq_parent = 66, .chip = &stm32_exti_h_chip },
- { .exti = 9, .irq_parent = 67, .chip = &stm32_exti_h_chip },
- { .exti = 10, .irq_parent = 40, .chip = &stm32_exti_h_chip },
- { .exti = 11, .irq_parent = 42, .chip = &stm32_exti_h_chip },
- { .exti = 12, .irq_parent = 76, .chip = &stm32_exti_h_chip },
- { .exti = 13, .irq_parent = 77, .chip = &stm32_exti_h_chip },
- { .exti = 14, .irq_parent = 121, .chip = &stm32_exti_h_chip },
- { .exti = 15, .irq_parent = 127, .chip = &stm32_exti_h_chip },
- { .exti = 16, .irq_parent = 1, .chip = &stm32_exti_h_chip },
- { .exti = 19, .irq_parent = 3, .chip = &stm32_exti_h_chip_direct },
- { .exti = 21, .irq_parent = 31, .chip = &stm32_exti_h_chip_direct },
- { .exti = 22, .irq_parent = 33, .chip = &stm32_exti_h_chip_direct },
- { .exti = 23, .irq_parent = 72, .chip = &stm32_exti_h_chip_direct },
- { .exti = 24, .irq_parent = 95, .chip = &stm32_exti_h_chip_direct },
- { .exti = 25, .irq_parent = 107, .chip = &stm32_exti_h_chip_direct },
- { .exti = 26, .irq_parent = 37, .chip = &stm32_exti_h_chip_direct },
- { .exti = 27, .irq_parent = 38, .chip = &stm32_exti_h_chip_direct },
- { .exti = 28, .irq_parent = 39, .chip = &stm32_exti_h_chip_direct },
- { .exti = 29, .irq_parent = 71, .chip = &stm32_exti_h_chip_direct },
- { .exti = 30, .irq_parent = 52, .chip = &stm32_exti_h_chip_direct },
- { .exti = 31, .irq_parent = 53, .chip = &stm32_exti_h_chip_direct },
- { .exti = 32, .irq_parent = 82, .chip = &stm32_exti_h_chip_direct },
- { .exti = 33, .irq_parent = 83, .chip = &stm32_exti_h_chip_direct },
- { .exti = 47, .irq_parent = 93, .chip = &stm32_exti_h_chip_direct },
- { .exti = 48, .irq_parent = 138, .chip = &stm32_exti_h_chip_direct },
- { .exti = 50, .irq_parent = 139, .chip = &stm32_exti_h_chip_direct },
- { .exti = 52, .irq_parent = 140, .chip = &stm32_exti_h_chip_direct },
- { .exti = 53, .irq_parent = 141, .chip = &stm32_exti_h_chip_direct },
- { .exti = 54, .irq_parent = 135, .chip = &stm32_exti_h_chip_direct },
- { .exti = 61, .irq_parent = 100, .chip = &stm32_exti_h_chip_direct },
- { .exti = 65, .irq_parent = 144, .chip = &stm32_exti_h_chip },
- { .exti = 68, .irq_parent = 143, .chip = &stm32_exti_h_chip },
- { .exti = 70, .irq_parent = 62, .chip = &stm32_exti_h_chip_direct },
- { .exti = 73, .irq_parent = 129, .chip = &stm32_exti_h_chip },
+ { .exti = 0, .irq_parent = 6 },
+ { .exti = 1, .irq_parent = 7 },
+ { .exti = 2, .irq_parent = 8 },
+ { .exti = 3, .irq_parent = 9 },
+ { .exti = 4, .irq_parent = 10 },
+ { .exti = 5, .irq_parent = 23 },
+ { .exti = 6, .irq_parent = 64 },
+ { .exti = 7, .irq_parent = 65 },
+ { .exti = 8, .irq_parent = 66 },
+ { .exti = 9, .irq_parent = 67 },
+ { .exti = 10, .irq_parent = 40 },
+ { .exti = 11, .irq_parent = 42 },
+ { .exti = 12, .irq_parent = 76 },
+ { .exti = 13, .irq_parent = 77 },
+ { .exti = 14, .irq_parent = 121 },
+ { .exti = 15, .irq_parent = 127 },
+ { .exti = 16, .irq_parent = 1 },
+ { .exti = 19, .irq_parent = 3 },
+ { .exti = 21, .irq_parent = 31 },
+ { .exti = 22, .irq_parent = 33 },
+ { .exti = 23, .irq_parent = 72 },
+ { .exti = 24, .irq_parent = 95 },
+ { .exti = 25, .irq_parent = 107 },
+ { .exti = 26, .irq_parent = 37 },
+ { .exti = 27, .irq_parent = 38 },
+ { .exti = 28, .irq_parent = 39 },
+ { .exti = 29, .irq_parent = 71 },
+ { .exti = 30, .irq_parent = 52 },
+ { .exti = 31, .irq_parent = 53 },
+ { .exti = 32, .irq_parent = 82 },
+ { .exti = 33, .irq_parent = 83 },
+ { .exti = 47, .irq_parent = 93 },
+ { .exti = 48, .irq_parent = 138 },
+ { .exti = 50, .irq_parent = 139 },
+ { .exti = 52, .irq_parent = 140 },
+ { .exti = 53, .irq_parent = 141 },
+ { .exti = 54, .irq_parent = 135 },
+ { .exti = 61, .irq_parent = 100 },
+ { .exti = 65, .irq_parent = 144 },
+ { .exti = 68, .irq_parent = 143 },
+ { .exti = 70, .irq_parent = 62 },
+ { .exti = 73, .irq_parent = 129 },
};

static const struct stm32_desc_irq stm32mp13_desc_irq[] = {
- { .exti = 0, .irq_parent = 6, .chip = &stm32_exti_h_chip },
- { .exti = 1, .irq_parent = 7, .chip = &stm32_exti_h_chip },
- { .exti = 2, .irq_parent = 8, .chip = &stm32_exti_h_chip },
- { .exti = 3, .irq_parent = 9, .chip = &stm32_exti_h_chip },
- { .exti = 4, .irq_parent = 10, .chip = &stm32_exti_h_chip },
- { .exti = 5, .irq_parent = 24, .chip = &stm32_exti_h_chip },
- { .exti = 6, .irq_parent = 65, .chip = &stm32_exti_h_chip },
- { .exti = 7, .irq_parent = 66, .chip = &stm32_exti_h_chip },
- { .exti = 8, .irq_parent = 67, .chip = &stm32_exti_h_chip },
- { .exti = 9, .irq_parent = 68, .chip = &stm32_exti_h_chip },
- { .exti = 10, .irq_parent = 41, .chip = &stm32_exti_h_chip },
- { .exti = 11, .irq_parent = 43, .chip = &stm32_exti_h_chip },
- { .exti = 12, .irq_parent = 77, .chip = &stm32_exti_h_chip },
- { .exti = 13, .irq_parent = 78, .chip = &stm32_exti_h_chip },
- { .exti = 14, .irq_parent = 106, .chip = &stm32_exti_h_chip },
- { .exti = 15, .irq_parent = 109, .chip = &stm32_exti_h_chip },
- { .exti = 16, .irq_parent = 1, .chip = &stm32_exti_h_chip },
- { .exti = 19, .irq_parent = 3, .chip = &stm32_exti_h_chip_direct },
- { .exti = 21, .irq_parent = 32, .chip = &stm32_exti_h_chip_direct },
- { .exti = 22, .irq_parent = 34, .chip = &stm32_exti_h_chip_direct },
- { .exti = 23, .irq_parent = 73, .chip = &stm32_exti_h_chip_direct },
- { .exti = 24, .irq_parent = 93, .chip = &stm32_exti_h_chip_direct },
- { .exti = 25, .irq_parent = 114, .chip = &stm32_exti_h_chip_direct },
- { .exti = 26, .irq_parent = 38, .chip = &stm32_exti_h_chip_direct },
- { .exti = 27, .irq_parent = 39, .chip = &stm32_exti_h_chip_direct },
- { .exti = 28, .irq_parent = 40, .chip = &stm32_exti_h_chip_direct },
- { .exti = 29, .irq_parent = 72, .chip = &stm32_exti_h_chip_direct },
- { .exti = 30, .irq_parent = 53, .chip = &stm32_exti_h_chip_direct },
- { .exti = 31, .irq_parent = 54, .chip = &stm32_exti_h_chip_direct },
- { .exti = 32, .irq_parent = 83, .chip = &stm32_exti_h_chip_direct },
- { .exti = 33, .irq_parent = 84, .chip = &stm32_exti_h_chip_direct },
- { .exti = 44, .irq_parent = 96, .chip = &stm32_exti_h_chip_direct },
- { .exti = 47, .irq_parent = 92, .chip = &stm32_exti_h_chip_direct },
- { .exti = 48, .irq_parent = 116, .chip = &stm32_exti_h_chip_direct },
- { .exti = 50, .irq_parent = 117, .chip = &stm32_exti_h_chip_direct },
- { .exti = 52, .irq_parent = 118, .chip = &stm32_exti_h_chip_direct },
- { .exti = 53, .irq_parent = 119, .chip = &stm32_exti_h_chip_direct },
- { .exti = 68, .irq_parent = 63, .chip = &stm32_exti_h_chip_direct },
- { .exti = 70, .irq_parent = 98, .chip = &stm32_exti_h_chip_direct },
+ { .exti = 0, .irq_parent = 6 },
+ { .exti = 1, .irq_parent = 7 },
+ { .exti = 2, .irq_parent = 8 },
+ { .exti = 3, .irq_parent = 9 },
+ { .exti = 4, .irq_parent = 10 },
+ { .exti = 5, .irq_parent = 24 },
+ { .exti = 6, .irq_parent = 65 },
+ { .exti = 7, .irq_parent = 66 },
+ { .exti = 8, .irq_parent = 67 },
+ { .exti = 9, .irq_parent = 68 },
+ { .exti = 10, .irq_parent = 41 },
+ { .exti = 11, .irq_parent = 43 },
+ { .exti = 12, .irq_parent = 77 },
+ { .exti = 13, .irq_parent = 78 },
+ { .exti = 14, .irq_parent = 106 },
+ { .exti = 15, .irq_parent = 109 },
+ { .exti = 16, .irq_parent = 1 },
+ { .exti = 19, .irq_parent = 3 },
+ { .exti = 21, .irq_parent = 32 },
+ { .exti = 22, .irq_parent = 34 },
+ { .exti = 23, .irq_parent = 73 },
+ { .exti = 24, .irq_parent = 93 },
+ { .exti = 25, .irq_parent = 114 },
+ { .exti = 26, .irq_parent = 38 },
+ { .exti = 27, .irq_parent = 39 },
+ { .exti = 28, .irq_parent = 40 },
+ { .exti = 29, .irq_parent = 72 },
+ { .exti = 30, .irq_parent = 53 },
+ { .exti = 31, .irq_parent = 54 },
+ { .exti = 32, .irq_parent = 83 },
+ { .exti = 33, .irq_parent = 84 },
+ { .exti = 44, .irq_parent = 96 },
+ { .exti = 47, .irq_parent = 92 },
+ { .exti = 48, .irq_parent = 116 },
+ { .exti = 50, .irq_parent = 117 },
+ { .exti = 52, .irq_parent = 118 },
+ { .exti = 53, .irq_parent = 119 },
+ { .exti = 68, .irq_parent = 63 },
+ { .exti = 70, .irq_parent = 98 },
};

static const struct stm32_exti_drv_data stm32mp1_drv_data = {
@@ -711,6 +718,8 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
struct irq_fwspec p_fwspec;
irq_hw_number_t hwirq;
int bank;
+ u32 event_trg;
+ struct irq_chip *chip;

hwirq = fwspec->param[0];
if (hwirq >= host_data->drv_data->bank_nr * IRQS_PER_BANK)
@@ -724,8 +733,11 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
if (!desc)
return -EINVAL;

- irq_domain_set_hwirq_and_chip(dm, virq, hwirq, desc->chip,
- chip_data);
+ event_trg = readl_relaxed(host_data->base + chip_data->reg_bank->trg_ofst);
+ chip = (event_trg & BIT(hwirq % IRQS_PER_BANK)) ?
+ &stm32_exti_h_chip : &stm32_exti_h_chip_direct;
+
+ irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data);
if (desc->irq_parent) {
p_fwspec.fwnode = dm->parent->fwnode;
p_fwspec.param_count = 3;

Subject: [irqchip: irq/irqchip-next] irqchip/stm32-exti: Prevent illegal read due to unbounded DT value

The following commit has been merged into the irq/irqchip-next branch of irqchip:

Commit-ID: c16ae609214e835692c33b1a090b5a15bf1b9e7e
Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/c16ae609214e835692c33b1a090b5a15bf1b9e7e
Author: Antonio Borneo <[email protected]>
AuthorDate: Mon, 06 Jun 2022 18:27:54 +02:00
Committer: Marc Zyngier <[email protected]>
CommitterDate: Thu, 07 Jul 2022 09:07:44 +01:00

irqchip/stm32-exti: Prevent illegal read due to unbounded DT value

The value hwirq is received from DT. If it exceeds the maximum
valid value it causes the code to address unexisting irq chips
reading outside the array boundary.

Check the value of hwirq before using it.

Signed-off-by: Antonio Borneo <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
---
drivers/irqchip/irq-stm32-exti.c | 3 +++
1 file changed, 3 insertions(+)

diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index 1145f06..e2722e4 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -713,6 +713,9 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
int bank;

hwirq = fwspec->param[0];
+ if (hwirq >= host_data->drv_data->bank_nr * IRQS_PER_BANK)
+ return -EINVAL;
+
bank = hwirq / IRQS_PER_BANK;
chip_data = &host_data->chips_data[bank];

Subject: [irqchip: irq/irqchip-next] irqchip/stm32-exti: Simplify irq description table

The following commit has been merged into the irq/irqchip-next branch of irqchip:

Commit-ID: c297493336b7bc0c12ced484a9e61d04ec2d9403
Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/c297493336b7bc0c12ced484a9e61d04ec2d9403
Author: Antonio Borneo <[email protected]>
AuthorDate: Mon, 06 Jun 2022 18:27:57 +02:00
Committer: Marc Zyngier <[email protected]>
CommitterDate: Thu, 07 Jul 2022 09:07:44 +01:00

irqchip/stm32-exti: Simplify irq description table

Having removed the event trigger type from struct stm32_desc_irq
makes worthless keep using a struct.

Replace the struct by a single dimension array and use 8 bit type
to reduce the overal memory footprint.
On armv7a this patch reduces by 7% the size of the driver, from
text data bss dec hex filename
6977 424 4 7405 1ced irq-stm32-exti.o
to
6449 424 4 6877 1add irq-stm32-exti.o

Signed-off-by: Antonio Borneo <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
---
drivers/irqchip/irq-stm32-exti.c | 220 +++++++++++++-----------------
1 file changed, 101 insertions(+), 119 deletions(-)

diff --git a/drivers/irqchip/irq-stm32-exti.c b/drivers/irqchip/irq-stm32-exti.c
index 0455896..a73763d 100644
--- a/drivers/irqchip/irq-stm32-exti.c
+++ b/drivers/irqchip/irq-stm32-exti.c
@@ -39,16 +39,10 @@ struct stm32_exti_bank {

#define UNDEF_REG ~0

-struct stm32_desc_irq {
- u32 exti;
- u32 irq_parent;
-};
-
struct stm32_exti_drv_data {
const struct stm32_exti_bank **exti_banks;
- const struct stm32_desc_irq *desc_irqs;
+ const u8 *desc_irqs;
u32 bank_nr;
- u32 irq_nr;
};

struct stm32_exti_chip_data {
@@ -176,126 +170,114 @@ static const struct stm32_exti_bank *stm32mp1_exti_banks[] = {
static struct irq_chip stm32_exti_h_chip;
static struct irq_chip stm32_exti_h_chip_direct;

-static const struct stm32_desc_irq stm32mp1_desc_irq[] = {
- { .exti = 0, .irq_parent = 6 },
- { .exti = 1, .irq_parent = 7 },
- { .exti = 2, .irq_parent = 8 },
- { .exti = 3, .irq_parent = 9 },
- { .exti = 4, .irq_parent = 10 },
- { .exti = 5, .irq_parent = 23 },
- { .exti = 6, .irq_parent = 64 },
- { .exti = 7, .irq_parent = 65 },
- { .exti = 8, .irq_parent = 66 },
- { .exti = 9, .irq_parent = 67 },
- { .exti = 10, .irq_parent = 40 },
- { .exti = 11, .irq_parent = 42 },
- { .exti = 12, .irq_parent = 76 },
- { .exti = 13, .irq_parent = 77 },
- { .exti = 14, .irq_parent = 121 },
- { .exti = 15, .irq_parent = 127 },
- { .exti = 16, .irq_parent = 1 },
- { .exti = 19, .irq_parent = 3 },
- { .exti = 21, .irq_parent = 31 },
- { .exti = 22, .irq_parent = 33 },
- { .exti = 23, .irq_parent = 72 },
- { .exti = 24, .irq_parent = 95 },
- { .exti = 25, .irq_parent = 107 },
- { .exti = 26, .irq_parent = 37 },
- { .exti = 27, .irq_parent = 38 },
- { .exti = 28, .irq_parent = 39 },
- { .exti = 29, .irq_parent = 71 },
- { .exti = 30, .irq_parent = 52 },
- { .exti = 31, .irq_parent = 53 },
- { .exti = 32, .irq_parent = 82 },
- { .exti = 33, .irq_parent = 83 },
- { .exti = 47, .irq_parent = 93 },
- { .exti = 48, .irq_parent = 138 },
- { .exti = 50, .irq_parent = 139 },
- { .exti = 52, .irq_parent = 140 },
- { .exti = 53, .irq_parent = 141 },
- { .exti = 54, .irq_parent = 135 },
- { .exti = 61, .irq_parent = 100 },
- { .exti = 65, .irq_parent = 144 },
- { .exti = 68, .irq_parent = 143 },
- { .exti = 70, .irq_parent = 62 },
- { .exti = 73, .irq_parent = 129 },
+#define EXTI_INVALID_IRQ U8_MAX
+#define STM32MP1_DESC_IRQ_SIZE (ARRAY_SIZE(stm32mp1_exti_banks) * IRQS_PER_BANK)
+
+static const u8 stm32mp1_desc_irq[] = {
+ /* default value */
+ [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] = EXTI_INVALID_IRQ,
+
+ [0] = 6,
+ [1] = 7,
+ [2] = 8,
+ [3] = 9,
+ [4] = 10,
+ [5] = 23,
+ [6] = 64,
+ [7] = 65,
+ [8] = 66,
+ [9] = 67,
+ [10] = 40,
+ [11] = 42,
+ [12] = 76,
+ [13] = 77,
+ [14] = 121,
+ [15] = 127,
+ [16] = 1,
+ [19] = 3,
+ [21] = 31,
+ [22] = 33,
+ [23] = 72,
+ [24] = 95,
+ [25] = 107,
+ [26] = 37,
+ [27] = 38,
+ [28] = 39,
+ [29] = 71,
+ [30] = 52,
+ [31] = 53,
+ [32] = 82,
+ [33] = 83,
+ [47] = 93,
+ [48] = 138,
+ [50] = 139,
+ [52] = 140,
+ [53] = 141,
+ [54] = 135,
+ [61] = 100,
+ [65] = 144,
+ [68] = 143,
+ [70] = 62,
+ [73] = 129,
};

-static const struct stm32_desc_irq stm32mp13_desc_irq[] = {
- { .exti = 0, .irq_parent = 6 },
- { .exti = 1, .irq_parent = 7 },
- { .exti = 2, .irq_parent = 8 },
- { .exti = 3, .irq_parent = 9 },
- { .exti = 4, .irq_parent = 10 },
- { .exti = 5, .irq_parent = 24 },
- { .exti = 6, .irq_parent = 65 },
- { .exti = 7, .irq_parent = 66 },
- { .exti = 8, .irq_parent = 67 },
- { .exti = 9, .irq_parent = 68 },
- { .exti = 10, .irq_parent = 41 },
- { .exti = 11, .irq_parent = 43 },
- { .exti = 12, .irq_parent = 77 },
- { .exti = 13, .irq_parent = 78 },
- { .exti = 14, .irq_parent = 106 },
- { .exti = 15, .irq_parent = 109 },
- { .exti = 16, .irq_parent = 1 },
- { .exti = 19, .irq_parent = 3 },
- { .exti = 21, .irq_parent = 32 },
- { .exti = 22, .irq_parent = 34 },
- { .exti = 23, .irq_parent = 73 },
- { .exti = 24, .irq_parent = 93 },
- { .exti = 25, .irq_parent = 114 },
- { .exti = 26, .irq_parent = 38 },
- { .exti = 27, .irq_parent = 39 },
- { .exti = 28, .irq_parent = 40 },
- { .exti = 29, .irq_parent = 72 },
- { .exti = 30, .irq_parent = 53 },
- { .exti = 31, .irq_parent = 54 },
- { .exti = 32, .irq_parent = 83 },
- { .exti = 33, .irq_parent = 84 },
- { .exti = 44, .irq_parent = 96 },
- { .exti = 47, .irq_parent = 92 },
- { .exti = 48, .irq_parent = 116 },
- { .exti = 50, .irq_parent = 117 },
- { .exti = 52, .irq_parent = 118 },
- { .exti = 53, .irq_parent = 119 },
- { .exti = 68, .irq_parent = 63 },
- { .exti = 70, .irq_parent = 98 },
+static const u8 stm32mp13_desc_irq[] = {
+ /* default value */
+ [0 ... (STM32MP1_DESC_IRQ_SIZE - 1)] = EXTI_INVALID_IRQ,
+
+ [0] = 6,
+ [1] = 7,
+ [2] = 8,
+ [3] = 9,
+ [4] = 10,
+ [5] = 24,
+ [6] = 65,
+ [7] = 66,
+ [8] = 67,
+ [9] = 68,
+ [10] = 41,
+ [11] = 43,
+ [12] = 77,
+ [13] = 78,
+ [14] = 106,
+ [15] = 109,
+ [16] = 1,
+ [19] = 3,
+ [21] = 32,
+ [22] = 34,
+ [23] = 73,
+ [24] = 93,
+ [25] = 114,
+ [26] = 38,
+ [27] = 39,
+ [28] = 40,
+ [29] = 72,
+ [30] = 53,
+ [31] = 54,
+ [32] = 83,
+ [33] = 84,
+ [44] = 96,
+ [47] = 92,
+ [48] = 116,
+ [50] = 117,
+ [52] = 118,
+ [53] = 119,
+ [68] = 63,
+ [70] = 98,
};

static const struct stm32_exti_drv_data stm32mp1_drv_data = {
.exti_banks = stm32mp1_exti_banks,
.bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
.desc_irqs = stm32mp1_desc_irq,
- .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq),
};

static const struct stm32_exti_drv_data stm32mp13_drv_data = {
.exti_banks = stm32mp1_exti_banks,
.bank_nr = ARRAY_SIZE(stm32mp1_exti_banks),
.desc_irqs = stm32mp13_desc_irq,
- .irq_nr = ARRAY_SIZE(stm32mp13_desc_irq),
};

-static const struct
-stm32_desc_irq *stm32_exti_get_desc(const struct stm32_exti_drv_data *drv_data,
- irq_hw_number_t hwirq)
-{
- const struct stm32_desc_irq *desc = NULL;
- int i;
-
- if (!drv_data->desc_irqs)
- return NULL;
-
- for (i = 0; i < drv_data->irq_nr; i++) {
- desc = &drv_data->desc_irqs[i];
- if (desc->exti == hwirq)
- break;
- }
-
- return desc;
-}
-
static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
{
struct stm32_exti_chip_data *chip_data = gc->private;
@@ -713,7 +695,7 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
{
struct stm32_exti_host_data *host_data = dm->host_data;
struct stm32_exti_chip_data *chip_data;
- const struct stm32_desc_irq *desc;
+ u8 desc_irq;
struct irq_fwspec *fwspec = data;
struct irq_fwspec p_fwspec;
irq_hw_number_t hwirq;
@@ -728,21 +710,21 @@ static int stm32_exti_h_domain_alloc(struct irq_domain *dm,
bank = hwirq / IRQS_PER_BANK;
chip_data = &host_data->chips_data[bank];

-
- desc = stm32_exti_get_desc(host_data->drv_data, hwirq);
- if (!desc)
- return -EINVAL;
-
event_trg = readl_relaxed(host_data->base + chip_data->reg_bank->trg_ofst);
chip = (event_trg & BIT(hwirq % IRQS_PER_BANK)) ?
&stm32_exti_h_chip : &stm32_exti_h_chip_direct;

irq_domain_set_hwirq_and_chip(dm, virq, hwirq, chip, chip_data);
- if (desc->irq_parent) {
+
+ if (!host_data->drv_data || !host_data->drv_data->desc_irqs)
+ return -EINVAL;
+
+ desc_irq = host_data->drv_data->desc_irqs[hwirq];
+ if (desc_irq != EXTI_INVALID_IRQ) {
p_fwspec.fwnode = dm->parent->fwnode;
p_fwspec.param_count = 3;
p_fwspec.param[0] = GIC_SPI;
- p_fwspec.param[1] = desc->irq_parent;
+ p_fwspec.param[1] = desc_irq;
p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH;

return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec);