fa84f89395e0 ("irqchip/loongson-liointc: Fix build error for
LoongArch") replaced get_ebase_cpunum with physical processor
id from SMP facilities. However that breaks MIPS non-SMP build
and makes booting from other cores inpossible on non-SMP kernel.
Thus we revert get_ebase_cpunum back and use get_csr_cpuid for
LoongArch.
Fixes: fa84f89395e0 ("irqchip/loongson-liointc: Fix build error for LoongArch")
Signed-off-by: Jiaxun Yang <[email protected]>
---
drivers/irqchip/irq-loongson-liointc.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
index aed88857d90f..8d05d8bcf56f 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -39,6 +39,12 @@
#define LIOINTC_ERRATA_IRQ 10
+#if defined(CONFIG_MIPS)
+#define liointc_core_id get_ebase_cpunum()
+#else
+#define liointc_core_id get_csr_cpuid()
+#endif
+
struct liointc_handler_data {
struct liointc_priv *priv;
u32 parent_int_map;
@@ -57,7 +63,7 @@ static void liointc_chained_handle_irq(struct irq_desc *desc)
struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
struct irq_chip_generic *gc = handler->priv->gc;
- int core = cpu_logical_map(smp_processor_id()) % LIOINTC_NUM_CORES;
+ int core = liointc_core_id % LIOINTC_NUM_CORES;
u32 pending;
chained_irq_enter(chip, desc);
--
2.25.1
Only low 9 bits of CPUID CSR represents coreid, higher bits
are marked as reserved. In case Loongson may define higher
bits in future, just mask them out for get_csr_cpuid.
Also, as we already have read_csr_cpuid, rename get_csr_cpuid
to get_csr_coreid to reflect the actual bit domain name.
Signed-off-by: Jiaxun Yang <[email protected]>
---
arch/loongarch/include/asm/loongarch.h | 4 ++--
drivers/irqchip/irq-loongson-liointc.c | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
index 3ba4f7e87cd2..fe2408144fa3 100644
--- a/arch/loongarch/include/asm/loongarch.h
+++ b/arch/loongarch/include/asm/loongarch.h
@@ -1198,9 +1198,9 @@ static inline u64 drdtime(void)
return val;
}
-static inline unsigned int get_csr_cpuid(void)
+static inline unsigned int get_csr_coreid(void)
{
- return csr_read32(LOONGARCH_CSR_CPUID);
+ return csr_read32(LOONGARCH_CSR_CPUID) & CSR_CPUID_COREID;
}
static inline void csr_any_send(unsigned int addr, unsigned int data,
diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
index 8d05d8bcf56f..2ee636b2d827 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -42,7 +42,7 @@
#if defined(CONFIG_MIPS)
#define liointc_core_id get_ebase_cpunum()
#else
-#define liointc_core_id get_csr_cpuid()
+#define liointc_core_id read_csr_cpuid()
#endif
struct liointc_handler_data {
--
2.25.1
The following commit has been merged into the irq/irqchip-fixes branch of irqchip:
Commit-ID: 6fac824f40987a54a08dfbcc36145869d02e45b1
Gitweb: https://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms/6fac824f40987a54a08dfbcc36145869d02e45b1
Author: Jiaxun Yang <[email protected]>
AuthorDate: Thu, 09 Jun 2022 18:52:41 +01:00
Committer: Marc Zyngier <[email protected]>
CommitterDate: Fri, 10 Jun 2022 08:57:19 +01:00
irqchip/loongson-liointc: Use architecture register to get coreid
fa84f89395e0 ("irqchip/loongson-liointc: Fix build error for
LoongArch") replaced get_ebase_cpunum with physical processor
id from SMP facilities. However that breaks MIPS non-SMP build
and makes booting from other cores inpossible on non-SMP kernel.
Thus we revert get_ebase_cpunum back and use get_csr_cpuid for
LoongArch.
Fixes: fa84f89395e0 ("irqchip/loongson-liointc: Fix build error for LoongArch")
Signed-off-by: Jiaxun Yang <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
---
drivers/irqchip/irq-loongson-liointc.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
index aed8885..8d05d8b 100644
--- a/drivers/irqchip/irq-loongson-liointc.c
+++ b/drivers/irqchip/irq-loongson-liointc.c
@@ -39,6 +39,12 @@
#define LIOINTC_ERRATA_IRQ 10
+#if defined(CONFIG_MIPS)
+#define liointc_core_id get_ebase_cpunum()
+#else
+#define liointc_core_id get_csr_cpuid()
+#endif
+
struct liointc_handler_data {
struct liointc_priv *priv;
u32 parent_int_map;
@@ -57,7 +63,7 @@ static void liointc_chained_handle_irq(struct irq_desc *desc)
struct liointc_handler_data *handler = irq_desc_get_handler_data(desc);
struct irq_chip *chip = irq_desc_get_chip(desc);
struct irq_chip_generic *gc = handler->priv->gc;
- int core = cpu_logical_map(smp_processor_id()) % LIOINTC_NUM_CORES;
+ int core = liointc_core_id % LIOINTC_NUM_CORES;
u32 pending;
chained_irq_enter(chip, desc);
On Thu, 09 Jun 2022 18:52:42 +0100,
Jiaxun Yang <[email protected]> wrote:
>
> Only low 9 bits of CPUID CSR represents coreid, higher bits
> are marked as reserved. In case Loongson may define higher
> bits in future, just mask them out for get_csr_cpuid.
>
> Also, as we already have read_csr_cpuid, rename get_csr_cpuid
> to get_csr_coreid to reflect the actual bit domain name.
I assume you meant read_csr_cpuid here?
>
> Signed-off-by: Jiaxun Yang <[email protected]>
> ---
> arch/loongarch/include/asm/loongarch.h | 4 ++--
> drivers/irqchip/irq-loongson-liointc.c | 2 +-
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/arch/loongarch/include/asm/loongarch.h b/arch/loongarch/include/asm/loongarch.h
> index 3ba4f7e87cd2..fe2408144fa3 100644
> --- a/arch/loongarch/include/asm/loongarch.h
> +++ b/arch/loongarch/include/asm/loongarch.h
> @@ -1198,9 +1198,9 @@ static inline u64 drdtime(void)
> return val;
> }
>
> -static inline unsigned int get_csr_cpuid(void)
> +static inline unsigned int get_csr_coreid(void)
> {
> - return csr_read32(LOONGARCH_CSR_CPUID);
> + return csr_read32(LOONGARCH_CSR_CPUID) & CSR_CPUID_COREID;
> }
>
> static inline void csr_any_send(unsigned int addr, unsigned int data,
> diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/irq-loongson-liointc.c
> index 8d05d8bcf56f..2ee636b2d827 100644
> --- a/drivers/irqchip/irq-loongson-liointc.c
> +++ b/drivers/irqchip/irq-loongson-liointc.c
> @@ -42,7 +42,7 @@
> #if defined(CONFIG_MIPS)
> #define liointc_core_id get_ebase_cpunum()
> #else
> -#define liointc_core_id get_csr_cpuid()
> +#define liointc_core_id read_csr_cpuid()
> #endif
>
> struct liointc_handler_data {
I'm not going to take this patch as part of 5.19, as loongarch doesn't
have any irqchip support yet, and this can be made part of the IRQ
enabling series if really necessary.
M.
--
Without deviation from the norm, progress is not possible.