Setting these individually gives a better picture of supported
functions at a glance. Plus if the list changes an unwanted
one will not accidentally get set with GENMASK.
Signed-off-by: Andrew Davis <[email protected]>
---
drivers/crypto/sa2ul.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/sa2ul.c b/drivers/crypto/sa2ul.c
index 6957a125b4470..1d732113b81ec 100644
--- a/drivers/crypto/sa2ul.c
+++ b/drivers/crypto/sa2ul.c
@@ -2361,7 +2361,15 @@ static int sa_link_child(struct device *dev, void *data)
static struct sa_match_data am654_match_data = {
.priv = 1,
.priv_id = 1,
- .supported_algos = GENMASK(SA_ALG_AUTHENC_SHA256_AES, 0),
+ .supported_algos = BIT(SA_ALG_CBC_AES) |
+ BIT(SA_ALG_EBC_AES) |
+ BIT(SA_ALG_CBC_DES3) |
+ BIT(SA_ALG_ECB_DES3) |
+ BIT(SA_ALG_SHA1) |
+ BIT(SA_ALG_SHA256) |
+ BIT(SA_ALG_SHA512) |
+ BIT(SA_ALG_AUTHENC_SHA1_AES) |
+ BIT(SA_ALG_AUTHENC_SHA256_AES),
};
static struct sa_match_data am64_match_data = {
--
2.36.1
J7200 has an instance of SA2UL in the MCU domain.
Add DT node for the same.
Signed-off-by: Andrew Davis <[email protected]>
---
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index 1044ec6c4b0d4..ebad3642c8e30 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -375,4 +375,24 @@ mcu_r5fss0_core1: r5f@41400000 {
ti,loczrama = <1>;
};
};
+
+ mcu_crypto: crypto@40900000 {
+ compatible = "ti,j721e-sa2ul";
+ reg = <0x00 0x40900000 0x00 0x1200>;
+ power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
+ dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>,
+ <&mcu_udmap 0x7503>;
+ dma-names = "tx", "rx1", "rx2";
+ dma-coherent;
+
+ rng: rng@40910000 {
+ compatible = "inside-secure,safexcel-eip76";
+ reg = <0x00 0x40910000 0x00 0x7d>;
+ interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
+ };
+ };
};
--
2.36.1
The first TX and first two RX PSI-L threads for SA2UL are used
by SYSFW on High Security(HS) devices. Use the next available
threads to prevent resource allocation conflicts.
Signed-off-by: Andrew Davis <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 113e959ba06d0..2b0bac89b23f2 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -117,8 +117,8 @@ crypto: crypto@4e00000 {
#size-cells = <2>;
ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
- dmas = <&main_udmap 0xc000>, <&main_udmap 0x4000>,
- <&main_udmap 0x4001>;
+ dmas = <&main_udmap 0xc001>, <&main_udmap 0x4002>,
+ <&main_udmap 0x4003>;
dma-names = "tx", "rx1", "rx2";
dma-coherent;
--
2.36.1
The SA2UL hardware is also used by SYSFW and OP-TEE. It should be
requested using the shared TI-SCI flags instead of the exclusive
flags or the request will fail.
Signed-off-by: Andrew Davis <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index 2b0bac89b23f2..8f9c6282e8925 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -112,7 +112,7 @@ main_uart2: serial@2820000 {
crypto: crypto@4e00000 {
compatible = "ti,am654-sa2ul";
reg = <0x0 0x4e00000 0x0 0x1200>;
- power-domains = <&k3_pds 136 TI_SCI_PD_EXCLUSIVE>;
+ power-domains = <&k3_pds 136 TI_SCI_PD_SHARED>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x04e00000 0x00 0x04e00000 0x0 0x30000>;
--
2.36.1
On 12:03-20220705, Andrew Davis wrote:
> J7200 has an instance of SA2UL in the MCU domain.
> Add DT node for the same.
>
> Signed-off-by: Andrew Davis <[email protected]>
> ---
> .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 20 +++++++++++++++++++
> 1 file changed, 20 insertions(+)
Please split this series into what crypto maintainers need to pick up vs
what I need to pick up for dts. patches for my tree need to have lakml
in cc as a rule (see MAINTAINERS file).
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> index 1044ec6c4b0d4..ebad3642c8e30 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
> @@ -375,4 +375,24 @@ mcu_r5fss0_core1: r5f@41400000 {
> ti,loczrama = <1>;
> };
> };
> +
> + mcu_crypto: crypto@40900000 {
> + compatible = "ti,j721e-sa2ul";
> + reg = <0x00 0x40900000 0x00 0x1200>;
> + power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
> + dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>,
> + <&mcu_udmap 0x7503>;
> + dma-names = "tx", "rx1", "rx2";
> + dma-coherent;
> +
> + rng: rng@40910000 {
> + compatible = "inside-secure,safexcel-eip76";
> + reg = <0x00 0x40910000 0x00 0x7d>;
> + interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>;
Please document why disabled.
> + status = "disabled";
> + };
> + };
> };
> --
> 2.36.1
>
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
On 7/6/22 1:04 PM, Nishanth Menon wrote:
> On 12:03-20220705, Andrew Davis wrote:
>> J7200 has an instance of SA2UL in the MCU domain.
>> Add DT node for the same.
>>
>> Signed-off-by: Andrew Davis <[email protected]>
>> ---
>> .../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 20 +++++++++++++++++++
>> 1 file changed, 20 insertions(+)
>
> Please split this series into what crypto maintainers need to pick up vs
> what I need to pick up for dts. patches for my tree need to have lakml
> in cc as a rule (see MAINTAINERS file).
>
Okay, I'll break the first two into their own series. Adding LAKML folks
for v2.
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
>> index 1044ec6c4b0d4..ebad3642c8e30 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
>> +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
>> @@ -375,4 +375,24 @@ mcu_r5fss0_core1: r5f@41400000 {
>> ti,loczrama = <1>;
>> };
>> };
>> +
>> + mcu_crypto: crypto@40900000 {
>> + compatible = "ti,j721e-sa2ul";
>> + reg = <0x00 0x40900000 0x00 0x1200>;
>> + power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
>> + dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>,
>> + <&mcu_udmap 0x7503>;
>> + dma-names = "tx", "rx1", "rx2";
>> + dma-coherent;
>> +
>> + rng: rng@40910000 {
>> + compatible = "inside-secure,safexcel-eip76";
>> + reg = <0x00 0x40910000 0x00 0x7d>;
>> + interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>;
>
> Please document why disabled.
>
Sure thing, will add background info to the commit message.
Thanks,
Andrew
>> + status = "disabled";
>> + };
>> + };
>> };
>> --
>> 2.36.1
>>
>
On 13:10-20220706, Andrew Davis wrote:
> > > + mcu_crypto: crypto@40900000 {
> > > + compatible = "ti,j721e-sa2ul";
> > > + reg = <0x00 0x40900000 0x00 0x1200>;
> > > + power-domains = <&k3_pds 265 TI_SCI_PD_SHARED>;
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> > > + ranges = <0x00 0x40900000 0x00 0x40900000 0x00 0x30000>;
> > > + dmas = <&mcu_udmap 0xf501>, <&mcu_udmap 0x7502>,
> > > + <&mcu_udmap 0x7503>;
> > > + dma-names = "tx", "rx1", "rx2";
> > > + dma-coherent;
> > > +
> > > + rng: rng@40910000 {
> > > + compatible = "inside-secure,safexcel-eip76";
> > > + reg = <0x00 0x40910000 0x00 0x7d>;
> > > + interrupts = <GIC_SPI 945 IRQ_TYPE_LEVEL_HIGH>;
> >
> > Please document why disabled.
> >
>
> Sure thing, will add background info to the commit message.
I'd suggest to document in dts as well. See thread [1]
[1] https://lore.kernel.org/linux-arm-kernel/[email protected]/
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D