Now that the basic SysMMU v7 support is ready [1,2], all SysMMU nodes
can be added to Exynos850 SoC device tree. This series includes next
changes:
1. Add all missing clock domains needed for SysMMU clocks
2. Add corresponding CMU nodes in device tree
3. Add all SysMMU nodes in device tree
All SysMMU instances were tested with "emulated translation" driver [3]
on E850-96 board: both the emulated translation and fault handling were
verified.
[1] https://lkml.org/lkml/2022/7/14/1215
[2] https://lkml.org/lkml/2022/7/26/950
[3] https://github.com/joe-skb7/linux/tree/e850-96-mainline-iommu
Changes in v2:
- Joined CMU and DTS patch series patches into one
- Sorted sysmmu nodes by unit address
Sam Protsenko (9):
dt-bindings: clock: Add bindings for Exynos850 CMU_AUD
dt-bindings: clock: Add bindings for Exynos850 CMU_IS
dt-bindings: clock: Add bindings for Exynos850 CMU_MFCMSCL
clk: samsung: exynos850: Style fixes
clk: samsung: exynos850: Implement CMU_AUD domain
clk: samsung: exynos850: Implement CMU_IS domain
clk: samsung: exynos850: Implement CMU_MFCMSCL domain
arm64: dts: exynos: Add CMU_AUD, CMU_IS and CMU_MFCMSCL for Exynos850
arm64: dts: exynos: Add SysMMU nodes for Exynos850
.../clock/samsung,exynos850-clock.yaml | 69 ++
arch/arm64/boot/dts/exynos/exynos850.dtsi | 83 +++
drivers/clk/samsung/clk-exynos850.c | 682 +++++++++++++++++-
include/dt-bindings/clock/exynos850.h | 136 +++-
4 files changed, 966 insertions(+), 4 deletions(-)
--
2.30.2
CMU_IS generates CSIS, IPP, ITP, VRA and GDC clocks for BLK_IS. Add
clock indices and bindings documentation for CMU_IS domain.
Signed-off-by: Sam Protsenko <[email protected]>
---
Changes in v2:
- (none)
.../clock/samsung,exynos850-clock.yaml | 25 ++++++++++++
include/dt-bindings/clock/exynos850.h | 40 ++++++++++++++++++-
2 files changed, 64 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
index 53511f056251..7f2e0b1c764c 100644
--- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
@@ -38,6 +38,7 @@ properties:
- samsung,exynos850-cmu-core
- samsung,exynos850-cmu-dpu
- samsung,exynos850-cmu-hsi
+ - samsung,exynos850-cmu-is
- samsung,exynos850-cmu-peri
clocks:
@@ -191,6 +192,30 @@ allOf:
- const: dout_hsi_mmc_card
- const: dout_hsi_usb20drd
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos850-cmu-is
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: CMU_IS bus clock (from CMU_TOP)
+ - description: Image Texture Processing core clock (from CMU_TOP)
+ - description: Visual Recognition Accelerator clock (from CMU_TOP)
+ - description: Geometric Distortion Correction clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_is_bus
+ - const: dout_is_itp
+ - const: dout_is_vra
+ - const: dout_is_gdc
+
- if:
properties:
compatible:
diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
index 3dc55d4e5b9e..f8bf26f118c1 100644
--- a/include/dt-bindings/clock/exynos850.h
+++ b/include/dt-bindings/clock/exynos850.h
@@ -61,7 +61,19 @@
#define CLK_MOUT_AUD 49
#define CLK_GOUT_AUD 50
#define CLK_DOUT_AUD 51
-#define TOP_NR_CLK 52
+#define CLK_MOUT_IS_BUS 52
+#define CLK_MOUT_IS_ITP 53
+#define CLK_MOUT_IS_VRA 54
+#define CLK_MOUT_IS_GDC 55
+#define CLK_GOUT_IS_BUS 56
+#define CLK_GOUT_IS_ITP 57
+#define CLK_GOUT_IS_VRA 58
+#define CLK_GOUT_IS_GDC 59
+#define CLK_DOUT_IS_BUS 60
+#define CLK_DOUT_IS_ITP 61
+#define CLK_DOUT_IS_VRA 62
+#define CLK_DOUT_IS_GDC 63
+#define TOP_NR_CLK 64
/* CMU_APM */
#define CLK_RCO_I3C_PMIC 1
@@ -187,6 +199,32 @@
#define CLK_GOUT_SYSREG_HSI_PCLK 13
#define HSI_NR_CLK 14
+/* CMU_IS */
+#define CLK_MOUT_IS_BUS_USER 1
+#define CLK_MOUT_IS_ITP_USER 2
+#define CLK_MOUT_IS_VRA_USER 3
+#define CLK_MOUT_IS_GDC_USER 4
+#define CLK_DOUT_IS_BUSP 5
+#define CLK_GOUT_IS_CMU_IS_PCLK 6
+#define CLK_GOUT_IS_CSIS0_ACLK 7
+#define CLK_GOUT_IS_CSIS1_ACLK 8
+#define CLK_GOUT_IS_CSIS2_ACLK 9
+#define CLK_GOUT_IS_TZPC_PCLK 10
+#define CLK_GOUT_IS_CSIS_DMA_CLK 11
+#define CLK_GOUT_IS_GDC_CLK 12
+#define CLK_GOUT_IS_IPP_CLK 13
+#define CLK_GOUT_IS_ITP_CLK 14
+#define CLK_GOUT_IS_MCSC_CLK 15
+#define CLK_GOUT_IS_VRA_CLK 16
+#define CLK_GOUT_IS_PPMU_IS0_ACLK 17
+#define CLK_GOUT_IS_PPMU_IS0_PCLK 18
+#define CLK_GOUT_IS_PPMU_IS1_ACLK 19
+#define CLK_GOUT_IS_PPMU_IS1_PCLK 20
+#define CLK_GOUT_IS_SYSMMU_IS0_CLK 21
+#define CLK_GOUT_IS_SYSMMU_IS1_CLK 22
+#define CLK_GOUT_IS_SYSREG_PCLK 23
+#define IS_NR_CLK 24
+
/* CMU_PERI */
#define CLK_MOUT_PERI_BUS_USER 1
#define CLK_MOUT_PERI_UART_USER 2
--
2.30.2
CMU_AUD generates Cortex-A32 clock, bus clock and audio clocks for
BLK_AUD. Add clock indices and binding documentation for CMU_AUD.
Signed-off-by: Sam Protsenko <[email protected]>
---
Changes in v2:
- (none)
.../clock/samsung,exynos850-clock.yaml | 19 ++++++
include/dt-bindings/clock/exynos850.h | 68 ++++++++++++++++++-
2 files changed, 86 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
index aa11815ad3a3..53511f056251 100644
--- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
@@ -33,6 +33,7 @@ properties:
enum:
- samsung,exynos850-cmu-top
- samsung,exynos850-cmu-apm
+ - samsung,exynos850-cmu-aud
- samsung,exynos850-cmu-cmgp
- samsung,exynos850-cmu-core
- samsung,exynos850-cmu-dpu
@@ -88,6 +89,24 @@ allOf:
- const: oscclk
- const: dout_clkcmu_apm_bus
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos850-cmu-aud
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: AUD clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_aud
+
- if:
properties:
compatible:
diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
index 0b6a3c6a7c90..3dc55d4e5b9e 100644
--- a/include/dt-bindings/clock/exynos850.h
+++ b/include/dt-bindings/clock/exynos850.h
@@ -58,7 +58,10 @@
#define CLK_MOUT_CLKCMU_APM_BUS 46
#define CLK_DOUT_CLKCMU_APM_BUS 47
#define CLK_GOUT_CLKCMU_APM_BUS 48
-#define TOP_NR_CLK 49
+#define CLK_MOUT_AUD 49
+#define CLK_GOUT_AUD 50
+#define CLK_DOUT_AUD 51
+#define TOP_NR_CLK 52
/* CMU_APM */
#define CLK_RCO_I3C_PMIC 1
@@ -87,6 +90,69 @@
#define CLK_GOUT_SYSREG_APM_PCLK 24
#define APM_NR_CLK 25
+/* CMU_AUD */
+#define CLK_DOUT_AUD_AUDIF 1
+#define CLK_DOUT_AUD_BUSD 2
+#define CLK_DOUT_AUD_BUSP 3
+#define CLK_DOUT_AUD_CNT 4
+#define CLK_DOUT_AUD_CPU 5
+#define CLK_DOUT_AUD_CPU_ACLK 6
+#define CLK_DOUT_AUD_CPU_PCLKDBG 7
+#define CLK_DOUT_AUD_FM 8
+#define CLK_DOUT_AUD_FM_SPDY 9
+#define CLK_DOUT_AUD_MCLK 10
+#define CLK_DOUT_AUD_UAIF0 11
+#define CLK_DOUT_AUD_UAIF1 12
+#define CLK_DOUT_AUD_UAIF2 13
+#define CLK_DOUT_AUD_UAIF3 14
+#define CLK_DOUT_AUD_UAIF4 15
+#define CLK_DOUT_AUD_UAIF5 16
+#define CLK_DOUT_AUD_UAIF6 17
+#define CLK_FOUT_AUD_PLL 18
+#define CLK_GOUT_AUD_ABOX_ACLK 19
+#define CLK_GOUT_AUD_ASB_CCLK 20
+#define CLK_GOUT_AUD_CA32_CCLK 21
+#define CLK_GOUT_AUD_CNT_BCLK 22
+#define CLK_GOUT_AUD_CODEC_MCLK 23
+#define CLK_GOUT_AUD_DAP_CCLK 24
+#define CLK_GOUT_AUD_GPIO_PCLK 25
+#define CLK_GOUT_AUD_PPMU_ACLK 26
+#define CLK_GOUT_AUD_PPMU_PCLK 27
+#define CLK_GOUT_AUD_SPDY_BCLK 28
+#define CLK_GOUT_AUD_SYSMMU_CLK 29
+#define CLK_GOUT_AUD_SYSREG_PCLK 30
+#define CLK_GOUT_AUD_TZPC_PCLK 31
+#define CLK_GOUT_AUD_UAIF0_BCLK 32
+#define CLK_GOUT_AUD_UAIF1_BCLK 33
+#define CLK_GOUT_AUD_UAIF2_BCLK 34
+#define CLK_GOUT_AUD_UAIF3_BCLK 35
+#define CLK_GOUT_AUD_UAIF4_BCLK 36
+#define CLK_GOUT_AUD_UAIF5_BCLK 37
+#define CLK_GOUT_AUD_UAIF6_BCLK 38
+#define CLK_GOUT_AUD_WDT_PCLK 39
+#define CLK_MOUT_AUD_CPU 40
+#define CLK_MOUT_AUD_CPU_HCH 41
+#define CLK_MOUT_AUD_CPU_USER 42
+#define CLK_MOUT_AUD_FM 43
+#define CLK_MOUT_AUD_PLL 44
+#define CLK_MOUT_AUD_TICK_USB_USER 45
+#define CLK_MOUT_AUD_UAIF0 46
+#define CLK_MOUT_AUD_UAIF1 47
+#define CLK_MOUT_AUD_UAIF2 48
+#define CLK_MOUT_AUD_UAIF3 49
+#define CLK_MOUT_AUD_UAIF4 50
+#define CLK_MOUT_AUD_UAIF5 51
+#define CLK_MOUT_AUD_UAIF6 52
+#define IOCLK_AUDIOCDCLK0 53
+#define IOCLK_AUDIOCDCLK1 54
+#define IOCLK_AUDIOCDCLK2 55
+#define IOCLK_AUDIOCDCLK3 56
+#define IOCLK_AUDIOCDCLK4 57
+#define IOCLK_AUDIOCDCLK5 58
+#define IOCLK_AUDIOCDCLK6 59
+#define TICK_USB 60
+#define AUD_NR_CLK 61
+
/* CMU_CMGP */
#define CLK_RCO_CMGP 1
#define CLK_MOUT_CMGP_ADC 2
--
2.30.2
CMU_IS clock domain provides clocks for IS IP-core (Image Signal
Processing Subsystem). According to Exynos850 TRM, CMU_IS generates
CSIS, IPP, ITP, VRA and GDC clocks for BLK_IS.
This patch adds next clocks:
- bus clocks in CMU_TOP needed for CMU_IS
- all internal CMU_IS clocks
- leaf clocks for IS IP-core, CSIS (Camera Serial Interface Slave),
D_TZPC (TrustZone Protection Controller), CSIS DMA, GDC (Geometric
Distortion Correction), IPP (Image Preprocessing Processing core),
ITP (Image Texture Processing core), MCSC (Multi-Channel Scaler),
VRA (Visual Recognition Accelerator), PPMU (Platform Performance
Monitoring Unit), SysMMU and SysReg
IS related gate clocks in CMU_TOP were marked as CLK_IS_CRITICAL,
because:
1. All of those have to be enabled in order to read
/sys/kernel/debug/clk/clk_summary file
2. When some user driver (e.g. exynos-sysmmu) disables some derived
leaf clock, it can lead to CMU_TOP clocks disable, which then makes
the system hang. To prevent that, the CLK_IS_CRITICAL flag is used,
as CLK_IGNORE_UNUSED is not enough.
Signed-off-by: Sam Protsenko <[email protected]>
---
Changes in v2:
- (none)
drivers/clk/samsung/clk-exynos850.c | 199 ++++++++++++++++++++++++++++
1 file changed, 199 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c
index c91984f3f14f..18a36d58101e 100644
--- a/drivers/clk/samsung/clk-exynos850.c
+++ b/drivers/clk/samsung/clk-exynos850.c
@@ -39,6 +39,10 @@
#define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c
#define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040
#define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044
+#define CLK_CON_MUX_MUX_CLKCMU_IS_BUS 0x1048
+#define CLK_CON_MUX_MUX_CLKCMU_IS_GDC 0x104c
+#define CLK_CON_MUX_MUX_CLKCMU_IS_ITP 0x1050
+#define CLK_CON_MUX_MUX_CLKCMU_IS_VRA 0x1054
#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070
#define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
@@ -52,6 +56,10 @@
#define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848
#define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c
#define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850
+#define CLK_CON_DIV_CLKCMU_IS_BUS 0x1854
+#define CLK_CON_DIV_CLKCMU_IS_GDC 0x1858
+#define CLK_CON_DIV_CLKCMU_IS_ITP 0x185c
+#define CLK_CON_DIV_CLKCMU_IS_VRA 0x1860
#define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c
#define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880
#define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884
@@ -71,6 +79,10 @@
#define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044
#define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048
#define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c
+#define CLK_CON_GAT_GATE_CLKCMU_IS_BUS 0x2050
+#define CLK_CON_GAT_GATE_CLKCMU_IS_GDC 0x2054
+#define CLK_CON_GAT_GATE_CLKCMU_IS_ITP 0x2058
+#define CLK_CON_GAT_GATE_CLKCMU_IS_VRA 0x205c
#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080
#define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084
#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088
@@ -95,6 +107,10 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_MUX_MUX_CLKCMU_HSI_BUS,
CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD,
CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD,
+ CLK_CON_MUX_MUX_CLKCMU_IS_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_IS_GDC,
+ CLK_CON_MUX_MUX_CLKCMU_IS_ITP,
+ CLK_CON_MUX_MUX_CLKCMU_IS_VRA,
CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
CLK_CON_MUX_MUX_CLKCMU_PERI_IP,
CLK_CON_MUX_MUX_CLKCMU_PERI_UART,
@@ -108,6 +124,10 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_DIV_CLKCMU_HSI_BUS,
CLK_CON_DIV_CLKCMU_HSI_MMC_CARD,
CLK_CON_DIV_CLKCMU_HSI_USB20DRD,
+ CLK_CON_DIV_CLKCMU_IS_BUS,
+ CLK_CON_DIV_CLKCMU_IS_GDC,
+ CLK_CON_DIV_CLKCMU_IS_ITP,
+ CLK_CON_DIV_CLKCMU_IS_VRA,
CLK_CON_DIV_CLKCMU_PERI_BUS,
CLK_CON_DIV_CLKCMU_PERI_IP,
CLK_CON_DIV_CLKCMU_PERI_UART,
@@ -127,6 +147,10 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_GAT_GATE_CLKCMU_HSI_BUS,
CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD,
CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD,
+ CLK_CON_GAT_GATE_CLKCMU_IS_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_IS_GDC,
+ CLK_CON_GAT_GATE_CLKCMU_IS_ITP,
+ CLK_CON_GAT_GATE_CLKCMU_IS_VRA,
CLK_CON_GAT_GATE_CLKCMU_PERI_BUS,
CLK_CON_GAT_GATE_CLKCMU_PERI_IP,
CLK_CON_GAT_GATE_CLKCMU_PERI_UART,
@@ -176,6 +200,15 @@ PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2",
"oscclk", "oscclk" };
PNAME(mout_hsi_usb20drd_p) = { "oscclk", "dout_shared0_div4",
"dout_shared1_div4", "oscclk" };
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_IS */
+PNAME(mout_is_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
+ "dout_shared0_div3", "dout_shared1_div3" };
+PNAME(mout_is_itp_p) = { "dout_shared0_div2", "dout_shared1_div2",
+ "dout_shared0_div3", "dout_shared1_div3" };
+PNAME(mout_is_vra_p) = { "dout_shared0_div2", "dout_shared1_div2",
+ "dout_shared0_div3", "dout_shared1_div3" };
+PNAME(mout_is_gdc_p) = { "dout_shared0_div2", "dout_shared1_div2",
+ "dout_shared0_div3", "dout_shared1_div3" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" };
PNAME(mout_peri_uart_p) = { "oscclk", "dout_shared0_div4",
@@ -225,6 +258,16 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p,
CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2),
+ /* IS */
+ MUX(CLK_MOUT_IS_BUS, "mout_is_bus", mout_is_bus_p,
+ CLK_CON_MUX_MUX_CLKCMU_IS_BUS, 0, 2),
+ MUX(CLK_MOUT_IS_ITP, "mout_is_itp", mout_is_itp_p,
+ CLK_CON_MUX_MUX_CLKCMU_IS_ITP, 0, 2),
+ MUX(CLK_MOUT_IS_VRA, "mout_is_vra", mout_is_vra_p,
+ CLK_CON_MUX_MUX_CLKCMU_IS_VRA, 0, 2),
+ MUX(CLK_MOUT_IS_GDC, "mout_is_gdc", mout_is_gdc_p,
+ CLK_CON_MUX_MUX_CLKCMU_IS_GDC, 0, 2),
+
/* PERI */
MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
@@ -279,6 +322,16 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd",
CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4),
+ /* IS */
+ DIV(CLK_DOUT_IS_BUS, "dout_is_bus", "gout_is_bus",
+ CLK_CON_DIV_CLKCMU_IS_BUS, 0, 4),
+ DIV(CLK_DOUT_IS_ITP, "dout_is_itp", "gout_is_itp",
+ CLK_CON_DIV_CLKCMU_IS_ITP, 0, 4),
+ DIV(CLK_DOUT_IS_VRA, "dout_is_vra", "gout_is_vra",
+ CLK_CON_DIV_CLKCMU_IS_VRA, 0, 4),
+ DIV(CLK_DOUT_IS_GDC, "dout_is_gdc", "gout_is_gdc",
+ CLK_CON_DIV_CLKCMU_IS_GDC, 0, 4),
+
/* PERI */
DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
@@ -319,6 +372,17 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd",
CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0),
+ /* IS */
+ /* TODO: These clocks have to be always enabled to access CMU_IS regs */
+ GATE(CLK_GOUT_IS_BUS, "gout_is_bus", "mout_is_bus",
+ CLK_CON_GAT_GATE_CLKCMU_IS_BUS, 21, CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_IS_ITP, "gout_is_itp", "mout_is_itp",
+ CLK_CON_GAT_GATE_CLKCMU_IS_ITP, 21, CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_IS_VRA, "gout_is_vra", "mout_is_vra",
+ CLK_CON_GAT_GATE_CLKCMU_IS_VRA, 21, CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_IS_GDC, "gout_is_gdc", "mout_is_gdc",
+ CLK_CON_GAT_GATE_CLKCMU_IS_GDC, 21, CLK_IS_CRITICAL, 0),
+
/* PERI */
GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus",
CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
@@ -952,6 +1016,138 @@ static const struct samsung_cmu_info hsi_cmu_info __initconst = {
.clk_name = "dout_hsi_bus",
};
+/* ---- CMU_IS -------------------------------------------------------------- */
+
+#define PLL_CON0_MUX_CLKCMU_IS_BUS_USER 0x0600
+#define PLL_CON0_MUX_CLKCMU_IS_GDC_USER 0x0610
+#define PLL_CON0_MUX_CLKCMU_IS_ITP_USER 0x0620
+#define PLL_CON0_MUX_CLKCMU_IS_VRA_USER 0x0630
+#define CLK_CON_DIV_DIV_CLK_IS_BUSP 0x1800
+#define CLK_CON_GAT_CLK_IS_CMU_IS_PCLK 0x2000
+#define CLK_CON_GAT_GOUT_IS_CSIS0_ACLK 0x2040
+#define CLK_CON_GAT_GOUT_IS_CSIS1_ACLK 0x2044
+#define CLK_CON_GAT_GOUT_IS_CSIS2_ACLK 0x2048
+#define CLK_CON_GAT_GOUT_IS_TZPC_PCLK 0x204c
+#define CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA 0x2050
+#define CLK_CON_GAT_GOUT_IS_CLK_GDC 0x2054
+#define CLK_CON_GAT_GOUT_IS_CLK_IPP 0x2058
+#define CLK_CON_GAT_GOUT_IS_CLK_ITP 0x205c
+#define CLK_CON_GAT_GOUT_IS_CLK_MCSC 0x2060
+#define CLK_CON_GAT_GOUT_IS_CLK_VRA 0x2064
+#define CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK 0x2074
+#define CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK 0x2078
+#define CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK 0x207c
+#define CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK 0x2080
+#define CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1 0x2098
+#define CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1 0x209c
+#define CLK_CON_GAT_GOUT_IS_SYSREG_PCLK 0x20a0
+
+static const unsigned long is_clk_regs[] __initconst = {
+ PLL_CON0_MUX_CLKCMU_IS_BUS_USER,
+ PLL_CON0_MUX_CLKCMU_IS_GDC_USER,
+ PLL_CON0_MUX_CLKCMU_IS_ITP_USER,
+ PLL_CON0_MUX_CLKCMU_IS_VRA_USER,
+ CLK_CON_DIV_DIV_CLK_IS_BUSP,
+ CLK_CON_GAT_CLK_IS_CMU_IS_PCLK,
+ CLK_CON_GAT_GOUT_IS_CSIS0_ACLK,
+ CLK_CON_GAT_GOUT_IS_CSIS1_ACLK,
+ CLK_CON_GAT_GOUT_IS_CSIS2_ACLK,
+ CLK_CON_GAT_GOUT_IS_TZPC_PCLK,
+ CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA,
+ CLK_CON_GAT_GOUT_IS_CLK_GDC,
+ CLK_CON_GAT_GOUT_IS_CLK_IPP,
+ CLK_CON_GAT_GOUT_IS_CLK_ITP,
+ CLK_CON_GAT_GOUT_IS_CLK_MCSC,
+ CLK_CON_GAT_GOUT_IS_CLK_VRA,
+ CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK,
+ CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK,
+ CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK,
+ CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK,
+ CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1,
+ CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1,
+ CLK_CON_GAT_GOUT_IS_SYSREG_PCLK,
+};
+
+/* List of parent clocks for Muxes in CMU_IS */
+PNAME(mout_is_bus_user_p) = { "oscclk", "dout_is_bus" };
+PNAME(mout_is_itp_user_p) = { "oscclk", "dout_is_itp" };
+PNAME(mout_is_vra_user_p) = { "oscclk", "dout_is_vra" };
+PNAME(mout_is_gdc_user_p) = { "oscclk", "dout_is_gdc" };
+
+static const struct samsung_mux_clock is_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_IS_BUS_USER, "mout_is_bus_user", mout_is_bus_user_p,
+ PLL_CON0_MUX_CLKCMU_IS_BUS_USER, 4, 1),
+ MUX(CLK_MOUT_IS_ITP_USER, "mout_is_itp_user", mout_is_itp_user_p,
+ PLL_CON0_MUX_CLKCMU_IS_ITP_USER, 4, 1),
+ MUX(CLK_MOUT_IS_VRA_USER, "mout_is_vra_user", mout_is_vra_user_p,
+ PLL_CON0_MUX_CLKCMU_IS_VRA_USER, 4, 1),
+ MUX(CLK_MOUT_IS_GDC_USER, "mout_is_gdc_user", mout_is_gdc_user_p,
+ PLL_CON0_MUX_CLKCMU_IS_GDC_USER, 4, 1),
+};
+
+static const struct samsung_div_clock is_div_clks[] __initconst = {
+ DIV(CLK_DOUT_IS_BUSP, "dout_is_busp", "mout_is_bus_user",
+ CLK_CON_DIV_DIV_CLK_IS_BUSP, 0, 2),
+};
+
+static const struct samsung_gate_clock is_gate_clks[] __initconst = {
+ /* TODO: Should be enabled in IS driver */
+ GATE(CLK_GOUT_IS_CMU_IS_PCLK, "gout_is_cmu_is_pclk", "dout_is_busp",
+ CLK_CON_GAT_CLK_IS_CMU_IS_PCLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_GOUT_IS_CSIS0_ACLK, "gout_is_csis0_aclk", "mout_is_bus_user",
+ CLK_CON_GAT_GOUT_IS_CSIS0_ACLK, 21, 0, 0),
+ GATE(CLK_GOUT_IS_CSIS1_ACLK, "gout_is_csis1_aclk", "mout_is_bus_user",
+ CLK_CON_GAT_GOUT_IS_CSIS1_ACLK, 21, 0, 0),
+ GATE(CLK_GOUT_IS_CSIS2_ACLK, "gout_is_csis2_aclk", "mout_is_bus_user",
+ CLK_CON_GAT_GOUT_IS_CSIS2_ACLK, 21, 0, 0),
+ GATE(CLK_GOUT_IS_TZPC_PCLK, "gout_is_tzpc_pclk", "dout_is_busp",
+ CLK_CON_GAT_GOUT_IS_TZPC_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_IS_CSIS_DMA_CLK, "gout_is_csis_dma_clk",
+ "mout_is_bus_user",
+ CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA, 21, 0, 0),
+ GATE(CLK_GOUT_IS_GDC_CLK, "gout_is_gdc_clk", "mout_is_gdc_user",
+ CLK_CON_GAT_GOUT_IS_CLK_GDC, 21, 0, 0),
+ GATE(CLK_GOUT_IS_IPP_CLK, "gout_is_ipp_clk", "mout_is_bus_user",
+ CLK_CON_GAT_GOUT_IS_CLK_IPP, 21, 0, 0),
+ GATE(CLK_GOUT_IS_ITP_CLK, "gout_is_itp_clk", "mout_is_itp_user",
+ CLK_CON_GAT_GOUT_IS_CLK_ITP, 21, 0, 0),
+ GATE(CLK_GOUT_IS_MCSC_CLK, "gout_is_mcsc_clk", "mout_is_itp_user",
+ CLK_CON_GAT_GOUT_IS_CLK_MCSC, 21, 0, 0),
+ GATE(CLK_GOUT_IS_VRA_CLK, "gout_is_vra_clk", "mout_is_vra_user",
+ CLK_CON_GAT_GOUT_IS_CLK_VRA, 21, 0, 0),
+ GATE(CLK_GOUT_IS_PPMU_IS0_ACLK, "gout_is_ppmu_is0_aclk",
+ "mout_is_bus_user",
+ CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK, 21, 0, 0),
+ GATE(CLK_GOUT_IS_PPMU_IS0_PCLK, "gout_is_ppmu_is0_pclk", "dout_is_busp",
+ CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_IS_PPMU_IS1_ACLK, "gout_is_ppmu_is1_aclk",
+ "mout_is_itp_user",
+ CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK, 21, 0, 0),
+ GATE(CLK_GOUT_IS_PPMU_IS1_PCLK, "gout_is_ppmu_is1_pclk", "dout_is_busp",
+ CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_IS_SYSMMU_IS0_CLK, "gout_is_sysmmu_is0_clk",
+ "mout_is_bus_user",
+ CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1, 21, 0, 0),
+ GATE(CLK_GOUT_IS_SYSMMU_IS1_CLK, "gout_is_sysmmu_is1_clk",
+ "mout_is_itp_user",
+ CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1, 21, 0, 0),
+ GATE(CLK_GOUT_IS_SYSREG_PCLK, "gout_is_sysreg_pclk", "dout_is_busp",
+ CLK_CON_GAT_GOUT_IS_SYSREG_PCLK, 21, 0, 0),
+};
+
+static const struct samsung_cmu_info is_cmu_info __initconst = {
+ .mux_clks = is_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(is_mux_clks),
+ .div_clks = is_div_clks,
+ .nr_div_clks = ARRAY_SIZE(is_div_clks),
+ .gate_clks = is_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(is_gate_clks),
+ .nr_clk_ids = IS_NR_CLK,
+ .clk_regs = is_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(is_clk_regs),
+ .clk_name = "dout_is_bus",
+};
+
/* ---- CMU_PERI ------------------------------------------------------------ */
/* Register Offset definitions for CMU_PERI (0x10030000) */
@@ -1334,6 +1530,9 @@ static const struct of_device_id exynos850_cmu_of_match[] = {
}, {
.compatible = "samsung,exynos850-cmu-hsi",
.data = &hsi_cmu_info,
+ }, {
+ .compatible = "samsung,exynos850-cmu-is",
+ .data = &is_cmu_info,
}, {
.compatible = "samsung,exynos850-cmu-core",
.data = &core_cmu_info,
--
2.30.2
CMU_MFCMSCL clock domain provides clocks for MFC (Multi-Format Codec),
JPEG Codec and Scaler IP-cores. According to Exynos850 TRM, CMU_MFCMSCL
generates MFC, M2M, MCSC and JPEG clocks for BLK_MFCMSCL.
This patch adds next clocks:
- bus clocks in CMU_TOP for CMU_MFCMSCL
- all internal CMU_MFCMSCL clocks
- leaf clocks for MFCMSCL, TZPC (TrustZone Protection Controller),
JPEG codec, M2M (Memory-to-Memory), MCSC (Multi-Channel Scaler),
MFC (Multi-Format Codec), PPMU (Platform Performance Monitoring
Unit), SysMMU and SysReg
MFCMSCL related gate clocks in CMU_TOP were marked as CLK_IS_CRITICAL,
because:
1. All of those have to be enabled in order to read
/sys/kernel/debug/clk/clk_summary file
2. When some user driver (e.g. exynos-sysmmu) disables some derived
leaf clock, it can lead to CMU_TOP clocks disable, which then makes
the system hang. To prevent that, the CLK_IS_CRITICAL flag is used,
as CLK_IGNORE_UNUSED is not enough.
Signed-off-by: Sam Protsenko <[email protected]>
---
Changes in v2:
- (none)
drivers/clk/samsung/clk-exynos850.c | 176 ++++++++++++++++++++++++++++
1 file changed, 176 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c
index 18a36d58101e..541761e96aeb 100644
--- a/drivers/clk/samsung/clk-exynos850.c
+++ b/drivers/clk/samsung/clk-exynos850.c
@@ -43,6 +43,10 @@
#define CLK_CON_MUX_MUX_CLKCMU_IS_GDC 0x104c
#define CLK_CON_MUX_MUX_CLKCMU_IS_ITP 0x1050
#define CLK_CON_MUX_MUX_CLKCMU_IS_VRA 0x1054
+#define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG 0x1058
+#define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M 0x105c
+#define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC 0x1060
+#define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC 0x1064
#define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070
#define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
@@ -60,6 +64,10 @@
#define CLK_CON_DIV_CLKCMU_IS_GDC 0x1858
#define CLK_CON_DIV_CLKCMU_IS_ITP 0x185c
#define CLK_CON_DIV_CLKCMU_IS_VRA 0x1860
+#define CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG 0x1864
+#define CLK_CON_DIV_CLKCMU_MFCMSCL_M2M 0x1868
+#define CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC 0x186c
+#define CLK_CON_DIV_CLKCMU_MFCMSCL_MFC 0x1870
#define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c
#define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880
#define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884
@@ -83,6 +91,10 @@
#define CLK_CON_GAT_GATE_CLKCMU_IS_GDC 0x2054
#define CLK_CON_GAT_GATE_CLKCMU_IS_ITP 0x2058
#define CLK_CON_GAT_GATE_CLKCMU_IS_VRA 0x205c
+#define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG 0x2060
+#define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M 0x2064
+#define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC 0x2068
+#define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC 0x206c
#define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080
#define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084
#define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088
@@ -111,6 +123,10 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_MUX_MUX_CLKCMU_IS_GDC,
CLK_CON_MUX_MUX_CLKCMU_IS_ITP,
CLK_CON_MUX_MUX_CLKCMU_IS_VRA,
+ CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG,
+ CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M,
+ CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC,
+ CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC,
CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
CLK_CON_MUX_MUX_CLKCMU_PERI_IP,
CLK_CON_MUX_MUX_CLKCMU_PERI_UART,
@@ -128,6 +144,10 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_DIV_CLKCMU_IS_GDC,
CLK_CON_DIV_CLKCMU_IS_ITP,
CLK_CON_DIV_CLKCMU_IS_VRA,
+ CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG,
+ CLK_CON_DIV_CLKCMU_MFCMSCL_M2M,
+ CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC,
+ CLK_CON_DIV_CLKCMU_MFCMSCL_MFC,
CLK_CON_DIV_CLKCMU_PERI_BUS,
CLK_CON_DIV_CLKCMU_PERI_IP,
CLK_CON_DIV_CLKCMU_PERI_UART,
@@ -151,6 +171,10 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_GAT_GATE_CLKCMU_IS_GDC,
CLK_CON_GAT_GATE_CLKCMU_IS_ITP,
CLK_CON_GAT_GATE_CLKCMU_IS_VRA,
+ CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG,
+ CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M,
+ CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC,
+ CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC,
CLK_CON_GAT_GATE_CLKCMU_PERI_BUS,
CLK_CON_GAT_GATE_CLKCMU_PERI_IP,
CLK_CON_GAT_GATE_CLKCMU_PERI_UART,
@@ -209,6 +233,15 @@ PNAME(mout_is_vra_p) = { "dout_shared0_div2", "dout_shared1_div2",
"dout_shared0_div3", "dout_shared1_div3" };
PNAME(mout_is_gdc_p) = { "dout_shared0_div2", "dout_shared1_div2",
"dout_shared0_div3", "dout_shared1_div3" };
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_MFCMSCL */
+PNAME(mout_mfcmscl_mfc_p) = { "dout_shared1_div2", "dout_shared0_div3",
+ "dout_shared1_div3", "dout_shared0_div4" };
+PNAME(mout_mfcmscl_m2m_p) = { "dout_shared1_div2", "dout_shared0_div3",
+ "dout_shared1_div3", "dout_shared0_div4" };
+PNAME(mout_mfcmscl_mcsc_p) = { "dout_shared1_div2", "dout_shared0_div3",
+ "dout_shared1_div3", "dout_shared0_div4" };
+PNAME(mout_mfcmscl_jpeg_p) = { "dout_shared0_div3", "dout_shared1_div3",
+ "dout_shared0_div4", "dout_shared1_div4" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" };
PNAME(mout_peri_uart_p) = { "oscclk", "dout_shared0_div4",
@@ -268,6 +301,16 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
MUX(CLK_MOUT_IS_GDC, "mout_is_gdc", mout_is_gdc_p,
CLK_CON_MUX_MUX_CLKCMU_IS_GDC, 0, 2),
+ /* MFCMSCL */
+ MUX(CLK_MOUT_MFCMSCL_MFC, "mout_mfcmscl_mfc", mout_mfcmscl_mfc_p,
+ CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC, 0, 2),
+ MUX(CLK_MOUT_MFCMSCL_M2M, "mout_mfcmscl_m2m", mout_mfcmscl_m2m_p,
+ CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M, 0, 2),
+ MUX(CLK_MOUT_MFCMSCL_MCSC, "mout_mfcmscl_mcsc", mout_mfcmscl_mcsc_p,
+ CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC, 0, 2),
+ MUX(CLK_MOUT_MFCMSCL_JPEG, "mout_mfcmscl_jpeg", mout_mfcmscl_jpeg_p,
+ CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG, 0, 2),
+
/* PERI */
MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
@@ -332,6 +375,16 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
DIV(CLK_DOUT_IS_GDC, "dout_is_gdc", "gout_is_gdc",
CLK_CON_DIV_CLKCMU_IS_GDC, 0, 4),
+ /* MFCMSCL */
+ DIV(CLK_DOUT_MFCMSCL_MFC, "dout_mfcmscl_mfc", "gout_mfcmscl_mfc",
+ CLK_CON_DIV_CLKCMU_MFCMSCL_MFC, 0, 4),
+ DIV(CLK_DOUT_MFCMSCL_M2M, "dout_mfcmscl_m2m", "gout_mfcmscl_m2m",
+ CLK_CON_DIV_CLKCMU_MFCMSCL_M2M, 0, 4),
+ DIV(CLK_DOUT_MFCMSCL_MCSC, "dout_mfcmscl_mcsc", "gout_mfcmscl_mcsc",
+ CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC, 0, 4),
+ DIV(CLK_DOUT_MFCMSCL_JPEG, "dout_mfcmscl_jpeg", "gout_mfcmscl_jpeg",
+ CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG, 0, 4),
+
/* PERI */
DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
@@ -383,6 +436,17 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
GATE(CLK_GOUT_IS_GDC, "gout_is_gdc", "mout_is_gdc",
CLK_CON_GAT_GATE_CLKCMU_IS_GDC, 21, CLK_IS_CRITICAL, 0),
+ /* MFCMSCL */
+ /* TODO: These have to be always enabled to access CMU_MFCMSCL regs */
+ GATE(CLK_GOUT_MFCMSCL_MFC, "gout_mfcmscl_mfc", "mout_mfcmscl_mfc",
+ CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC, 21, CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_MFCMSCL_M2M, "gout_mfcmscl_m2m", "mout_mfcmscl_m2m",
+ CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M, 21, CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_MFCMSCL_MCSC, "gout_mfcmscl_mcsc", "mout_mfcmscl_mcsc",
+ CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC, 21, CLK_IS_CRITICAL, 0),
+ GATE(CLK_GOUT_MFCMSCL_JPEG, "gout_mfcmscl_jpeg", "mout_mfcmscl_jpeg",
+ CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG, 21, CLK_IS_CRITICAL, 0),
+
/* PERI */
GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus",
CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
@@ -1148,6 +1212,115 @@ static const struct samsung_cmu_info is_cmu_info __initconst = {
.clk_name = "dout_is_bus",
};
+/* ---- CMU_MFCMSCL --------------------------------------------------------- */
+
+#define PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER 0x0600
+#define PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER 0x0610
+#define PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER 0x0620
+#define PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER 0x0630
+#define CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP 0x1800
+#define CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK 0x2000
+#define CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK 0x2038
+#define CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK 0x203c
+#define CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK 0x2048
+#define CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK 0x204c
+#define CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK 0x2050
+#define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK 0x2054
+#define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK 0x2058
+#define CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1 0x2074
+#define CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK 0x2078
+
+static const unsigned long mfcmscl_clk_regs[] __initconst = {
+ PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER,
+ PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER,
+ PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER,
+ PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER,
+ CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP,
+ CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK,
+ CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK,
+ CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK,
+ CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK,
+ CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK,
+ CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK,
+ CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK,
+ CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK,
+ CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1,
+ CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK,
+};
+
+/* List of parent clocks for Muxes in CMU_MFCMSCL */
+PNAME(mout_mfcmscl_mfc_user_p) = { "oscclk", "dout_mfcmscl_mfc" };
+PNAME(mout_mfcmscl_m2m_user_p) = { "oscclk", "dout_mfcmscl_m2m" };
+PNAME(mout_mfcmscl_mcsc_user_p) = { "oscclk", "dout_mfcmscl_mcsc" };
+PNAME(mout_mfcmscl_jpeg_user_p) = { "oscclk", "dout_mfcmscl_jpeg" };
+
+static const struct samsung_mux_clock mfcmscl_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_MFCMSCL_MFC_USER, "mout_mfcmscl_mfc_user",
+ mout_mfcmscl_mfc_user_p,
+ PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER, 4, 1),
+ MUX(CLK_MOUT_MFCMSCL_M2M_USER, "mout_mfcmscl_m2m_user",
+ mout_mfcmscl_m2m_user_p,
+ PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER, 4, 1),
+ MUX(CLK_MOUT_MFCMSCL_MCSC_USER, "mout_mfcmscl_mcsc_user",
+ mout_mfcmscl_mcsc_user_p,
+ PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER, 4, 1),
+ MUX(CLK_MOUT_MFCMSCL_JPEG_USER, "mout_mfcmscl_jpeg_user",
+ mout_mfcmscl_jpeg_user_p,
+ PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER, 4, 1),
+};
+
+static const struct samsung_div_clock mfcmscl_div_clks[] __initconst = {
+ DIV(CLK_DOUT_MFCMSCL_BUSP, "dout_mfcmscl_busp", "mout_mfcmscl_mfc_user",
+ CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP, 0, 3),
+};
+
+static const struct samsung_gate_clock mfcmscl_gate_clks[] __initconst = {
+ /* TODO: Should be enabled in MFC driver */
+ GATE(CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK, "gout_mfcmscl_cmu_mfcmscl_pclk",
+ "dout_mfcmscl_busp", CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK,
+ 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_GOUT_MFCMSCL_TZPC_PCLK, "gout_mfcmscl_tzpc_pclk",
+ "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_MFCMSCL_JPEG_ACLK, "gout_mfcmscl_jpeg_aclk",
+ "mout_mfcmscl_jpeg_user", CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_MFCMSCL_M2M_ACLK, "gout_mfcmscl_m2m_aclk",
+ "mout_mfcmscl_m2m_user", CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_MFCMSCL_MCSC_CLK, "gout_mfcmscl_mcsc_clk",
+ "mout_mfcmscl_mcsc_user", CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_MFCMSCL_MFC_ACLK, "gout_mfcmscl_mfc_aclk",
+ "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_MFCMSCL_PPMU_ACLK, "gout_mfcmscl_ppmu_aclk",
+ "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_MFCMSCL_PPMU_PCLK, "gout_mfcmscl_ppmu_pclk",
+ "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK,
+ 21, 0, 0),
+ GATE(CLK_GOUT_MFCMSCL_SYSMMU_CLK, "gout_mfcmscl_sysmmu_clk",
+ "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1,
+ 21, 0, 0),
+ GATE(CLK_GOUT_MFCMSCL_SYSREG_PCLK, "gout_mfcmscl_sysreg_pclk",
+ "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK,
+ 21, 0, 0),
+};
+
+static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = {
+ .mux_clks = mfcmscl_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(mfcmscl_mux_clks),
+ .div_clks = mfcmscl_div_clks,
+ .nr_div_clks = ARRAY_SIZE(mfcmscl_div_clks),
+ .gate_clks = mfcmscl_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(mfcmscl_gate_clks),
+ .nr_clk_ids = MFCMSCL_NR_CLK,
+ .clk_regs = mfcmscl_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(mfcmscl_clk_regs),
+ .clk_name = "dout_mfcmscl_mfc",
+};
+
/* ---- CMU_PERI ------------------------------------------------------------ */
/* Register Offset definitions for CMU_PERI (0x10030000) */
@@ -1533,6 +1706,9 @@ static const struct of_device_id exynos850_cmu_of_match[] = {
}, {
.compatible = "samsung,exynos850-cmu-is",
.data = &is_cmu_info,
+ }, {
+ .compatible = "samsung,exynos850-cmu-mfcmscl",
+ .data = &mfcmscl_cmu_info,
}, {
.compatible = "samsung,exynos850-cmu-core",
.data = &core_cmu_info,
--
2.30.2
Add missing clock domains to Exynos850 SoC device tree.
Signed-off-by: Sam Protsenko <[email protected]>
---
Changes in v2:
- (none)
arch/arm64/boot/dts/exynos/exynos850.dtsi | 38 +++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi
index 9076afd4bb3e..8e78b50416d8 100644
--- a/arch/arm64/boot/dts/exynos/exynos850.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi
@@ -286,6 +286,21 @@ cmu_top: clock-controller@120e0000 {
clock-names = "oscclk";
};
+ cmu_mfcmscl: clock-controller@12c00000 {
+ compatible = "samsung,exynos850-cmu-mfcmscl";
+ reg = <0x12c00000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_MFCMSCL_MFC>,
+ <&cmu_top CLK_DOUT_MFCMSCL_M2M>,
+ <&cmu_top CLK_DOUT_MFCMSCL_MCSC>,
+ <&cmu_top CLK_DOUT_MFCMSCL_JPEG>;
+ clock-names = "oscclk", "dout_mfcmscl_mfc",
+ "dout_mfcmscl_m2m", "dout_mfcmscl_mcsc",
+ "dout_mfcmscl_jpeg";
+ };
+
cmu_dpu: clock-controller@13000000 {
compatible = "samsung,exynos850-cmu-dpu";
reg = <0x13000000 0x8000>;
@@ -308,6 +323,29 @@ cmu_hsi: clock-controller@13400000 {
"dout_hsi_mmc_card", "dout_hsi_usb20drd";
};
+ cmu_is: clock-controller@14500000 {
+ compatible = "samsung,exynos850-cmu-is";
+ reg = <0x14500000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>,
+ <&cmu_top CLK_DOUT_IS_BUS>,
+ <&cmu_top CLK_DOUT_IS_ITP>,
+ <&cmu_top CLK_DOUT_IS_VRA>,
+ <&cmu_top CLK_DOUT_IS_GDC>;
+ clock-names = "oscclk", "dout_is_bus", "dout_is_itp",
+ "dout_is_vra", "dout_is_gdc";
+ };
+
+ cmu_aud: clock-controller@14a00000 {
+ compatible = "samsung,exynos850-cmu-aud";
+ reg = <0x14a00000 0x8000>;
+ #clock-cells = <1>;
+
+ clocks = <&oscclk>, <&cmu_top CLK_DOUT_AUD>;
+ clock-names = "oscclk", "dout_aud";
+ };
+
pinctrl_alive: pinctrl@11850000 {
compatible = "samsung,exynos850-pinctrl";
reg = <0x11850000 0x1000>;
--
2.30.2
Add all SysMMU nodes to Exynos850 SoC device tree.
Signed-off-by: Sam Protsenko <[email protected]>
---
Changes in v2:
- Sorted sysmmu nodes by unit address
arch/arm64/boot/dts/exynos/exynos850.dtsi | 45 +++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi
index 8e78b50416d8..c61441f3a89a 100644
--- a/arch/arm64/boot/dts/exynos/exynos850.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi
@@ -503,6 +503,51 @@ i2c_6: i2c@13890000 {
status = "disabled";
};
+ sysmmu_mfcmscl: sysmmu@12c50000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x12c50000 0x9000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "sysmmu";
+ clocks = <&cmu_mfcmscl CLK_GOUT_MFCMSCL_SYSMMU_CLK>;
+ #iommu-cells = <0>;
+ };
+
+ sysmmu_dpu: sysmmu@130c0000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x130c0000 0x9000>;
+ interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "sysmmu";
+ clocks = <&cmu_dpu CLK_GOUT_DPU_SMMU_CLK>;
+ #iommu-cells = <0>;
+ };
+
+ sysmmu_is0: sysmmu@14550000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x14550000 0x9000>;
+ interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "sysmmu";
+ clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS0_CLK>;
+ #iommu-cells = <0>;
+ };
+
+ sysmmu_is1: sysmmu@14570000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x14570000 0x9000>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "sysmmu";
+ clocks = <&cmu_is CLK_GOUT_IS_SYSMMU_IS1_CLK>;
+ #iommu-cells = <0>;
+ };
+
+ sysmmu_aud: sysmmu@14850000 {
+ compatible = "samsung,exynos-sysmmu";
+ reg = <0x14850000 0x9000>;
+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "sysmmu";
+ clocks = <&cmu_aud CLK_GOUT_AUD_SYSMMU_CLK>;
+ #iommu-cells = <0>;
+ };
+
sysreg_peri: syscon@10020000 {
compatible = "samsung,exynos850-sysreg", "syscon";
reg = <0x10020000 0x10000>;
--
2.30.2
Fix some typos in comments and do small coding style improvements.
Signed-off-by: Sam Protsenko <[email protected]>
---
Changes in v2:
- (none)
drivers/clk/samsung/clk-exynos850.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c
index cd9725f1dbf7..ef32546d3090 100644
--- a/drivers/clk/samsung/clk-exynos850.c
+++ b/drivers/clk/samsung/clk-exynos850.c
@@ -173,7 +173,6 @@ PNAME(mout_peri_uart_p) = { "oscclk", "dout_shared0_div4",
"dout_shared1_div4", "oscclk" };
PNAME(mout_peri_ip_p) = { "oscclk", "dout_shared0_div4",
"dout_shared1_div4", "oscclk" };
-
/* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */
PNAME(mout_dpu_p) = { "dout_shared0_div3", "dout_shared1_div3",
"dout_shared0_div4", "dout_shared1_div4" };
@@ -599,7 +598,7 @@ static const unsigned long hsi_clk_regs[] __initconst = {
CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY,
};
-/* List of parent clocks for Muxes in CMU_PERI */
+/* List of parent clocks for Muxes in CMU_HSI */
PNAME(mout_hsi_bus_user_p) = { "oscclk", "dout_hsi_bus" };
PNAME(mout_hsi_mmc_card_user_p) = { "oscclk", "dout_hsi_mmc_card" };
PNAME(mout_hsi_usb20drd_user_p) = { "oscclk", "dout_hsi_usb20drd" };
@@ -963,7 +962,7 @@ static const unsigned long dpu_clk_regs[] __initconst = {
CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK,
};
-/* List of parent clocks for Muxes in CMU_CORE */
+/* List of parent clocks for Muxes in CMU_DPU */
PNAME(mout_dpu_user_p) = { "oscclk", "dout_dpu" };
static const struct samsung_mux_clock dpu_mux_clks[] __initconst = {
--
2.30.2
CMU_AUD clock domain provides clocks for ABOX IP-core (audio subsystem).
According to Exynos850 TRM, CMU_AUD generates Cortex-A32 clock, bus
clock and audio clocks for BLK_AUD.
This patch adds next clocks:
- bus clocks in CMU_TOP needed for CMU_AUD
- all internal CMU_AUD clocks
- leaf clocks for Cortex-A32, Speedy FM, UAIF0..UAIF6 (Unified Audio
Interface), CNT (counter), ABOX IP-core, ASB (Asynchronous Bridge),
DAP (Debug Access Port), I2S Codec MCLK, D_TZPC (TrustZone
Protection Controller), GPIO, PPMU (Platform Performance Monitoring
Unit), SysMMU, SysReg and WDT
ABOX clock was marked as CLK_IGNORE_UNUSED, as system hangs on boot
otherwise. Once ABOX driver is implemented, maybe it can be handled
there instead.
Signed-off-by: Sam Protsenko <[email protected]>
---
Changes in v2:
- (none)
drivers/clk/samsung/clk-exynos850.c | 302 ++++++++++++++++++++++++++++
1 file changed, 302 insertions(+)
diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c
index ef32546d3090..c91984f3f14f 100644
--- a/drivers/clk/samsung/clk-exynos850.c
+++ b/drivers/clk/samsung/clk-exynos850.c
@@ -30,6 +30,7 @@
#define PLL_CON0_PLL_SHARED1 0x0180
#define PLL_CON3_PLL_SHARED1 0x018c
#define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000
+#define CLK_CON_MUX_MUX_CLKCMU_AUD 0x1004
#define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
#define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
#define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
@@ -42,6 +43,7 @@
#define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
#define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
#define CLK_CON_DIV_CLKCMU_APM_BUS 0x180c
+#define CLK_CON_DIV_CLKCMU_AUD 0x1810
#define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820
#define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824
#define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
@@ -60,6 +62,7 @@
#define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c
#define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0
#define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008
+#define CLK_CON_GAT_GATE_CLKCMU_AUD 0x200c
#define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
#define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
#define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
@@ -83,6 +86,7 @@ static const unsigned long top_clk_regs[] __initconst = {
PLL_CON0_PLL_SHARED1,
PLL_CON3_PLL_SHARED1,
CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
+ CLK_CON_MUX_MUX_CLKCMU_AUD,
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD,
@@ -95,6 +99,7 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_MUX_MUX_CLKCMU_PERI_IP,
CLK_CON_MUX_MUX_CLKCMU_PERI_UART,
CLK_CON_DIV_CLKCMU_APM_BUS,
+ CLK_CON_DIV_CLKCMU_AUD,
CLK_CON_DIV_CLKCMU_CORE_BUS,
CLK_CON_DIV_CLKCMU_CORE_CCI,
CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD,
@@ -113,6 +118,7 @@ static const unsigned long top_clk_regs[] __initconst = {
CLK_CON_DIV_PLL_SHARED1_DIV3,
CLK_CON_DIV_PLL_SHARED1_DIV4,
CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
+ CLK_CON_GAT_GATE_CLKCMU_AUD,
CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD,
@@ -148,6 +154,9 @@ PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */
PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared0_div4", "pll_shared1_div4" };
+/* List of parent clocks for Muxes in CMU_TOP: for CMU_AUD */
+PNAME(mout_aud_p) = { "fout_shared1_pll", "dout_shared0_div2",
+ "dout_shared1_div2", "dout_shared0_div3" };
/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3",
"dout_shared1_div3", "dout_shared0_div4" };
@@ -190,6 +199,10 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus",
mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
+ /* AUD */
+ MUX(CLK_MOUT_AUD, "mout_aud", mout_aud_p,
+ CLK_CON_MUX_MUX_CLKCMU_AUD, 0, 2),
+
/* CORE */
MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
@@ -240,6 +253,10 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
DIV(CLK_DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus",
"gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
+ /* AUD */
+ DIV(CLK_DOUT_AUD, "dout_aud", "gout_aud",
+ CLK_CON_DIV_CLKCMU_AUD, 0, 4),
+
/* CORE */
DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus",
CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
@@ -286,6 +303,10 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
GATE(CLK_GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus",
"mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0),
+ /* AUD */
+ GATE(CLK_GOUT_AUD, "gout_aud", "mout_aud",
+ CLK_CON_GAT_GATE_CLKCMU_AUD, 21, 0, 0),
+
/* DPU */
GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu",
CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
@@ -462,6 +483,284 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = {
.clk_name = "dout_clkcmu_apm_bus",
};
+/* ---- CMU_AUD ------------------------------------------------------------- */
+
+#define PLL_LOCKTIME_PLL_AUD 0x0000
+#define PLL_CON0_PLL_AUD 0x0100
+#define PLL_CON3_PLL_AUD 0x010c
+#define PLL_CON0_MUX_CLKCMU_AUD_CPU_USER 0x0600
+#define PLL_CON0_MUX_TICK_USB_USER 0x0610
+#define CLK_CON_MUX_MUX_CLK_AUD_CPU 0x1000
+#define CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH 0x1004
+#define CLK_CON_MUX_MUX_CLK_AUD_FM 0x1008
+#define CLK_CON_MUX_MUX_CLK_AUD_UAIF0 0x100c
+#define CLK_CON_MUX_MUX_CLK_AUD_UAIF1 0x1010
+#define CLK_CON_MUX_MUX_CLK_AUD_UAIF2 0x1014
+#define CLK_CON_MUX_MUX_CLK_AUD_UAIF3 0x1018
+#define CLK_CON_MUX_MUX_CLK_AUD_UAIF4 0x101c
+#define CLK_CON_MUX_MUX_CLK_AUD_UAIF5 0x1020
+#define CLK_CON_MUX_MUX_CLK_AUD_UAIF6 0x1024
+#define CLK_CON_DIV_DIV_CLK_AUD_MCLK 0x1800
+#define CLK_CON_DIV_DIV_CLK_AUD_AUDIF 0x1804
+#define CLK_CON_DIV_DIV_CLK_AUD_BUSD 0x1808
+#define CLK_CON_DIV_DIV_CLK_AUD_BUSP 0x180c
+#define CLK_CON_DIV_DIV_CLK_AUD_CNT 0x1810
+#define CLK_CON_DIV_DIV_CLK_AUD_CPU 0x1814
+#define CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK 0x1818
+#define CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG 0x181c
+#define CLK_CON_DIV_DIV_CLK_AUD_FM 0x1820
+#define CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY 0x1824
+#define CLK_CON_DIV_DIV_CLK_AUD_UAIF0 0x1828
+#define CLK_CON_DIV_DIV_CLK_AUD_UAIF1 0x182c
+#define CLK_CON_DIV_DIV_CLK_AUD_UAIF2 0x1830
+#define CLK_CON_DIV_DIV_CLK_AUD_UAIF3 0x1834
+#define CLK_CON_DIV_DIV_CLK_AUD_UAIF4 0x1838
+#define CLK_CON_DIV_DIV_CLK_AUD_UAIF5 0x183c
+#define CLK_CON_DIV_DIV_CLK_AUD_UAIF6 0x1840
+#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT 0x2000
+#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0 0x2004
+#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1 0x2008
+#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2 0x200c
+#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3 0x2010
+#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014
+#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018
+#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c
+#define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048
+#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c
+#define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050
+#define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32 0x2054
+#define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP 0x2058
+#define CLK_CON_GAT_GOUT_AUD_CODEC_MCLK 0x206c
+#define CLK_CON_GAT_GOUT_AUD_TZPC_PCLK 0x2070
+#define CLK_CON_GAT_GOUT_AUD_GPIO_PCLK 0x2074
+#define CLK_CON_GAT_GOUT_AUD_PPMU_ACLK 0x2088
+#define CLK_CON_GAT_GOUT_AUD_PPMU_PCLK 0x208c
+#define CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1 0x20b4
+#define CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK 0x20b8
+#define CLK_CON_GAT_GOUT_AUD_WDT_PCLK 0x20bc
+
+static const unsigned long aud_clk_regs[] __initconst = {
+ PLL_LOCKTIME_PLL_AUD,
+ PLL_CON0_PLL_AUD,
+ PLL_CON3_PLL_AUD,
+ PLL_CON0_MUX_CLKCMU_AUD_CPU_USER,
+ PLL_CON0_MUX_TICK_USB_USER,
+ CLK_CON_MUX_MUX_CLK_AUD_CPU,
+ CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH,
+ CLK_CON_MUX_MUX_CLK_AUD_FM,
+ CLK_CON_MUX_MUX_CLK_AUD_UAIF0,
+ CLK_CON_MUX_MUX_CLK_AUD_UAIF1,
+ CLK_CON_MUX_MUX_CLK_AUD_UAIF2,
+ CLK_CON_MUX_MUX_CLK_AUD_UAIF3,
+ CLK_CON_MUX_MUX_CLK_AUD_UAIF4,
+ CLK_CON_MUX_MUX_CLK_AUD_UAIF5,
+ CLK_CON_MUX_MUX_CLK_AUD_UAIF6,
+ CLK_CON_DIV_DIV_CLK_AUD_MCLK,
+ CLK_CON_DIV_DIV_CLK_AUD_AUDIF,
+ CLK_CON_DIV_DIV_CLK_AUD_BUSD,
+ CLK_CON_DIV_DIV_CLK_AUD_BUSP,
+ CLK_CON_DIV_DIV_CLK_AUD_CNT,
+ CLK_CON_DIV_DIV_CLK_AUD_CPU,
+ CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK,
+ CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG,
+ CLK_CON_DIV_DIV_CLK_AUD_FM,
+ CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY,
+ CLK_CON_DIV_DIV_CLK_AUD_UAIF0,
+ CLK_CON_DIV_DIV_CLK_AUD_UAIF1,
+ CLK_CON_DIV_DIV_CLK_AUD_UAIF2,
+ CLK_CON_DIV_DIV_CLK_AUD_UAIF3,
+ CLK_CON_DIV_DIV_CLK_AUD_UAIF4,
+ CLK_CON_DIV_DIV_CLK_AUD_UAIF5,
+ CLK_CON_DIV_DIV_CLK_AUD_UAIF6,
+ CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT,
+ CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0,
+ CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1,
+ CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2,
+ CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3,
+ CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4,
+ CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5,
+ CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6,
+ CLK_CON_GAT_GOUT_AUD_ABOX_ACLK,
+ CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY,
+ CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB,
+ CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32,
+ CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP,
+ CLK_CON_GAT_GOUT_AUD_CODEC_MCLK,
+ CLK_CON_GAT_GOUT_AUD_TZPC_PCLK,
+ CLK_CON_GAT_GOUT_AUD_GPIO_PCLK,
+ CLK_CON_GAT_GOUT_AUD_PPMU_ACLK,
+ CLK_CON_GAT_GOUT_AUD_PPMU_PCLK,
+ CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1,
+ CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK,
+ CLK_CON_GAT_GOUT_AUD_WDT_PCLK,
+};
+
+/* List of parent clocks for Muxes in CMU_AUD */
+PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll" };
+PNAME(mout_aud_cpu_user_p) = { "oscclk", "dout_aud" };
+PNAME(mout_aud_cpu_p) = { "dout_aud_cpu", "mout_aud_cpu_user" };
+PNAME(mout_aud_cpu_hch_p) = { "mout_aud_cpu", "oscclk" };
+PNAME(mout_aud_uaif0_p) = { "dout_aud_uaif0", "ioclk_audiocdclk0" };
+PNAME(mout_aud_uaif1_p) = { "dout_aud_uaif1", "ioclk_audiocdclk1" };
+PNAME(mout_aud_uaif2_p) = { "dout_aud_uaif2", "ioclk_audiocdclk2" };
+PNAME(mout_aud_uaif3_p) = { "dout_aud_uaif3", "ioclk_audiocdclk3" };
+PNAME(mout_aud_uaif4_p) = { "dout_aud_uaif4", "ioclk_audiocdclk4" };
+PNAME(mout_aud_uaif5_p) = { "dout_aud_uaif5", "ioclk_audiocdclk5" };
+PNAME(mout_aud_uaif6_p) = { "dout_aud_uaif6", "ioclk_audiocdclk6" };
+PNAME(mout_aud_tick_usb_user_p) = { "oscclk", "tick_usb" };
+PNAME(mout_aud_fm_p) = { "oscclk", "dout_aud_fm_spdy" };
+
+/*
+ * Do not provide PLL table to PLL_AUD, as MANUAL_PLL_CTRL bit is not set
+ * for that PLL by default, so set_rate operation would fail.
+ */
+static const struct samsung_pll_clock aud_pll_clks[] __initconst = {
+ PLL(pll_0831x, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
+ PLL_LOCKTIME_PLL_AUD, PLL_CON3_PLL_AUD, NULL),
+};
+
+static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = {
+ FRATE(IOCLK_AUDIOCDCLK0, "ioclk_audiocdclk0", NULL, 0, 25000000),
+ FRATE(IOCLK_AUDIOCDCLK1, "ioclk_audiocdclk1", NULL, 0, 25000000),
+ FRATE(IOCLK_AUDIOCDCLK2, "ioclk_audiocdclk2", NULL, 0, 25000000),
+ FRATE(IOCLK_AUDIOCDCLK3, "ioclk_audiocdclk3", NULL, 0, 25000000),
+ FRATE(IOCLK_AUDIOCDCLK4, "ioclk_audiocdclk4", NULL, 0, 25000000),
+ FRATE(IOCLK_AUDIOCDCLK5, "ioclk_audiocdclk5", NULL, 0, 25000000),
+ FRATE(IOCLK_AUDIOCDCLK6, "ioclk_audiocdclk6", NULL, 0, 25000000),
+ FRATE(TICK_USB, "tick_usb", NULL, 0, 60000000),
+};
+
+static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
+ MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p,
+ PLL_CON0_PLL_AUD, 4, 1),
+ MUX(CLK_MOUT_AUD_CPU_USER, "mout_aud_cpu_user", mout_aud_cpu_user_p,
+ PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 4, 1),
+ MUX(CLK_MOUT_AUD_TICK_USB_USER, "mout_aud_tick_usb_user",
+ mout_aud_tick_usb_user_p,
+ PLL_CON0_MUX_TICK_USB_USER, 4, 1),
+ MUX(CLK_MOUT_AUD_CPU, "mout_aud_cpu", mout_aud_cpu_p,
+ CLK_CON_MUX_MUX_CLK_AUD_CPU, 0, 1),
+ MUX(CLK_MOUT_AUD_CPU_HCH, "mout_aud_cpu_hch", mout_aud_cpu_hch_p,
+ CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 0, 1),
+ MUX(CLK_MOUT_AUD_UAIF0, "mout_aud_uaif0", mout_aud_uaif0_p,
+ CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0, 1),
+ MUX(CLK_MOUT_AUD_UAIF1, "mout_aud_uaif1", mout_aud_uaif1_p,
+ CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 0, 1),
+ MUX(CLK_MOUT_AUD_UAIF2, "mout_aud_uaif2", mout_aud_uaif2_p,
+ CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0, 1),
+ MUX(CLK_MOUT_AUD_UAIF3, "mout_aud_uaif3", mout_aud_uaif3_p,
+ CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 0, 1),
+ MUX(CLK_MOUT_AUD_UAIF4, "mout_aud_uaif4", mout_aud_uaif4_p,
+ CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 0, 1),
+ MUX(CLK_MOUT_AUD_UAIF5, "mout_aud_uaif5", mout_aud_uaif5_p,
+ CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 0, 1),
+ MUX(CLK_MOUT_AUD_UAIF6, "mout_aud_uaif6", mout_aud_uaif6_p,
+ CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 0, 1),
+ MUX(CLK_MOUT_AUD_FM, "mout_aud_fm", mout_aud_fm_p,
+ CLK_CON_MUX_MUX_CLK_AUD_FM, 0, 1),
+};
+
+static const struct samsung_div_clock aud_div_clks[] __initconst = {
+ DIV(CLK_DOUT_AUD_CPU, "dout_aud_cpu", "mout_aud_pll",
+ CLK_CON_DIV_DIV_CLK_AUD_CPU, 0, 4),
+ DIV(CLK_DOUT_AUD_BUSD, "dout_aud_busd", "mout_aud_pll",
+ CLK_CON_DIV_DIV_CLK_AUD_BUSD, 0, 4),
+ DIV(CLK_DOUT_AUD_BUSP, "dout_aud_busp", "mout_aud_pll",
+ CLK_CON_DIV_DIV_CLK_AUD_BUSP, 0, 4),
+ DIV(CLK_DOUT_AUD_AUDIF, "dout_aud_audif", "mout_aud_pll",
+ CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0, 9),
+ DIV(CLK_DOUT_AUD_CPU_ACLK, "dout_aud_cpu_aclk", "mout_aud_cpu_hch",
+ CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0, 3),
+ DIV(CLK_DOUT_AUD_CPU_PCLKDBG, "dout_aud_cpu_pclkdbg",
+ "mout_aud_cpu_hch",
+ CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0, 3),
+ DIV(CLK_DOUT_AUD_MCLK, "dout_aud_mclk", "dout_aud_audif",
+ CLK_CON_DIV_DIV_CLK_AUD_MCLK, 0, 2),
+ DIV(CLK_DOUT_AUD_CNT, "dout_aud_cnt", "dout_aud_audif",
+ CLK_CON_DIV_DIV_CLK_AUD_CNT, 0, 10),
+ DIV(CLK_DOUT_AUD_UAIF0, "dout_aud_uaif0", "dout_aud_audif",
+ CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0, 10),
+ DIV(CLK_DOUT_AUD_UAIF1, "dout_aud_uaif1", "dout_aud_audif",
+ CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 0, 10),
+ DIV(CLK_DOUT_AUD_UAIF2, "dout_aud_uaif2", "dout_aud_audif",
+ CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0, 10),
+ DIV(CLK_DOUT_AUD_UAIF3, "dout_aud_uaif3", "dout_aud_audif",
+ CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 0, 10),
+ DIV(CLK_DOUT_AUD_UAIF4, "dout_aud_uaif4", "dout_aud_audif",
+ CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 0, 10),
+ DIV(CLK_DOUT_AUD_UAIF5, "dout_aud_uaif5", "dout_aud_audif",
+ CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 0, 10),
+ DIV(CLK_DOUT_AUD_UAIF6, "dout_aud_uaif6", "dout_aud_audif",
+ CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 0, 10),
+ DIV(CLK_DOUT_AUD_FM_SPDY, "dout_aud_fm_spdy", "mout_aud_tick_usb_user",
+ CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 0, 1),
+ DIV(CLK_DOUT_AUD_FM, "dout_aud_fm", "mout_aud_fm",
+ CLK_CON_DIV_DIV_CLK_AUD_FM, 0, 10),
+};
+
+static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
+ GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", "mout_aud_cpu_hch",
+ CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0),
+ GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", "dout_aud_cpu_aclk",
+ CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, 21, 0, 0),
+ GATE(CLK_GOUT_AUD_DAP_CCLK, "gout_aud_dap_cclk", "dout_aud_cpu_pclkdbg",
+ CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP, 21, 0, 0),
+ /* TODO: Should be enabled in ABOX driver (or made CLK_IS_CRITICAL) */
+ GATE(CLK_GOUT_AUD_ABOX_ACLK, "gout_aud_abox_aclk", "dout_aud_busd",
+ CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, 21, CLK_IGNORE_UNUSED, 0),
+ GATE(CLK_GOUT_AUD_GPIO_PCLK, "gout_aud_gpio_pclk", "dout_aud_busd",
+ CLK_CON_GAT_GOUT_AUD_GPIO_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_AUD_PPMU_ACLK, "gout_aud_ppmu_aclk", "dout_aud_busd",
+ CLK_CON_GAT_GOUT_AUD_PPMU_ACLK, 21, 0, 0),
+ GATE(CLK_GOUT_AUD_PPMU_PCLK, "gout_aud_ppmu_pclk", "dout_aud_busd",
+ CLK_CON_GAT_GOUT_AUD_PPMU_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_AUD_SYSMMU_CLK, "gout_aud_sysmmu_clk", "dout_aud_busd",
+ CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1, 21, 0, 0),
+ GATE(CLK_GOUT_AUD_SYSREG_PCLK, "gout_aud_sysreg_pclk", "dout_aud_busd",
+ CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_AUD_WDT_PCLK, "gout_aud_wdt_pclk", "dout_aud_busd",
+ CLK_CON_GAT_GOUT_AUD_WDT_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_AUD_TZPC_PCLK, "gout_aud_tzpc_pclk", "dout_aud_busp",
+ CLK_CON_GAT_GOUT_AUD_TZPC_PCLK, 21, 0, 0),
+ GATE(CLK_GOUT_AUD_CODEC_MCLK, "gout_aud_codec_mclk", "dout_aud_mclk",
+ CLK_CON_GAT_GOUT_AUD_CODEC_MCLK, 21, 0, 0),
+ GATE(CLK_GOUT_AUD_CNT_BCLK, "gout_aud_cnt_bclk", "dout_aud_cnt",
+ CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT, 21, 0, 0),
+ GATE(CLK_GOUT_AUD_UAIF0_BCLK, "gout_aud_uaif0_bclk", "mout_aud_uaif0",
+ CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0, 21, 0, 0),
+ GATE(CLK_GOUT_AUD_UAIF1_BCLK, "gout_aud_uaif1_bclk", "mout_aud_uaif1",
+ CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1, 21, 0, 0),
+ GATE(CLK_GOUT_AUD_UAIF2_BCLK, "gout_aud_uaif2_bclk", "mout_aud_uaif2",
+ CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2, 21, 0, 0),
+ GATE(CLK_GOUT_AUD_UAIF3_BCLK, "gout_aud_uaif3_bclk", "mout_aud_uaif3",
+ CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3, 21, 0, 0),
+ GATE(CLK_GOUT_AUD_UAIF4_BCLK, "gout_aud_uaif4_bclk", "mout_aud_uaif4",
+ CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, 21, 0, 0),
+ GATE(CLK_GOUT_AUD_UAIF5_BCLK, "gout_aud_uaif5_bclk", "mout_aud_uaif5",
+ CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, 21, 0, 0),
+ GATE(CLK_GOUT_AUD_UAIF6_BCLK, "gout_aud_uaif6_bclk", "mout_aud_uaif6",
+ CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, 21, 0, 0),
+ GATE(CLK_GOUT_AUD_SPDY_BCLK, "gout_aud_spdy_bclk", "dout_aud_fm",
+ CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, 21, 0, 0),
+};
+
+static const struct samsung_cmu_info aud_cmu_info __initconst = {
+ .pll_clks = aud_pll_clks,
+ .nr_pll_clks = ARRAY_SIZE(aud_pll_clks),
+ .mux_clks = aud_mux_clks,
+ .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
+ .div_clks = aud_div_clks,
+ .nr_div_clks = ARRAY_SIZE(aud_div_clks),
+ .gate_clks = aud_gate_clks,
+ .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
+ .fixed_clks = aud_fixed_clks,
+ .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
+ .nr_clk_ids = AUD_NR_CLK,
+ .clk_regs = aud_clk_regs,
+ .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
+ .clk_name = "dout_aud",
+};
+
/* ---- CMU_CMGP ------------------------------------------------------------ */
/* Register Offset definitions for CMU_CMGP (0x11c00000) */
@@ -1026,6 +1325,9 @@ static const struct of_device_id exynos850_cmu_of_match[] = {
{
.compatible = "samsung,exynos850-cmu-apm",
.data = &apm_cmu_info,
+ }, {
+ .compatible = "samsung,exynos850-cmu-aud",
+ .data = &aud_cmu_info,
}, {
.compatible = "samsung,exynos850-cmu-cmgp",
.data = &cmgp_cmu_info,
--
2.30.2
CMU_MFCMSCL generates MFC, M2M, MCSC and JPEG clocks for BLK_MFCMSCL.
Add clock indices and binding documentation for CMU_MFCMSCL.
Signed-off-by: Sam Protsenko <[email protected]>
---
Changes in v2:
- (none)
.../clock/samsung,exynos850-clock.yaml | 25 +++++++++++++++
include/dt-bindings/clock/exynos850.h | 32 ++++++++++++++++++-
2 files changed, 56 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
index 7f2e0b1c764c..141cf173f87d 100644
--- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
@@ -39,6 +39,7 @@ properties:
- samsung,exynos850-cmu-dpu
- samsung,exynos850-cmu-hsi
- samsung,exynos850-cmu-is
+ - samsung,exynos850-cmu-mfcmscl
- samsung,exynos850-cmu-peri
clocks:
@@ -216,6 +217,30 @@ allOf:
- const: dout_is_vra
- const: dout_is_gdc
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos850-cmu-mfcmscl
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: Multi-Format Codec clock (from CMU_TOP)
+ - description: Memory to Memory Scaler clock (from CMU_TOP)
+ - description: Multi-Channel Scaler clock (from CMU_TOP)
+ - description: JPEG codec clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_mfcmscl_mfc
+ - const: dout_mfcmscl_m2m
+ - const: dout_mfcmscl_mcsc
+ - const: dout_mfcmscl_jpeg
+
- if:
properties:
compatible:
diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
index f8bf26f118c1..88d5289883d3 100644
--- a/include/dt-bindings/clock/exynos850.h
+++ b/include/dt-bindings/clock/exynos850.h
@@ -73,7 +73,19 @@
#define CLK_DOUT_IS_ITP 61
#define CLK_DOUT_IS_VRA 62
#define CLK_DOUT_IS_GDC 63
-#define TOP_NR_CLK 64
+#define CLK_MOUT_MFCMSCL_MFC 64
+#define CLK_MOUT_MFCMSCL_M2M 65
+#define CLK_MOUT_MFCMSCL_MCSC 66
+#define CLK_MOUT_MFCMSCL_JPEG 67
+#define CLK_GOUT_MFCMSCL_MFC 68
+#define CLK_GOUT_MFCMSCL_M2M 69
+#define CLK_GOUT_MFCMSCL_MCSC 70
+#define CLK_GOUT_MFCMSCL_JPEG 71
+#define CLK_DOUT_MFCMSCL_MFC 72
+#define CLK_DOUT_MFCMSCL_M2M 73
+#define CLK_DOUT_MFCMSCL_MCSC 74
+#define CLK_DOUT_MFCMSCL_JPEG 75
+#define TOP_NR_CLK 76
/* CMU_APM */
#define CLK_RCO_I3C_PMIC 1
@@ -225,6 +237,24 @@
#define CLK_GOUT_IS_SYSREG_PCLK 23
#define IS_NR_CLK 24
+/* CMU_MFCMSCL */
+#define CLK_MOUT_MFCMSCL_MFC_USER 1
+#define CLK_MOUT_MFCMSCL_M2M_USER 2
+#define CLK_MOUT_MFCMSCL_MCSC_USER 3
+#define CLK_MOUT_MFCMSCL_JPEG_USER 4
+#define CLK_DOUT_MFCMSCL_BUSP 5
+#define CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK 6
+#define CLK_GOUT_MFCMSCL_TZPC_PCLK 7
+#define CLK_GOUT_MFCMSCL_JPEG_ACLK 8
+#define CLK_GOUT_MFCMSCL_M2M_ACLK 9
+#define CLK_GOUT_MFCMSCL_MCSC_CLK 10
+#define CLK_GOUT_MFCMSCL_MFC_ACLK 11
+#define CLK_GOUT_MFCMSCL_PPMU_ACLK 12
+#define CLK_GOUT_MFCMSCL_PPMU_PCLK 13
+#define CLK_GOUT_MFCMSCL_SYSMMU_CLK 14
+#define CLK_GOUT_MFCMSCL_SYSREG_PCLK 15
+#define MFCMSCL_NR_CLK 16
+
/* CMU_PERI */
#define CLK_MOUT_PERI_BUS_USER 1
#define CLK_MOUT_PERI_UART_USER 2
--
2.30.2
On 09/08/2022 14:33, Sam Protsenko wrote:
> CMU_AUD clock domain provides clocks for ABOX IP-core (audio subsystem).
> According to Exynos850 TRM, CMU_AUD generates Cortex-A32 clock, bus
> clock and audio clocks for BLK_AUD.
>
> This patch adds next clocks:
> - bus clocks in CMU_TOP needed for CMU_AUD
> - all internal CMU_AUD clocks
> - leaf clocks for Cortex-A32, Speedy FM, UAIF0..UAIF6 (Unified Audio
> Interface), CNT (counter), ABOX IP-core, ASB (Asynchronous Bridge),
> DAP (Debug Access Port), I2S Codec MCLK, D_TZPC (TrustZone
> Protection Controller), GPIO, PPMU (Platform Performance Monitoring
> Unit), SysMMU, SysReg and WDT
>
> ABOX clock was marked as CLK_IGNORE_UNUSED, as system hangs on boot
> otherwise. Once ABOX driver is implemented, maybe it can be handled
> there instead.
>
> Signed-off-by: Sam Protsenko <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 09/08/2022 14:33, Sam Protsenko wrote:
> Fix some typos in comments and do small coding style improvements.
>
> Signed-off-by: Sam Protsenko <[email protected]>
> ---
> Changes in v2:
> - (none)
>
> drivers/clk/samsung/clk-exynos850.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 09/08/2022 14:33, Sam Protsenko wrote:
> CMU_AUD generates Cortex-A32 clock, bus clock and audio clocks for
> BLK_AUD. Add clock indices and binding documentation for CMU_AUD.
>
> Signed-off-by: Sam Protsenko <[email protected]>
> ---
> Changes in v2:
> - (none)
>
> .../clock/samsung,exynos850-clock.yaml | 19 ++++++
> include/dt-bindings/clock/exynos850.h | 68 ++++++++++++++++++-
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Sylwester,
The DTS depends on these, so I can apply headers and provide you a tag
with them. We could try also the other way, but Arnd is picky about it.
Best regards,
Krzysztof
On 09/08/2022 14:33, Sam Protsenko wrote:
> CMU_IS clock domain provides clocks for IS IP-core (Image Signal
> Processing Subsystem). According to Exynos850 TRM, CMU_IS generates
> CSIS, IPP, ITP, VRA and GDC clocks for BLK_IS.
>
> This patch adds next clocks:
> - bus clocks in CMU_TOP needed for CMU_IS
> - all internal CMU_IS clocks
> - leaf clocks for IS IP-core, CSIS (Camera Serial Interface Slave),
> D_TZPC (TrustZone Protection Controller), CSIS DMA, GDC (Geometric
> Distortion Correction), IPP (Image Preprocessing Processing core),
> ITP (Image Texture Processing core), MCSC (Multi-Channel Scaler),
> VRA (Visual Recognition Accelerator), PPMU (Platform Performance
> Monitoring Unit), SysMMU and SysReg
>
> IS related gate clocks in CMU_TOP were marked as CLK_IS_CRITICAL,
> because:
> 1. All of those have to be enabled in order to read
> /sys/kernel/debug/clk/clk_summary file
This sounds exactly like previous ISP clock hangs:
https://lore.kernel.org/all/[email protected]/
It looks like missing power domain references and your CLK_IS_CRITICAL
is not correct. These are not critical clocks.
> 2. When some user driver (e.g. exynos-sysmmu) disables some derived
> leaf clock, it can lead to CMU_TOP clocks disable, which then makes
> the system hang. To prevent that, the CLK_IS_CRITICAL flag is used,
> as CLK_IGNORE_UNUSED is not enough.
These are not critical clocks and usage of CLK_IS_CRITICAL is not
appropriate. This looks like the same has as with other ISP, so it
should be handled in similar way.
Best regards,
Krzysztof
On 09/08/2022 14:33, Sam Protsenko wrote:
> CMU_MFCMSCL clock domain provides clocks for MFC (Multi-Format Codec),
> JPEG Codec and Scaler IP-cores. According to Exynos850 TRM, CMU_MFCMSCL
> generates MFC, M2M, MCSC and JPEG clocks for BLK_MFCMSCL.
>
> This patch adds next clocks:
> - bus clocks in CMU_TOP for CMU_MFCMSCL
> - all internal CMU_MFCMSCL clocks
> - leaf clocks for MFCMSCL, TZPC (TrustZone Protection Controller),
> JPEG codec, M2M (Memory-to-Memory), MCSC (Multi-Channel Scaler),
> MFC (Multi-Format Codec), PPMU (Platform Performance Monitoring
> Unit), SysMMU and SysReg
>
> MFCMSCL related gate clocks in CMU_TOP were marked as CLK_IS_CRITICAL,
> because:
> 1. All of those have to be enabled in order to read
> /sys/kernel/debug/clk/clk_summary file
> 2. When some user driver (e.g. exynos-sysmmu) disables some derived
> leaf clock, it can lead to CMU_TOP clocks disable, which then makes
> the system hang. To prevent that, the CLK_IS_CRITICAL flag is used,
> as CLK_IGNORE_UNUSED is not enough.
No, same as with ISP these are not critical clocks.
Best regards,
Krzysztof
On 09/08/2022 14:33, Sam Protsenko wrote:
> CMU_AUD clock domain provides clocks for ABOX IP-core (audio subsystem).
> According to Exynos850 TRM, CMU_AUD generates Cortex-A32 clock, bus
> clock and audio clocks for BLK_AUD.
>
> This patch adds next clocks:
> - bus clocks in CMU_TOP needed for CMU_AUD
> - all internal CMU_AUD clocks
> - leaf clocks for Cortex-A32, Speedy FM, UAIF0..UAIF6 (Unified Audio
> Interface), CNT (counter), ABOX IP-core, ASB (Asynchronous Bridge),
> DAP (Debug Access Port), I2S Codec MCLK, D_TZPC (TrustZone
> Protection Controller), GPIO, PPMU (Platform Performance Monitoring
> Unit), SysMMU, SysReg and WDT
>
> ABOX clock was marked as CLK_IGNORE_UNUSED, as system hangs on boot
> otherwise. Once ABOX driver is implemented, maybe it can be handled
> there instead.
>
> Signed-off-by: Sam Protsenko <[email protected]>
> ---
> Changes in v2:
> - (none)
>
> drivers/clk/samsung/clk-exynos850.c | 302 ++++++++++++++++++++++++++++
> 1 file changed, 302 insertions(+)
Reviewed-by: Krzysztof Kozlowski <[email protected]>
Best regards,
Krzysztof
On 22. 8. 9. 20:33, Sam Protsenko wrote:
> Fix some typos in comments and do small coding style improvements.
>
> Signed-off-by: Sam Protsenko <[email protected]>
> ---
> Changes in v2:
> - (none)
>
> drivers/clk/samsung/clk-exynos850.c | 5 ++---
> 1 file changed, 2 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c
> index cd9725f1dbf7..ef32546d3090 100644
> --- a/drivers/clk/samsung/clk-exynos850.c
> +++ b/drivers/clk/samsung/clk-exynos850.c
> @@ -173,7 +173,6 @@ PNAME(mout_peri_uart_p) = { "oscclk", "dout_shared0_div4",
> "dout_shared1_div4", "oscclk" };
> PNAME(mout_peri_ip_p) = { "oscclk", "dout_shared0_div4",
> "dout_shared1_div4", "oscclk" };
> -
> /* List of parent clocks for Muxes in CMU_TOP: for CMU_DPU */
> PNAME(mout_dpu_p) = { "dout_shared0_div3", "dout_shared1_div3",
> "dout_shared0_div4", "dout_shared1_div4" };
> @@ -599,7 +598,7 @@ static const unsigned long hsi_clk_regs[] __initconst = {
> CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY,
> };
>
> -/* List of parent clocks for Muxes in CMU_PERI */
> +/* List of parent clocks for Muxes in CMU_HSI */
> PNAME(mout_hsi_bus_user_p) = { "oscclk", "dout_hsi_bus" };
> PNAME(mout_hsi_mmc_card_user_p) = { "oscclk", "dout_hsi_mmc_card" };
> PNAME(mout_hsi_usb20drd_user_p) = { "oscclk", "dout_hsi_usb20drd" };
> @@ -963,7 +962,7 @@ static const unsigned long dpu_clk_regs[] __initconst = {
> CLK_CON_GAT_GOUT_DPU_SYSREG_PCLK,
> };
>
> -/* List of parent clocks for Muxes in CMU_CORE */
> +/* List of parent clocks for Muxes in CMU_DPU */
> PNAME(mout_dpu_user_p) = { "oscclk", "dout_dpu" };
>
> static const struct samsung_mux_clock dpu_mux_clks[] __initconst = {
Acked-by: Chanwoo Choi <[email protected]>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
On 22. 8. 9. 20:33, Sam Protsenko wrote:
> CMU_IS clock domain provides clocks for IS IP-core (Image Signal
> Processing Subsystem). According to Exynos850 TRM, CMU_IS generates
> CSIS, IPP, ITP, VRA and GDC clocks for BLK_IS.
>
> This patch adds next clocks:
> - bus clocks in CMU_TOP needed for CMU_IS
> - all internal CMU_IS clocks
> - leaf clocks for IS IP-core, CSIS (Camera Serial Interface Slave),
> D_TZPC (TrustZone Protection Controller), CSIS DMA, GDC (Geometric
> Distortion Correction), IPP (Image Preprocessing Processing core),
> ITP (Image Texture Processing core), MCSC (Multi-Channel Scaler),
> VRA (Visual Recognition Accelerator), PPMU (Platform Performance
> Monitoring Unit), SysMMU and SysReg
>
> IS related gate clocks in CMU_TOP were marked as CLK_IS_CRITICAL,
> because:
> 1. All of those have to be enabled in order to read
> /sys/kernel/debug/clk/clk_summary file
> 2. When some user driver (e.g. exynos-sysmmu) disables some derived
> leaf clock, it can lead to CMU_TOP clocks disable, which then makes
> the system hang. To prevent that, the CLK_IS_CRITICAL flag is used,
> as CLK_IGNORE_UNUSED is not enough.
>
> Signed-off-by: Sam Protsenko <[email protected]>
> ---
> Changes in v2:
> - (none)
>
> drivers/clk/samsung/clk-exynos850.c | 199 ++++++++++++++++++++++++++++
> 1 file changed, 199 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c
> index c91984f3f14f..18a36d58101e 100644
> --- a/drivers/clk/samsung/clk-exynos850.c
> +++ b/drivers/clk/samsung/clk-exynos850.c
> @@ -39,6 +39,10 @@
> #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c
> #define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040
> #define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044
> +#define CLK_CON_MUX_MUX_CLKCMU_IS_BUS 0x1048
> +#define CLK_CON_MUX_MUX_CLKCMU_IS_GDC 0x104c
> +#define CLK_CON_MUX_MUX_CLKCMU_IS_ITP 0x1050
> +#define CLK_CON_MUX_MUX_CLKCMU_IS_VRA 0x1054
> #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070
> #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
> #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
> @@ -52,6 +56,10 @@
> #define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848
> #define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c
> #define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850
> +#define CLK_CON_DIV_CLKCMU_IS_BUS 0x1854
> +#define CLK_CON_DIV_CLKCMU_IS_GDC 0x1858
> +#define CLK_CON_DIV_CLKCMU_IS_ITP 0x185c
> +#define CLK_CON_DIV_CLKCMU_IS_VRA 0x1860
> #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c
> #define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880
> #define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884
> @@ -71,6 +79,10 @@
> #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044
> #define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048
> #define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c
> +#define CLK_CON_GAT_GATE_CLKCMU_IS_BUS 0x2050
> +#define CLK_CON_GAT_GATE_CLKCMU_IS_GDC 0x2054
> +#define CLK_CON_GAT_GATE_CLKCMU_IS_ITP 0x2058
> +#define CLK_CON_GAT_GATE_CLKCMU_IS_VRA 0x205c
> #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080
> #define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084
> #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088
> @@ -95,6 +107,10 @@ static const unsigned long top_clk_regs[] __initconst = {
> CLK_CON_MUX_MUX_CLKCMU_HSI_BUS,
> CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD,
> CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD,
> + CLK_CON_MUX_MUX_CLKCMU_IS_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_IS_GDC,
> + CLK_CON_MUX_MUX_CLKCMU_IS_ITP,
> + CLK_CON_MUX_MUX_CLKCMU_IS_VRA,
> CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
> CLK_CON_MUX_MUX_CLKCMU_PERI_IP,
> CLK_CON_MUX_MUX_CLKCMU_PERI_UART,
> @@ -108,6 +124,10 @@ static const unsigned long top_clk_regs[] __initconst = {
> CLK_CON_DIV_CLKCMU_HSI_BUS,
> CLK_CON_DIV_CLKCMU_HSI_MMC_CARD,
> CLK_CON_DIV_CLKCMU_HSI_USB20DRD,
> + CLK_CON_DIV_CLKCMU_IS_BUS,
> + CLK_CON_DIV_CLKCMU_IS_GDC,
> + CLK_CON_DIV_CLKCMU_IS_ITP,
> + CLK_CON_DIV_CLKCMU_IS_VRA,
> CLK_CON_DIV_CLKCMU_PERI_BUS,
> CLK_CON_DIV_CLKCMU_PERI_IP,
> CLK_CON_DIV_CLKCMU_PERI_UART,
> @@ -127,6 +147,10 @@ static const unsigned long top_clk_regs[] __initconst = {
> CLK_CON_GAT_GATE_CLKCMU_HSI_BUS,
> CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD,
> CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD,
> + CLK_CON_GAT_GATE_CLKCMU_IS_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_IS_GDC,
> + CLK_CON_GAT_GATE_CLKCMU_IS_ITP,
> + CLK_CON_GAT_GATE_CLKCMU_IS_VRA,
> CLK_CON_GAT_GATE_CLKCMU_PERI_BUS,
> CLK_CON_GAT_GATE_CLKCMU_PERI_IP,
> CLK_CON_GAT_GATE_CLKCMU_PERI_UART,
> @@ -176,6 +200,15 @@ PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2",
> "oscclk", "oscclk" };
> PNAME(mout_hsi_usb20drd_p) = { "oscclk", "dout_shared0_div4",
> "dout_shared1_div4", "oscclk" };
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_IS */
> +PNAME(mout_is_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
> + "dout_shared0_div3", "dout_shared1_div3" };
> +PNAME(mout_is_itp_p) = { "dout_shared0_div2", "dout_shared1_div2",
> + "dout_shared0_div3", "dout_shared1_div3" };
> +PNAME(mout_is_vra_p) = { "dout_shared0_div2", "dout_shared1_div2",
> + "dout_shared0_div3", "dout_shared1_div3" };
> +PNAME(mout_is_gdc_p) = { "dout_shared0_div2", "dout_shared1_div2",
> + "dout_shared0_div3", "dout_shared1_div3" };
> /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
> PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" };
> PNAME(mout_peri_uart_p) = { "oscclk", "dout_shared0_div4",
> @@ -225,6 +258,16 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
> MUX(CLK_MOUT_HSI_USB20DRD, "mout_hsi_usb20drd", mout_hsi_usb20drd_p,
> CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, 0, 2),
>
> + /* IS */
> + MUX(CLK_MOUT_IS_BUS, "mout_is_bus", mout_is_bus_p,
> + CLK_CON_MUX_MUX_CLKCMU_IS_BUS, 0, 2),
> + MUX(CLK_MOUT_IS_ITP, "mout_is_itp", mout_is_itp_p,
> + CLK_CON_MUX_MUX_CLKCMU_IS_ITP, 0, 2),
> + MUX(CLK_MOUT_IS_VRA, "mout_is_vra", mout_is_vra_p,
> + CLK_CON_MUX_MUX_CLKCMU_IS_VRA, 0, 2),
> + MUX(CLK_MOUT_IS_GDC, "mout_is_gdc", mout_is_gdc_p,
> + CLK_CON_MUX_MUX_CLKCMU_IS_GDC, 0, 2),
> +
> /* PERI */
> MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
> CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
> @@ -279,6 +322,16 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
> DIV(CLK_DOUT_HSI_USB20DRD, "dout_hsi_usb20drd", "gout_hsi_usb20drd",
> CLK_CON_DIV_CLKCMU_HSI_USB20DRD, 0, 4),
>
> + /* IS */
> + DIV(CLK_DOUT_IS_BUS, "dout_is_bus", "gout_is_bus",
> + CLK_CON_DIV_CLKCMU_IS_BUS, 0, 4),
> + DIV(CLK_DOUT_IS_ITP, "dout_is_itp", "gout_is_itp",
> + CLK_CON_DIV_CLKCMU_IS_ITP, 0, 4),
> + DIV(CLK_DOUT_IS_VRA, "dout_is_vra", "gout_is_vra",
> + CLK_CON_DIV_CLKCMU_IS_VRA, 0, 4),
> + DIV(CLK_DOUT_IS_GDC, "dout_is_gdc", "gout_is_gdc",
> + CLK_CON_DIV_CLKCMU_IS_GDC, 0, 4),
> +
> /* PERI */
> DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
> CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
> @@ -319,6 +372,17 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
> GATE(CLK_GOUT_HSI_USB20DRD, "gout_hsi_usb20drd", "mout_hsi_usb20drd",
> CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, 21, 0, 0),
>
> + /* IS */
> + /* TODO: These clocks have to be always enabled to access CMU_IS regs */
> + GATE(CLK_GOUT_IS_BUS, "gout_is_bus", "mout_is_bus",
> + CLK_CON_GAT_GATE_CLKCMU_IS_BUS, 21, CLK_IS_CRITICAL, 0),
> + GATE(CLK_GOUT_IS_ITP, "gout_is_itp", "mout_is_itp",
> + CLK_CON_GAT_GATE_CLKCMU_IS_ITP, 21, CLK_IS_CRITICAL, 0),
> + GATE(CLK_GOUT_IS_VRA, "gout_is_vra", "mout_is_vra",
> + CLK_CON_GAT_GATE_CLKCMU_IS_VRA, 21, CLK_IS_CRITICAL, 0),
> + GATE(CLK_GOUT_IS_GDC, "gout_is_gdc", "mout_is_gdc",
> + CLK_CON_GAT_GATE_CLKCMU_IS_GDC, 21, CLK_IS_CRITICAL, 0),
> +
> /* PERI */
> GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus",
> CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
> @@ -952,6 +1016,138 @@ static const struct samsung_cmu_info hsi_cmu_info __initconst = {
> .clk_name = "dout_hsi_bus",
> };
>
> +/* ---- CMU_IS -------------------------------------------------------------- */
> +
> +#define PLL_CON0_MUX_CLKCMU_IS_BUS_USER 0x0600
> +#define PLL_CON0_MUX_CLKCMU_IS_GDC_USER 0x0610
> +#define PLL_CON0_MUX_CLKCMU_IS_ITP_USER 0x0620
> +#define PLL_CON0_MUX_CLKCMU_IS_VRA_USER 0x0630
> +#define CLK_CON_DIV_DIV_CLK_IS_BUSP 0x1800
> +#define CLK_CON_GAT_CLK_IS_CMU_IS_PCLK 0x2000
> +#define CLK_CON_GAT_GOUT_IS_CSIS0_ACLK 0x2040
> +#define CLK_CON_GAT_GOUT_IS_CSIS1_ACLK 0x2044
> +#define CLK_CON_GAT_GOUT_IS_CSIS2_ACLK 0x2048
> +#define CLK_CON_GAT_GOUT_IS_TZPC_PCLK 0x204c
> +#define CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA 0x2050
> +#define CLK_CON_GAT_GOUT_IS_CLK_GDC 0x2054
> +#define CLK_CON_GAT_GOUT_IS_CLK_IPP 0x2058
> +#define CLK_CON_GAT_GOUT_IS_CLK_ITP 0x205c
> +#define CLK_CON_GAT_GOUT_IS_CLK_MCSC 0x2060
> +#define CLK_CON_GAT_GOUT_IS_CLK_VRA 0x2064
> +#define CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK 0x2074
> +#define CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK 0x2078
> +#define CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK 0x207c
> +#define CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK 0x2080
> +#define CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1 0x2098
> +#define CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1 0x209c
> +#define CLK_CON_GAT_GOUT_IS_SYSREG_PCLK 0x20a0
> +
> +static const unsigned long is_clk_regs[] __initconst = {
> + PLL_CON0_MUX_CLKCMU_IS_BUS_USER,
> + PLL_CON0_MUX_CLKCMU_IS_GDC_USER,
> + PLL_CON0_MUX_CLKCMU_IS_ITP_USER,
> + PLL_CON0_MUX_CLKCMU_IS_VRA_USER,
> + CLK_CON_DIV_DIV_CLK_IS_BUSP,
> + CLK_CON_GAT_CLK_IS_CMU_IS_PCLK,
> + CLK_CON_GAT_GOUT_IS_CSIS0_ACLK,
> + CLK_CON_GAT_GOUT_IS_CSIS1_ACLK,
> + CLK_CON_GAT_GOUT_IS_CSIS2_ACLK,
> + CLK_CON_GAT_GOUT_IS_TZPC_PCLK,
> + CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA,
> + CLK_CON_GAT_GOUT_IS_CLK_GDC,
> + CLK_CON_GAT_GOUT_IS_CLK_IPP,
> + CLK_CON_GAT_GOUT_IS_CLK_ITP,
> + CLK_CON_GAT_GOUT_IS_CLK_MCSC,
> + CLK_CON_GAT_GOUT_IS_CLK_VRA,
> + CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK,
> + CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK,
> + CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK,
> + CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK,
> + CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1,
> + CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1,
> + CLK_CON_GAT_GOUT_IS_SYSREG_PCLK,
> +};
> +
> +/* List of parent clocks for Muxes in CMU_IS */
> +PNAME(mout_is_bus_user_p) = { "oscclk", "dout_is_bus" };
> +PNAME(mout_is_itp_user_p) = { "oscclk", "dout_is_itp" };
> +PNAME(mout_is_vra_user_p) = { "oscclk", "dout_is_vra" };
> +PNAME(mout_is_gdc_user_p) = { "oscclk", "dout_is_gdc" };
> +
> +static const struct samsung_mux_clock is_mux_clks[] __initconst = {
> + MUX(CLK_MOUT_IS_BUS_USER, "mout_is_bus_user", mout_is_bus_user_p,
> + PLL_CON0_MUX_CLKCMU_IS_BUS_USER, 4, 1),
> + MUX(CLK_MOUT_IS_ITP_USER, "mout_is_itp_user", mout_is_itp_user_p,
> + PLL_CON0_MUX_CLKCMU_IS_ITP_USER, 4, 1),
> + MUX(CLK_MOUT_IS_VRA_USER, "mout_is_vra_user", mout_is_vra_user_p,
> + PLL_CON0_MUX_CLKCMU_IS_VRA_USER, 4, 1),
> + MUX(CLK_MOUT_IS_GDC_USER, "mout_is_gdc_user", mout_is_gdc_user_p,
> + PLL_CON0_MUX_CLKCMU_IS_GDC_USER, 4, 1),
> +};
> +
> +static const struct samsung_div_clock is_div_clks[] __initconst = {
> + DIV(CLK_DOUT_IS_BUSP, "dout_is_busp", "mout_is_bus_user",
> + CLK_CON_DIV_DIV_CLK_IS_BUSP, 0, 2),
> +};
> +
> +static const struct samsung_gate_clock is_gate_clks[] __initconst = {
> + /* TODO: Should be enabled in IS driver */
> + GATE(CLK_GOUT_IS_CMU_IS_PCLK, "gout_is_cmu_is_pclk", "dout_is_busp",
> + CLK_CON_GAT_CLK_IS_CMU_IS_PCLK, 21, CLK_IGNORE_UNUSED, 0),
> + GATE(CLK_GOUT_IS_CSIS0_ACLK, "gout_is_csis0_aclk", "mout_is_bus_user",
> + CLK_CON_GAT_GOUT_IS_CSIS0_ACLK, 21, 0, 0),
> + GATE(CLK_GOUT_IS_CSIS1_ACLK, "gout_is_csis1_aclk", "mout_is_bus_user",
> + CLK_CON_GAT_GOUT_IS_CSIS1_ACLK, 21, 0, 0),
> + GATE(CLK_GOUT_IS_CSIS2_ACLK, "gout_is_csis2_aclk", "mout_is_bus_user",
> + CLK_CON_GAT_GOUT_IS_CSIS2_ACLK, 21, 0, 0),
> + GATE(CLK_GOUT_IS_TZPC_PCLK, "gout_is_tzpc_pclk", "dout_is_busp",
> + CLK_CON_GAT_GOUT_IS_TZPC_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_IS_CSIS_DMA_CLK, "gout_is_csis_dma_clk",
> + "mout_is_bus_user",
> + CLK_CON_GAT_GOUT_IS_CLK_CSIS_DMA, 21, 0, 0),
> + GATE(CLK_GOUT_IS_GDC_CLK, "gout_is_gdc_clk", "mout_is_gdc_user",
> + CLK_CON_GAT_GOUT_IS_CLK_GDC, 21, 0, 0),
> + GATE(CLK_GOUT_IS_IPP_CLK, "gout_is_ipp_clk", "mout_is_bus_user",
> + CLK_CON_GAT_GOUT_IS_CLK_IPP, 21, 0, 0),
> + GATE(CLK_GOUT_IS_ITP_CLK, "gout_is_itp_clk", "mout_is_itp_user",
> + CLK_CON_GAT_GOUT_IS_CLK_ITP, 21, 0, 0),
> + GATE(CLK_GOUT_IS_MCSC_CLK, "gout_is_mcsc_clk", "mout_is_itp_user",
> + CLK_CON_GAT_GOUT_IS_CLK_MCSC, 21, 0, 0),
> + GATE(CLK_GOUT_IS_VRA_CLK, "gout_is_vra_clk", "mout_is_vra_user",
> + CLK_CON_GAT_GOUT_IS_CLK_VRA, 21, 0, 0),
> + GATE(CLK_GOUT_IS_PPMU_IS0_ACLK, "gout_is_ppmu_is0_aclk",
> + "mout_is_bus_user",
> + CLK_CON_GAT_GOUT_IS_PPMU_IS0_ACLK, 21, 0, 0),
> + GATE(CLK_GOUT_IS_PPMU_IS0_PCLK, "gout_is_ppmu_is0_pclk", "dout_is_busp",
> + CLK_CON_GAT_GOUT_IS_PPMU_IS0_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_IS_PPMU_IS1_ACLK, "gout_is_ppmu_is1_aclk",
> + "mout_is_itp_user",
> + CLK_CON_GAT_GOUT_IS_PPMU_IS1_ACLK, 21, 0, 0),
> + GATE(CLK_GOUT_IS_PPMU_IS1_PCLK, "gout_is_ppmu_is1_pclk", "dout_is_busp",
> + CLK_CON_GAT_GOUT_IS_PPMU_IS1_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_IS_SYSMMU_IS0_CLK, "gout_is_sysmmu_is0_clk",
> + "mout_is_bus_user",
> + CLK_CON_GAT_GOUT_IS_SYSMMU_IS0_CLK_S1, 21, 0, 0),
> + GATE(CLK_GOUT_IS_SYSMMU_IS1_CLK, "gout_is_sysmmu_is1_clk",
> + "mout_is_itp_user",
> + CLK_CON_GAT_GOUT_IS_SYSMMU_IS1_CLK_S1, 21, 0, 0),
> + GATE(CLK_GOUT_IS_SYSREG_PCLK, "gout_is_sysreg_pclk", "dout_is_busp",
> + CLK_CON_GAT_GOUT_IS_SYSREG_PCLK, 21, 0, 0),
> +};
> +
> +static const struct samsung_cmu_info is_cmu_info __initconst = {
> + .mux_clks = is_mux_clks,
> + .nr_mux_clks = ARRAY_SIZE(is_mux_clks),
> + .div_clks = is_div_clks,
> + .nr_div_clks = ARRAY_SIZE(is_div_clks),
> + .gate_clks = is_gate_clks,
> + .nr_gate_clks = ARRAY_SIZE(is_gate_clks),
> + .nr_clk_ids = IS_NR_CLK,
> + .clk_regs = is_clk_regs,
> + .nr_clk_regs = ARRAY_SIZE(is_clk_regs),
> + .clk_name = "dout_is_bus",
> +};
> +
> /* ---- CMU_PERI ------------------------------------------------------------ */
>
> /* Register Offset definitions for CMU_PERI (0x10030000) */
> @@ -1334,6 +1530,9 @@ static const struct of_device_id exynos850_cmu_of_match[] = {
> }, {
> .compatible = "samsung,exynos850-cmu-hsi",
> .data = &hsi_cmu_info,
> + }, {
> + .compatible = "samsung,exynos850-cmu-is",
> + .data = &is_cmu_info,
> }, {
> .compatible = "samsung,exynos850-cmu-core",
> .data = &core_cmu_info,
Acked-by: Chanwoo Choi <[email protected]>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
On 22. 8. 9. 20:33, Sam Protsenko wrote:
> CMU_MFCMSCL clock domain provides clocks for MFC (Multi-Format Codec),
> JPEG Codec and Scaler IP-cores. According to Exynos850 TRM, CMU_MFCMSCL
> generates MFC, M2M, MCSC and JPEG clocks for BLK_MFCMSCL.
>
> This patch adds next clocks:
> - bus clocks in CMU_TOP for CMU_MFCMSCL
> - all internal CMU_MFCMSCL clocks
> - leaf clocks for MFCMSCL, TZPC (TrustZone Protection Controller),
> JPEG codec, M2M (Memory-to-Memory), MCSC (Multi-Channel Scaler),
> MFC (Multi-Format Codec), PPMU (Platform Performance Monitoring
> Unit), SysMMU and SysReg
>
> MFCMSCL related gate clocks in CMU_TOP were marked as CLK_IS_CRITICAL,
> because:
> 1. All of those have to be enabled in order to read
> /sys/kernel/debug/clk/clk_summary file
> 2. When some user driver (e.g. exynos-sysmmu) disables some derived
> leaf clock, it can lead to CMU_TOP clocks disable, which then makes
> the system hang. To prevent that, the CLK_IS_CRITICAL flag is used,
> as CLK_IGNORE_UNUSED is not enough.
>
> Signed-off-by: Sam Protsenko <[email protected]>
> ---
> Changes in v2:
> - (none)
>
> drivers/clk/samsung/clk-exynos850.c | 176 ++++++++++++++++++++++++++++
> 1 file changed, 176 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c
> index 18a36d58101e..541761e96aeb 100644
> --- a/drivers/clk/samsung/clk-exynos850.c
> +++ b/drivers/clk/samsung/clk-exynos850.c
> @@ -43,6 +43,10 @@
> #define CLK_CON_MUX_MUX_CLKCMU_IS_GDC 0x104c
> #define CLK_CON_MUX_MUX_CLKCMU_IS_ITP 0x1050
> #define CLK_CON_MUX_MUX_CLKCMU_IS_VRA 0x1054
> +#define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG 0x1058
> +#define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M 0x105c
> +#define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC 0x1060
> +#define CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC 0x1064
> #define CLK_CON_MUX_MUX_CLKCMU_PERI_BUS 0x1070
> #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
> #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
> @@ -60,6 +64,10 @@
> #define CLK_CON_DIV_CLKCMU_IS_GDC 0x1858
> #define CLK_CON_DIV_CLKCMU_IS_ITP 0x185c
> #define CLK_CON_DIV_CLKCMU_IS_VRA 0x1860
> +#define CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG 0x1864
> +#define CLK_CON_DIV_CLKCMU_MFCMSCL_M2M 0x1868
> +#define CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC 0x186c
> +#define CLK_CON_DIV_CLKCMU_MFCMSCL_MFC 0x1870
> #define CLK_CON_DIV_CLKCMU_PERI_BUS 0x187c
> #define CLK_CON_DIV_CLKCMU_PERI_IP 0x1880
> #define CLK_CON_DIV_CLKCMU_PERI_UART 0x1884
> @@ -83,6 +91,10 @@
> #define CLK_CON_GAT_GATE_CLKCMU_IS_GDC 0x2054
> #define CLK_CON_GAT_GATE_CLKCMU_IS_ITP 0x2058
> #define CLK_CON_GAT_GATE_CLKCMU_IS_VRA 0x205c
> +#define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG 0x2060
> +#define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M 0x2064
> +#define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC 0x2068
> +#define CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC 0x206c
> #define CLK_CON_GAT_GATE_CLKCMU_PERI_BUS 0x2080
> #define CLK_CON_GAT_GATE_CLKCMU_PERI_IP 0x2084
> #define CLK_CON_GAT_GATE_CLKCMU_PERI_UART 0x2088
> @@ -111,6 +123,10 @@ static const unsigned long top_clk_regs[] __initconst = {
> CLK_CON_MUX_MUX_CLKCMU_IS_GDC,
> CLK_CON_MUX_MUX_CLKCMU_IS_ITP,
> CLK_CON_MUX_MUX_CLKCMU_IS_VRA,
> + CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG,
> + CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M,
> + CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC,
> + CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC,
> CLK_CON_MUX_MUX_CLKCMU_PERI_BUS,
> CLK_CON_MUX_MUX_CLKCMU_PERI_IP,
> CLK_CON_MUX_MUX_CLKCMU_PERI_UART,
> @@ -128,6 +144,10 @@ static const unsigned long top_clk_regs[] __initconst = {
> CLK_CON_DIV_CLKCMU_IS_GDC,
> CLK_CON_DIV_CLKCMU_IS_ITP,
> CLK_CON_DIV_CLKCMU_IS_VRA,
> + CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG,
> + CLK_CON_DIV_CLKCMU_MFCMSCL_M2M,
> + CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC,
> + CLK_CON_DIV_CLKCMU_MFCMSCL_MFC,
> CLK_CON_DIV_CLKCMU_PERI_BUS,
> CLK_CON_DIV_CLKCMU_PERI_IP,
> CLK_CON_DIV_CLKCMU_PERI_UART,
> @@ -151,6 +171,10 @@ static const unsigned long top_clk_regs[] __initconst = {
> CLK_CON_GAT_GATE_CLKCMU_IS_GDC,
> CLK_CON_GAT_GATE_CLKCMU_IS_ITP,
> CLK_CON_GAT_GATE_CLKCMU_IS_VRA,
> + CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG,
> + CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M,
> + CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC,
> + CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC,
> CLK_CON_GAT_GATE_CLKCMU_PERI_BUS,
> CLK_CON_GAT_GATE_CLKCMU_PERI_IP,
> CLK_CON_GAT_GATE_CLKCMU_PERI_UART,
> @@ -209,6 +233,15 @@ PNAME(mout_is_vra_p) = { "dout_shared0_div2", "dout_shared1_div2",
> "dout_shared0_div3", "dout_shared1_div3" };
> PNAME(mout_is_gdc_p) = { "dout_shared0_div2", "dout_shared1_div2",
> "dout_shared0_div3", "dout_shared1_div3" };
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_MFCMSCL */
> +PNAME(mout_mfcmscl_mfc_p) = { "dout_shared1_div2", "dout_shared0_div3",
> + "dout_shared1_div3", "dout_shared0_div4" };
> +PNAME(mout_mfcmscl_m2m_p) = { "dout_shared1_div2", "dout_shared0_div3",
> + "dout_shared1_div3", "dout_shared0_div4" };
> +PNAME(mout_mfcmscl_mcsc_p) = { "dout_shared1_div2", "dout_shared0_div3",
> + "dout_shared1_div3", "dout_shared0_div4" };
> +PNAME(mout_mfcmscl_jpeg_p) = { "dout_shared0_div3", "dout_shared1_div3",
> + "dout_shared0_div4", "dout_shared1_div4" };
> /* List of parent clocks for Muxes in CMU_TOP: for CMU_PERI */
> PNAME(mout_peri_bus_p) = { "dout_shared0_div4", "dout_shared1_div4" };
> PNAME(mout_peri_uart_p) = { "oscclk", "dout_shared0_div4",
> @@ -268,6 +301,16 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
> MUX(CLK_MOUT_IS_GDC, "mout_is_gdc", mout_is_gdc_p,
> CLK_CON_MUX_MUX_CLKCMU_IS_GDC, 0, 2),
>
> + /* MFCMSCL */
> + MUX(CLK_MOUT_MFCMSCL_MFC, "mout_mfcmscl_mfc", mout_mfcmscl_mfc_p,
> + CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MFC, 0, 2),
> + MUX(CLK_MOUT_MFCMSCL_M2M, "mout_mfcmscl_m2m", mout_mfcmscl_m2m_p,
> + CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_M2M, 0, 2),
> + MUX(CLK_MOUT_MFCMSCL_MCSC, "mout_mfcmscl_mcsc", mout_mfcmscl_mcsc_p,
> + CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_MCSC, 0, 2),
> + MUX(CLK_MOUT_MFCMSCL_JPEG, "mout_mfcmscl_jpeg", mout_mfcmscl_jpeg_p,
> + CLK_CON_MUX_MUX_CLKCMU_MFCMSCL_JPEG, 0, 2),
> +
> /* PERI */
> MUX(CLK_MOUT_PERI_BUS, "mout_peri_bus", mout_peri_bus_p,
> CLK_CON_MUX_MUX_CLKCMU_PERI_BUS, 0, 1),
> @@ -332,6 +375,16 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
> DIV(CLK_DOUT_IS_GDC, "dout_is_gdc", "gout_is_gdc",
> CLK_CON_DIV_CLKCMU_IS_GDC, 0, 4),
>
> + /* MFCMSCL */
> + DIV(CLK_DOUT_MFCMSCL_MFC, "dout_mfcmscl_mfc", "gout_mfcmscl_mfc",
> + CLK_CON_DIV_CLKCMU_MFCMSCL_MFC, 0, 4),
> + DIV(CLK_DOUT_MFCMSCL_M2M, "dout_mfcmscl_m2m", "gout_mfcmscl_m2m",
> + CLK_CON_DIV_CLKCMU_MFCMSCL_M2M, 0, 4),
> + DIV(CLK_DOUT_MFCMSCL_MCSC, "dout_mfcmscl_mcsc", "gout_mfcmscl_mcsc",
> + CLK_CON_DIV_CLKCMU_MFCMSCL_MCSC, 0, 4),
> + DIV(CLK_DOUT_MFCMSCL_JPEG, "dout_mfcmscl_jpeg", "gout_mfcmscl_jpeg",
> + CLK_CON_DIV_CLKCMU_MFCMSCL_JPEG, 0, 4),
> +
> /* PERI */
> DIV(CLK_DOUT_PERI_BUS, "dout_peri_bus", "gout_peri_bus",
> CLK_CON_DIV_CLKCMU_PERI_BUS, 0, 4),
> @@ -383,6 +436,17 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
> GATE(CLK_GOUT_IS_GDC, "gout_is_gdc", "mout_is_gdc",
> CLK_CON_GAT_GATE_CLKCMU_IS_GDC, 21, CLK_IS_CRITICAL, 0),
>
> + /* MFCMSCL */
> + /* TODO: These have to be always enabled to access CMU_MFCMSCL regs */
> + GATE(CLK_GOUT_MFCMSCL_MFC, "gout_mfcmscl_mfc", "mout_mfcmscl_mfc",
> + CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MFC, 21, CLK_IS_CRITICAL, 0),
> + GATE(CLK_GOUT_MFCMSCL_M2M, "gout_mfcmscl_m2m", "mout_mfcmscl_m2m",
> + CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_M2M, 21, CLK_IS_CRITICAL, 0),
> + GATE(CLK_GOUT_MFCMSCL_MCSC, "gout_mfcmscl_mcsc", "mout_mfcmscl_mcsc",
> + CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_MCSC, 21, CLK_IS_CRITICAL, 0),
> + GATE(CLK_GOUT_MFCMSCL_JPEG, "gout_mfcmscl_jpeg", "mout_mfcmscl_jpeg",
> + CLK_CON_GAT_GATE_CLKCMU_MFCMSCL_JPEG, 21, CLK_IS_CRITICAL, 0),
> +
> /* PERI */
> GATE(CLK_GOUT_PERI_BUS, "gout_peri_bus", "mout_peri_bus",
> CLK_CON_GAT_GATE_CLKCMU_PERI_BUS, 21, 0, 0),
> @@ -1148,6 +1212,115 @@ static const struct samsung_cmu_info is_cmu_info __initconst = {
> .clk_name = "dout_is_bus",
> };
>
> +/* ---- CMU_MFCMSCL --------------------------------------------------------- */
> +
> +#define PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER 0x0600
> +#define PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER 0x0610
> +#define PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER 0x0620
> +#define PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER 0x0630
> +#define CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP 0x1800
> +#define CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK 0x2000
> +#define CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK 0x2038
> +#define CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK 0x203c
> +#define CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK 0x2048
> +#define CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK 0x204c
> +#define CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK 0x2050
> +#define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK 0x2054
> +#define CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK 0x2058
> +#define CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1 0x2074
> +#define CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK 0x2078
> +
> +static const unsigned long mfcmscl_clk_regs[] __initconst = {
> + PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER,
> + PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER,
> + PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER,
> + PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER,
> + CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP,
> + CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK,
> + CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK,
> + CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK,
> + CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK,
> + CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK,
> + CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK,
> + CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK,
> + CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK,
> + CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1,
> + CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK,
> +};
> +
> +/* List of parent clocks for Muxes in CMU_MFCMSCL */
> +PNAME(mout_mfcmscl_mfc_user_p) = { "oscclk", "dout_mfcmscl_mfc" };
> +PNAME(mout_mfcmscl_m2m_user_p) = { "oscclk", "dout_mfcmscl_m2m" };
> +PNAME(mout_mfcmscl_mcsc_user_p) = { "oscclk", "dout_mfcmscl_mcsc" };
> +PNAME(mout_mfcmscl_jpeg_user_p) = { "oscclk", "dout_mfcmscl_jpeg" };
> +
> +static const struct samsung_mux_clock mfcmscl_mux_clks[] __initconst = {
> + MUX(CLK_MOUT_MFCMSCL_MFC_USER, "mout_mfcmscl_mfc_user",
> + mout_mfcmscl_mfc_user_p,
> + PLL_CON0_MUX_CLKCMU_MFCMSCL_MFC_USER, 4, 1),
> + MUX(CLK_MOUT_MFCMSCL_M2M_USER, "mout_mfcmscl_m2m_user",
> + mout_mfcmscl_m2m_user_p,
> + PLL_CON0_MUX_CLKCMU_MFCMSCL_M2M_USER, 4, 1),
> + MUX(CLK_MOUT_MFCMSCL_MCSC_USER, "mout_mfcmscl_mcsc_user",
> + mout_mfcmscl_mcsc_user_p,
> + PLL_CON0_MUX_CLKCMU_MFCMSCL_MCSC_USER, 4, 1),
> + MUX(CLK_MOUT_MFCMSCL_JPEG_USER, "mout_mfcmscl_jpeg_user",
> + mout_mfcmscl_jpeg_user_p,
> + PLL_CON0_MUX_CLKCMU_MFCMSCL_JPEG_USER, 4, 1),
> +};
> +
> +static const struct samsung_div_clock mfcmscl_div_clks[] __initconst = {
> + DIV(CLK_DOUT_MFCMSCL_BUSP, "dout_mfcmscl_busp", "mout_mfcmscl_mfc_user",
> + CLK_CON_DIV_DIV_CLK_MFCMSCL_BUSP, 0, 3),
> +};
> +
> +static const struct samsung_gate_clock mfcmscl_gate_clks[] __initconst = {
> + /* TODO: Should be enabled in MFC driver */
> + GATE(CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK, "gout_mfcmscl_cmu_mfcmscl_pclk",
> + "dout_mfcmscl_busp", CLK_CON_GAT_CLK_MFCMSCL_CMU_MFCMSCL_PCLK,
> + 21, CLK_IGNORE_UNUSED, 0),
> + GATE(CLK_GOUT_MFCMSCL_TZPC_PCLK, "gout_mfcmscl_tzpc_pclk",
> + "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_TZPC_PCLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_MFCMSCL_JPEG_ACLK, "gout_mfcmscl_jpeg_aclk",
> + "mout_mfcmscl_jpeg_user", CLK_CON_GAT_GOUT_MFCMSCL_JPEG_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_MFCMSCL_M2M_ACLK, "gout_mfcmscl_m2m_aclk",
> + "mout_mfcmscl_m2m_user", CLK_CON_GAT_GOUT_MFCMSCL_M2M_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_MFCMSCL_MCSC_CLK, "gout_mfcmscl_mcsc_clk",
> + "mout_mfcmscl_mcsc_user", CLK_CON_GAT_GOUT_MFCMSCL_MCSC_I_CLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_MFCMSCL_MFC_ACLK, "gout_mfcmscl_mfc_aclk",
> + "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_MFC_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_MFCMSCL_PPMU_ACLK, "gout_mfcmscl_ppmu_aclk",
> + "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_ACLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_MFCMSCL_PPMU_PCLK, "gout_mfcmscl_ppmu_pclk",
> + "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_PPMU_PCLK,
> + 21, 0, 0),
> + GATE(CLK_GOUT_MFCMSCL_SYSMMU_CLK, "gout_mfcmscl_sysmmu_clk",
> + "mout_mfcmscl_mfc_user", CLK_CON_GAT_GOUT_MFCMSCL_SYSMMU_CLK_S1,
> + 21, 0, 0),
> + GATE(CLK_GOUT_MFCMSCL_SYSREG_PCLK, "gout_mfcmscl_sysreg_pclk",
> + "dout_mfcmscl_busp", CLK_CON_GAT_GOUT_MFCMSCL_SYSREG_PCLK,
> + 21, 0, 0),
> +};
> +
> +static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = {
> + .mux_clks = mfcmscl_mux_clks,
> + .nr_mux_clks = ARRAY_SIZE(mfcmscl_mux_clks),
> + .div_clks = mfcmscl_div_clks,
> + .nr_div_clks = ARRAY_SIZE(mfcmscl_div_clks),
> + .gate_clks = mfcmscl_gate_clks,
> + .nr_gate_clks = ARRAY_SIZE(mfcmscl_gate_clks),
> + .nr_clk_ids = MFCMSCL_NR_CLK,
> + .clk_regs = mfcmscl_clk_regs,
> + .nr_clk_regs = ARRAY_SIZE(mfcmscl_clk_regs),
> + .clk_name = "dout_mfcmscl_mfc",
> +};
> +
> /* ---- CMU_PERI ------------------------------------------------------------ */
>
> /* Register Offset definitions for CMU_PERI (0x10030000) */
> @@ -1533,6 +1706,9 @@ static const struct of_device_id exynos850_cmu_of_match[] = {
> }, {
> .compatible = "samsung,exynos850-cmu-is",
> .data = &is_cmu_info,
> + }, {
> + .compatible = "samsung,exynos850-cmu-mfcmscl",
> + .data = &mfcmscl_cmu_info,
> }, {
> .compatible = "samsung,exynos850-cmu-core",
> .data = &core_cmu_info,
Acked-by: Chanwoo Choi <[email protected]>
Thanks for your work.
--
Best Regards,
Samsung Electronics
Chanwoo Choi
On 22. 8. 9. 20:33, Sam Protsenko wrote:
> CMU_AUD clock domain provides clocks for ABOX IP-core (audio subsystem).
> According to Exynos850 TRM, CMU_AUD generates Cortex-A32 clock, bus
> clock and audio clocks for BLK_AUD.
>
> This patch adds next clocks:
> - bus clocks in CMU_TOP needed for CMU_AUD
> - all internal CMU_AUD clocks
> - leaf clocks for Cortex-A32, Speedy FM, UAIF0..UAIF6 (Unified Audio
> Interface), CNT (counter), ABOX IP-core, ASB (Asynchronous Bridge),
> DAP (Debug Access Port), I2S Codec MCLK, D_TZPC (TrustZone
> Protection Controller), GPIO, PPMU (Platform Performance Monitoring
> Unit), SysMMU, SysReg and WDT
>
> ABOX clock was marked as CLK_IGNORE_UNUSED, as system hangs on boot
> otherwise. Once ABOX driver is implemented, maybe it can be handled
> there instead.
>
> Signed-off-by: Sam Protsenko <[email protected]>
> ---
> Changes in v2:
> - (none)
>
> drivers/clk/samsung/clk-exynos850.c | 302 ++++++++++++++++++++++++++++
> 1 file changed, 302 insertions(+)
>
> diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c
> index ef32546d3090..c91984f3f14f 100644
> --- a/drivers/clk/samsung/clk-exynos850.c
> +++ b/drivers/clk/samsung/clk-exynos850.c
> @@ -30,6 +30,7 @@
> #define PLL_CON0_PLL_SHARED1 0x0180
> #define PLL_CON3_PLL_SHARED1 0x018c
> #define CLK_CON_MUX_MUX_CLKCMU_APM_BUS 0x1000
> +#define CLK_CON_MUX_MUX_CLKCMU_AUD 0x1004
> #define CLK_CON_MUX_MUX_CLKCMU_CORE_BUS 0x1014
> #define CLK_CON_MUX_MUX_CLKCMU_CORE_CCI 0x1018
> #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c
> @@ -42,6 +43,7 @@
> #define CLK_CON_MUX_MUX_CLKCMU_PERI_IP 0x1074
> #define CLK_CON_MUX_MUX_CLKCMU_PERI_UART 0x1078
> #define CLK_CON_DIV_CLKCMU_APM_BUS 0x180c
> +#define CLK_CON_DIV_CLKCMU_AUD 0x1810
> #define CLK_CON_DIV_CLKCMU_CORE_BUS 0x1820
> #define CLK_CON_DIV_CLKCMU_CORE_CCI 0x1824
> #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828
> @@ -60,6 +62,7 @@
> #define CLK_CON_DIV_PLL_SHARED1_DIV3 0x189c
> #define CLK_CON_DIV_PLL_SHARED1_DIV4 0x18a0
> #define CLK_CON_GAT_GATE_CLKCMU_APM_BUS 0x2008
> +#define CLK_CON_GAT_GATE_CLKCMU_AUD 0x200c
> #define CLK_CON_GAT_GATE_CLKCMU_CORE_BUS 0x201c
> #define CLK_CON_GAT_GATE_CLKCMU_CORE_CCI 0x2020
> #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024
> @@ -83,6 +86,7 @@ static const unsigned long top_clk_regs[] __initconst = {
> PLL_CON0_PLL_SHARED1,
> PLL_CON3_PLL_SHARED1,
> CLK_CON_MUX_MUX_CLKCMU_APM_BUS,
> + CLK_CON_MUX_MUX_CLKCMU_AUD,
> CLK_CON_MUX_MUX_CLKCMU_CORE_BUS,
> CLK_CON_MUX_MUX_CLKCMU_CORE_CCI,
> CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD,
> @@ -95,6 +99,7 @@ static const unsigned long top_clk_regs[] __initconst = {
> CLK_CON_MUX_MUX_CLKCMU_PERI_IP,
> CLK_CON_MUX_MUX_CLKCMU_PERI_UART,
> CLK_CON_DIV_CLKCMU_APM_BUS,
> + CLK_CON_DIV_CLKCMU_AUD,
> CLK_CON_DIV_CLKCMU_CORE_BUS,
> CLK_CON_DIV_CLKCMU_CORE_CCI,
> CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD,
> @@ -113,6 +118,7 @@ static const unsigned long top_clk_regs[] __initconst = {
> CLK_CON_DIV_PLL_SHARED1_DIV3,
> CLK_CON_DIV_PLL_SHARED1_DIV4,
> CLK_CON_GAT_GATE_CLKCMU_APM_BUS,
> + CLK_CON_GAT_GATE_CLKCMU_AUD,
> CLK_CON_GAT_GATE_CLKCMU_CORE_BUS,
> CLK_CON_GAT_GATE_CLKCMU_CORE_CCI,
> CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD,
> @@ -148,6 +154,9 @@ PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
> PNAME(mout_mmc_pll_p) = { "oscclk", "fout_mmc_pll" };
> /* List of parent clocks for Muxes in CMU_TOP: for CMU_APM */
> PNAME(mout_clkcmu_apm_bus_p) = { "dout_shared0_div4", "pll_shared1_div4" };
> +/* List of parent clocks for Muxes in CMU_TOP: for CMU_AUD */
> +PNAME(mout_aud_p) = { "fout_shared1_pll", "dout_shared0_div2",
> + "dout_shared1_div2", "dout_shared0_div3" };
> /* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
> PNAME(mout_core_bus_p) = { "dout_shared1_div2", "dout_shared0_div3",
> "dout_shared1_div3", "dout_shared0_div4" };
> @@ -190,6 +199,10 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
> MUX(CLK_MOUT_CLKCMU_APM_BUS, "mout_clkcmu_apm_bus",
> mout_clkcmu_apm_bus_p, CLK_CON_MUX_MUX_CLKCMU_APM_BUS, 0, 1),
>
> + /* AUD */
> + MUX(CLK_MOUT_AUD, "mout_aud", mout_aud_p,
> + CLK_CON_MUX_MUX_CLKCMU_AUD, 0, 2),
> +
> /* CORE */
> MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
> CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
> @@ -240,6 +253,10 @@ static const struct samsung_div_clock top_div_clks[] __initconst = {
> DIV(CLK_DOUT_CLKCMU_APM_BUS, "dout_clkcmu_apm_bus",
> "gout_clkcmu_apm_bus", CLK_CON_DIV_CLKCMU_APM_BUS, 0, 3),
>
> + /* AUD */
> + DIV(CLK_DOUT_AUD, "dout_aud", "gout_aud",
> + CLK_CON_DIV_CLKCMU_AUD, 0, 4),
> +
> /* CORE */
> DIV(CLK_DOUT_CORE_BUS, "dout_core_bus", "gout_core_bus",
> CLK_CON_DIV_CLKCMU_CORE_BUS, 0, 4),
> @@ -286,6 +303,10 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = {
> GATE(CLK_GOUT_CLKCMU_APM_BUS, "gout_clkcmu_apm_bus",
> "mout_clkcmu_apm_bus", CLK_CON_GAT_GATE_CLKCMU_APM_BUS, 21, 0, 0),
>
> + /* AUD */
> + GATE(CLK_GOUT_AUD, "gout_aud", "mout_aud",
> + CLK_CON_GAT_GATE_CLKCMU_AUD, 21, 0, 0),
> +
> /* DPU */
> GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu",
> CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0),
> @@ -462,6 +483,284 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = {
> .clk_name = "dout_clkcmu_apm_bus",
> };
>
> +/* ---- CMU_AUD ------------------------------------------------------------- */
> +
> +#define PLL_LOCKTIME_PLL_AUD 0x0000
> +#define PLL_CON0_PLL_AUD 0x0100
> +#define PLL_CON3_PLL_AUD 0x010c
> +#define PLL_CON0_MUX_CLKCMU_AUD_CPU_USER 0x0600
> +#define PLL_CON0_MUX_TICK_USB_USER 0x0610
> +#define CLK_CON_MUX_MUX_CLK_AUD_CPU 0x1000
> +#define CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH 0x1004
> +#define CLK_CON_MUX_MUX_CLK_AUD_FM 0x1008
> +#define CLK_CON_MUX_MUX_CLK_AUD_UAIF0 0x100c
> +#define CLK_CON_MUX_MUX_CLK_AUD_UAIF1 0x1010
> +#define CLK_CON_MUX_MUX_CLK_AUD_UAIF2 0x1014
> +#define CLK_CON_MUX_MUX_CLK_AUD_UAIF3 0x1018
> +#define CLK_CON_MUX_MUX_CLK_AUD_UAIF4 0x101c
> +#define CLK_CON_MUX_MUX_CLK_AUD_UAIF5 0x1020
> +#define CLK_CON_MUX_MUX_CLK_AUD_UAIF6 0x1024
> +#define CLK_CON_DIV_DIV_CLK_AUD_MCLK 0x1800
> +#define CLK_CON_DIV_DIV_CLK_AUD_AUDIF 0x1804
> +#define CLK_CON_DIV_DIV_CLK_AUD_BUSD 0x1808
> +#define CLK_CON_DIV_DIV_CLK_AUD_BUSP 0x180c
> +#define CLK_CON_DIV_DIV_CLK_AUD_CNT 0x1810
> +#define CLK_CON_DIV_DIV_CLK_AUD_CPU 0x1814
> +#define CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK 0x1818
> +#define CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG 0x181c
> +#define CLK_CON_DIV_DIV_CLK_AUD_FM 0x1820
> +#define CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY 0x1824
> +#define CLK_CON_DIV_DIV_CLK_AUD_UAIF0 0x1828
> +#define CLK_CON_DIV_DIV_CLK_AUD_UAIF1 0x182c
> +#define CLK_CON_DIV_DIV_CLK_AUD_UAIF2 0x1830
> +#define CLK_CON_DIV_DIV_CLK_AUD_UAIF3 0x1834
> +#define CLK_CON_DIV_DIV_CLK_AUD_UAIF4 0x1838
> +#define CLK_CON_DIV_DIV_CLK_AUD_UAIF5 0x183c
> +#define CLK_CON_DIV_DIV_CLK_AUD_UAIF6 0x1840
> +#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT 0x2000
> +#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0 0x2004
> +#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1 0x2008
> +#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2 0x200c
> +#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3 0x2010
> +#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014
> +#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018
> +#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c
> +#define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048
> +#define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c
> +#define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050
> +#define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32 0x2054
> +#define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP 0x2058
> +#define CLK_CON_GAT_GOUT_AUD_CODEC_MCLK 0x206c
> +#define CLK_CON_GAT_GOUT_AUD_TZPC_PCLK 0x2070
> +#define CLK_CON_GAT_GOUT_AUD_GPIO_PCLK 0x2074
> +#define CLK_CON_GAT_GOUT_AUD_PPMU_ACLK 0x2088
> +#define CLK_CON_GAT_GOUT_AUD_PPMU_PCLK 0x208c
> +#define CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1 0x20b4
> +#define CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK 0x20b8
> +#define CLK_CON_GAT_GOUT_AUD_WDT_PCLK 0x20bc
> +
> +static const unsigned long aud_clk_regs[] __initconst = {
> + PLL_LOCKTIME_PLL_AUD,
> + PLL_CON0_PLL_AUD,
> + PLL_CON3_PLL_AUD,
> + PLL_CON0_MUX_CLKCMU_AUD_CPU_USER,
> + PLL_CON0_MUX_TICK_USB_USER,
> + CLK_CON_MUX_MUX_CLK_AUD_CPU,
> + CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH,
> + CLK_CON_MUX_MUX_CLK_AUD_FM,
> + CLK_CON_MUX_MUX_CLK_AUD_UAIF0,
> + CLK_CON_MUX_MUX_CLK_AUD_UAIF1,
> + CLK_CON_MUX_MUX_CLK_AUD_UAIF2,
> + CLK_CON_MUX_MUX_CLK_AUD_UAIF3,
> + CLK_CON_MUX_MUX_CLK_AUD_UAIF4,
> + CLK_CON_MUX_MUX_CLK_AUD_UAIF5,
> + CLK_CON_MUX_MUX_CLK_AUD_UAIF6,
> + CLK_CON_DIV_DIV_CLK_AUD_MCLK,
> + CLK_CON_DIV_DIV_CLK_AUD_AUDIF,
> + CLK_CON_DIV_DIV_CLK_AUD_BUSD,
> + CLK_CON_DIV_DIV_CLK_AUD_BUSP,
> + CLK_CON_DIV_DIV_CLK_AUD_CNT,
> + CLK_CON_DIV_DIV_CLK_AUD_CPU,
> + CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK,
> + CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG,
> + CLK_CON_DIV_DIV_CLK_AUD_FM,
> + CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY,
> + CLK_CON_DIV_DIV_CLK_AUD_UAIF0,
> + CLK_CON_DIV_DIV_CLK_AUD_UAIF1,
> + CLK_CON_DIV_DIV_CLK_AUD_UAIF2,
> + CLK_CON_DIV_DIV_CLK_AUD_UAIF3,
> + CLK_CON_DIV_DIV_CLK_AUD_UAIF4,
> + CLK_CON_DIV_DIV_CLK_AUD_UAIF5,
> + CLK_CON_DIV_DIV_CLK_AUD_UAIF6,
> + CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT,
> + CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0,
> + CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1,
> + CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2,
> + CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3,
> + CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4,
> + CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5,
> + CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6,
> + CLK_CON_GAT_GOUT_AUD_ABOX_ACLK,
> + CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY,
> + CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB,
> + CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32,
> + CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP,
> + CLK_CON_GAT_GOUT_AUD_CODEC_MCLK,
> + CLK_CON_GAT_GOUT_AUD_TZPC_PCLK,
> + CLK_CON_GAT_GOUT_AUD_GPIO_PCLK,
> + CLK_CON_GAT_GOUT_AUD_PPMU_ACLK,
> + CLK_CON_GAT_GOUT_AUD_PPMU_PCLK,
> + CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1,
> + CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK,
> + CLK_CON_GAT_GOUT_AUD_WDT_PCLK,
> +};
> +
> +/* List of parent clocks for Muxes in CMU_AUD */
> +PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll" };
> +PNAME(mout_aud_cpu_user_p) = { "oscclk", "dout_aud" };
> +PNAME(mout_aud_cpu_p) = { "dout_aud_cpu", "mout_aud_cpu_user" };
> +PNAME(mout_aud_cpu_hch_p) = { "mout_aud_cpu", "oscclk" };
> +PNAME(mout_aud_uaif0_p) = { "dout_aud_uaif0", "ioclk_audiocdclk0" };
> +PNAME(mout_aud_uaif1_p) = { "dout_aud_uaif1", "ioclk_audiocdclk1" };
> +PNAME(mout_aud_uaif2_p) = { "dout_aud_uaif2", "ioclk_audiocdclk2" };
> +PNAME(mout_aud_uaif3_p) = { "dout_aud_uaif3", "ioclk_audiocdclk3" };
> +PNAME(mout_aud_uaif4_p) = { "dout_aud_uaif4", "ioclk_audiocdclk4" };
> +PNAME(mout_aud_uaif5_p) = { "dout_aud_uaif5", "ioclk_audiocdclk5" };
> +PNAME(mout_aud_uaif6_p) = { "dout_aud_uaif6", "ioclk_audiocdclk6" };
> +PNAME(mout_aud_tick_usb_user_p) = { "oscclk", "tick_usb" };
> +PNAME(mout_aud_fm_p) = { "oscclk", "dout_aud_fm_spdy" };
> +
> +/*
> + * Do not provide PLL table to PLL_AUD, as MANUAL_PLL_CTRL bit is not set
> + * for that PLL by default, so set_rate operation would fail.
> + */
> +static const struct samsung_pll_clock aud_pll_clks[] __initconst = {
> + PLL(pll_0831x, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
> + PLL_LOCKTIME_PLL_AUD, PLL_CON3_PLL_AUD, NULL),
> +};
> +
> +static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = {
> + FRATE(IOCLK_AUDIOCDCLK0, "ioclk_audiocdclk0", NULL, 0, 25000000),
> + FRATE(IOCLK_AUDIOCDCLK1, "ioclk_audiocdclk1", NULL, 0, 25000000),
> + FRATE(IOCLK_AUDIOCDCLK2, "ioclk_audiocdclk2", NULL, 0, 25000000),
> + FRATE(IOCLK_AUDIOCDCLK3, "ioclk_audiocdclk3", NULL, 0, 25000000),
> + FRATE(IOCLK_AUDIOCDCLK4, "ioclk_audiocdclk4", NULL, 0, 25000000),
> + FRATE(IOCLK_AUDIOCDCLK5, "ioclk_audiocdclk5", NULL, 0, 25000000),
> + FRATE(IOCLK_AUDIOCDCLK6, "ioclk_audiocdclk6", NULL, 0, 25000000),
> + FRATE(TICK_USB, "tick_usb", NULL, 0, 60000000),
> +};
> +
> +static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
> + MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p,
> + PLL_CON0_PLL_AUD, 4, 1),
> + MUX(CLK_MOUT_AUD_CPU_USER, "mout_aud_cpu_user", mout_aud_cpu_user_p,
> + PLL_CON0_MUX_CLKCMU_AUD_CPU_USER, 4, 1),
> + MUX(CLK_MOUT_AUD_TICK_USB_USER, "mout_aud_tick_usb_user",
> + mout_aud_tick_usb_user_p,
> + PLL_CON0_MUX_TICK_USB_USER, 4, 1),
> + MUX(CLK_MOUT_AUD_CPU, "mout_aud_cpu", mout_aud_cpu_p,
> + CLK_CON_MUX_MUX_CLK_AUD_CPU, 0, 1),
> + MUX(CLK_MOUT_AUD_CPU_HCH, "mout_aud_cpu_hch", mout_aud_cpu_hch_p,
> + CLK_CON_MUX_MUX_CLK_AUD_CPU_HCH, 0, 1),
> + MUX(CLK_MOUT_AUD_UAIF0, "mout_aud_uaif0", mout_aud_uaif0_p,
> + CLK_CON_MUX_MUX_CLK_AUD_UAIF0, 0, 1),
> + MUX(CLK_MOUT_AUD_UAIF1, "mout_aud_uaif1", mout_aud_uaif1_p,
> + CLK_CON_MUX_MUX_CLK_AUD_UAIF1, 0, 1),
> + MUX(CLK_MOUT_AUD_UAIF2, "mout_aud_uaif2", mout_aud_uaif2_p,
> + CLK_CON_MUX_MUX_CLK_AUD_UAIF2, 0, 1),
> + MUX(CLK_MOUT_AUD_UAIF3, "mout_aud_uaif3", mout_aud_uaif3_p,
> + CLK_CON_MUX_MUX_CLK_AUD_UAIF3, 0, 1),
> + MUX(CLK_MOUT_AUD_UAIF4, "mout_aud_uaif4", mout_aud_uaif4_p,
> + CLK_CON_MUX_MUX_CLK_AUD_UAIF4, 0, 1),
> + MUX(CLK_MOUT_AUD_UAIF5, "mout_aud_uaif5", mout_aud_uaif5_p,
> + CLK_CON_MUX_MUX_CLK_AUD_UAIF5, 0, 1),
> + MUX(CLK_MOUT_AUD_UAIF6, "mout_aud_uaif6", mout_aud_uaif6_p,
> + CLK_CON_MUX_MUX_CLK_AUD_UAIF6, 0, 1),
> + MUX(CLK_MOUT_AUD_FM, "mout_aud_fm", mout_aud_fm_p,
> + CLK_CON_MUX_MUX_CLK_AUD_FM, 0, 1),
> +};
> +
> +static const struct samsung_div_clock aud_div_clks[] __initconst = {
> + DIV(CLK_DOUT_AUD_CPU, "dout_aud_cpu", "mout_aud_pll",
> + CLK_CON_DIV_DIV_CLK_AUD_CPU, 0, 4),
> + DIV(CLK_DOUT_AUD_BUSD, "dout_aud_busd", "mout_aud_pll",
> + CLK_CON_DIV_DIV_CLK_AUD_BUSD, 0, 4),
> + DIV(CLK_DOUT_AUD_BUSP, "dout_aud_busp", "mout_aud_pll",
> + CLK_CON_DIV_DIV_CLK_AUD_BUSP, 0, 4),
> + DIV(CLK_DOUT_AUD_AUDIF, "dout_aud_audif", "mout_aud_pll",
> + CLK_CON_DIV_DIV_CLK_AUD_AUDIF, 0, 9),
> + DIV(CLK_DOUT_AUD_CPU_ACLK, "dout_aud_cpu_aclk", "mout_aud_cpu_hch",
> + CLK_CON_DIV_DIV_CLK_AUD_CPU_ACLK, 0, 3),
> + DIV(CLK_DOUT_AUD_CPU_PCLKDBG, "dout_aud_cpu_pclkdbg",
> + "mout_aud_cpu_hch",
> + CLK_CON_DIV_DIV_CLK_AUD_CPU_PCLKDBG, 0, 3),
> + DIV(CLK_DOUT_AUD_MCLK, "dout_aud_mclk", "dout_aud_audif",
> + CLK_CON_DIV_DIV_CLK_AUD_MCLK, 0, 2),
> + DIV(CLK_DOUT_AUD_CNT, "dout_aud_cnt", "dout_aud_audif",
> + CLK_CON_DIV_DIV_CLK_AUD_CNT, 0, 10),
> + DIV(CLK_DOUT_AUD_UAIF0, "dout_aud_uaif0", "dout_aud_audif",
> + CLK_CON_DIV_DIV_CLK_AUD_UAIF0, 0, 10),
> + DIV(CLK_DOUT_AUD_UAIF1, "dout_aud_uaif1", "dout_aud_audif",
> + CLK_CON_DIV_DIV_CLK_AUD_UAIF1, 0, 10),
> + DIV(CLK_DOUT_AUD_UAIF2, "dout_aud_uaif2", "dout_aud_audif",
> + CLK_CON_DIV_DIV_CLK_AUD_UAIF2, 0, 10),
> + DIV(CLK_DOUT_AUD_UAIF3, "dout_aud_uaif3", "dout_aud_audif",
> + CLK_CON_DIV_DIV_CLK_AUD_UAIF3, 0, 10),
> + DIV(CLK_DOUT_AUD_UAIF4, "dout_aud_uaif4", "dout_aud_audif",
> + CLK_CON_DIV_DIV_CLK_AUD_UAIF4, 0, 10),
> + DIV(CLK_DOUT_AUD_UAIF5, "dout_aud_uaif5", "dout_aud_audif",
> + CLK_CON_DIV_DIV_CLK_AUD_UAIF5, 0, 10),
> + DIV(CLK_DOUT_AUD_UAIF6, "dout_aud_uaif6", "dout_aud_audif",
> + CLK_CON_DIV_DIV_CLK_AUD_UAIF6, 0, 10),
> + DIV(CLK_DOUT_AUD_FM_SPDY, "dout_aud_fm_spdy", "mout_aud_tick_usb_user",
> + CLK_CON_DIV_DIV_CLK_AUD_FM_SPDY, 0, 1),
> + DIV(CLK_DOUT_AUD_FM, "dout_aud_fm", "mout_aud_fm",
> + CLK_CON_DIV_DIV_CLK_AUD_FM, 0, 10),
> +};
> +
> +static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
> + GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", "mout_aud_cpu_hch",
> + CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0),
> + GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", "dout_aud_cpu_aclk",
> + CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, 21, 0, 0),
> + GATE(CLK_GOUT_AUD_DAP_CCLK, "gout_aud_dap_cclk", "dout_aud_cpu_pclkdbg",
> + CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_DAP, 21, 0, 0),
> + /* TODO: Should be enabled in ABOX driver (or made CLK_IS_CRITICAL) */
> + GATE(CLK_GOUT_AUD_ABOX_ACLK, "gout_aud_abox_aclk", "dout_aud_busd",
> + CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, 21, CLK_IGNORE_UNUSED, 0),
> + GATE(CLK_GOUT_AUD_GPIO_PCLK, "gout_aud_gpio_pclk", "dout_aud_busd",
> + CLK_CON_GAT_GOUT_AUD_GPIO_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_AUD_PPMU_ACLK, "gout_aud_ppmu_aclk", "dout_aud_busd",
> + CLK_CON_GAT_GOUT_AUD_PPMU_ACLK, 21, 0, 0),
> + GATE(CLK_GOUT_AUD_PPMU_PCLK, "gout_aud_ppmu_pclk", "dout_aud_busd",
> + CLK_CON_GAT_GOUT_AUD_PPMU_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_AUD_SYSMMU_CLK, "gout_aud_sysmmu_clk", "dout_aud_busd",
> + CLK_CON_GAT_GOUT_AUD_SYSMMU_CLK_S1, 21, 0, 0),
> + GATE(CLK_GOUT_AUD_SYSREG_PCLK, "gout_aud_sysreg_pclk", "dout_aud_busd",
> + CLK_CON_GAT_GOUT_AUD_SYSREG_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_AUD_WDT_PCLK, "gout_aud_wdt_pclk", "dout_aud_busd",
> + CLK_CON_GAT_GOUT_AUD_WDT_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_AUD_TZPC_PCLK, "gout_aud_tzpc_pclk", "dout_aud_busp",
> + CLK_CON_GAT_GOUT_AUD_TZPC_PCLK, 21, 0, 0),
> + GATE(CLK_GOUT_AUD_CODEC_MCLK, "gout_aud_codec_mclk", "dout_aud_mclk",
> + CLK_CON_GAT_GOUT_AUD_CODEC_MCLK, 21, 0, 0),
> + GATE(CLK_GOUT_AUD_CNT_BCLK, "gout_aud_cnt_bclk", "dout_aud_cnt",
> + CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_CNT, 21, 0, 0),
> + GATE(CLK_GOUT_AUD_UAIF0_BCLK, "gout_aud_uaif0_bclk", "mout_aud_uaif0",
> + CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF0, 21, 0, 0),
> + GATE(CLK_GOUT_AUD_UAIF1_BCLK, "gout_aud_uaif1_bclk", "mout_aud_uaif1",
> + CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF1, 21, 0, 0),
> + GATE(CLK_GOUT_AUD_UAIF2_BCLK, "gout_aud_uaif2_bclk", "mout_aud_uaif2",
> + CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF2, 21, 0, 0),
> + GATE(CLK_GOUT_AUD_UAIF3_BCLK, "gout_aud_uaif3_bclk", "mout_aud_uaif3",
> + CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF3, 21, 0, 0),
> + GATE(CLK_GOUT_AUD_UAIF4_BCLK, "gout_aud_uaif4_bclk", "mout_aud_uaif4",
> + CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, 21, 0, 0),
> + GATE(CLK_GOUT_AUD_UAIF5_BCLK, "gout_aud_uaif5_bclk", "mout_aud_uaif5",
> + CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, 21, 0, 0),
> + GATE(CLK_GOUT_AUD_UAIF6_BCLK, "gout_aud_uaif6_bclk", "mout_aud_uaif6",
> + CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, 21, 0, 0),
> + GATE(CLK_GOUT_AUD_SPDY_BCLK, "gout_aud_spdy_bclk", "dout_aud_fm",
> + CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, 21, 0, 0),
> +};
> +
> +static const struct samsung_cmu_info aud_cmu_info __initconst = {
> + .pll_clks = aud_pll_clks,
> + .nr_pll_clks = ARRAY_SIZE(aud_pll_clks),
> + .mux_clks = aud_mux_clks,
> + .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
> + .div_clks = aud_div_clks,
> + .nr_div_clks = ARRAY_SIZE(aud_div_clks),
> + .gate_clks = aud_gate_clks,
> + .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
> + .fixed_clks = aud_fixed_clks,
> + .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
> + .nr_clk_ids = AUD_NR_CLK,
> + .clk_regs = aud_clk_regs,
> + .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
> + .clk_name = "dout_aud",
> +};
> +
> /* ---- CMU_CMGP ------------------------------------------------------------ */
>
> /* Register Offset definitions for CMU_CMGP (0x11c00000) */
> @@ -1026,6 +1325,9 @@ static const struct of_device_id exynos850_cmu_of_match[] = {
> {
> .compatible = "samsung,exynos850-cmu-apm",
> .data = &apm_cmu_info,
> + }, {
> + .compatible = "samsung,exynos850-cmu-aud",
> + .data = &aud_cmu_info,
> }, {
> .compatible = "samsung,exynos850-cmu-cmgp",
> .data = &cmgp_cmu_info,
Acked-by: Chanwoo Choi <[email protected]>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
On 22. 8. 9. 20:33, Sam Protsenko wrote:
> CMU_IS generates CSIS, IPP, ITP, VRA and GDC clocks for BLK_IS. Add
> clock indices and bindings documentation for CMU_IS domain.
>
> Signed-off-by: Sam Protsenko <[email protected]>
> ---
> Changes in v2:
> - (none)
>
> .../clock/samsung,exynos850-clock.yaml | 25 ++++++++++++
> include/dt-bindings/clock/exynos850.h | 40 ++++++++++++++++++-
> 2 files changed, 64 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
> index 53511f056251..7f2e0b1c764c 100644
> --- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
> @@ -38,6 +38,7 @@ properties:
> - samsung,exynos850-cmu-core
> - samsung,exynos850-cmu-dpu
> - samsung,exynos850-cmu-hsi
> + - samsung,exynos850-cmu-is
> - samsung,exynos850-cmu-peri
>
> clocks:
> @@ -191,6 +192,30 @@ allOf:
> - const: dout_hsi_mmc_card
> - const: dout_hsi_usb20drd
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: samsung,exynos850-cmu-is
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (26 MHz)
> + - description: CMU_IS bus clock (from CMU_TOP)
> + - description: Image Texture Processing core clock (from CMU_TOP)
> + - description: Visual Recognition Accelerator clock (from CMU_TOP)
> + - description: Geometric Distortion Correction clock (from CMU_TOP)
> +
> + clock-names:
> + items:
> + - const: oscclk
> + - const: dout_is_bus
> + - const: dout_is_itp
> + - const: dout_is_vra
> + - const: dout_is_gdc
> +
> - if:
> properties:
> compatible:
> diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
> index 3dc55d4e5b9e..f8bf26f118c1 100644
> --- a/include/dt-bindings/clock/exynos850.h
> +++ b/include/dt-bindings/clock/exynos850.h
> @@ -61,7 +61,19 @@
> #define CLK_MOUT_AUD 49
> #define CLK_GOUT_AUD 50
> #define CLK_DOUT_AUD 51
> -#define TOP_NR_CLK 52
> +#define CLK_MOUT_IS_BUS 52
> +#define CLK_MOUT_IS_ITP 53
> +#define CLK_MOUT_IS_VRA 54
> +#define CLK_MOUT_IS_GDC 55
> +#define CLK_GOUT_IS_BUS 56
> +#define CLK_GOUT_IS_ITP 57
> +#define CLK_GOUT_IS_VRA 58
> +#define CLK_GOUT_IS_GDC 59
> +#define CLK_DOUT_IS_BUS 60
> +#define CLK_DOUT_IS_ITP 61
> +#define CLK_DOUT_IS_VRA 62
> +#define CLK_DOUT_IS_GDC 63
> +#define TOP_NR_CLK 64
>
> /* CMU_APM */
> #define CLK_RCO_I3C_PMIC 1
> @@ -187,6 +199,32 @@
> #define CLK_GOUT_SYSREG_HSI_PCLK 13
> #define HSI_NR_CLK 14
>
> +/* CMU_IS */
> +#define CLK_MOUT_IS_BUS_USER 1
> +#define CLK_MOUT_IS_ITP_USER 2
> +#define CLK_MOUT_IS_VRA_USER 3
> +#define CLK_MOUT_IS_GDC_USER 4
> +#define CLK_DOUT_IS_BUSP 5
> +#define CLK_GOUT_IS_CMU_IS_PCLK 6
> +#define CLK_GOUT_IS_CSIS0_ACLK 7
> +#define CLK_GOUT_IS_CSIS1_ACLK 8
> +#define CLK_GOUT_IS_CSIS2_ACLK 9
> +#define CLK_GOUT_IS_TZPC_PCLK 10
> +#define CLK_GOUT_IS_CSIS_DMA_CLK 11
> +#define CLK_GOUT_IS_GDC_CLK 12
> +#define CLK_GOUT_IS_IPP_CLK 13
> +#define CLK_GOUT_IS_ITP_CLK 14
> +#define CLK_GOUT_IS_MCSC_CLK 15
> +#define CLK_GOUT_IS_VRA_CLK 16
> +#define CLK_GOUT_IS_PPMU_IS0_ACLK 17
> +#define CLK_GOUT_IS_PPMU_IS0_PCLK 18
> +#define CLK_GOUT_IS_PPMU_IS1_ACLK 19
> +#define CLK_GOUT_IS_PPMU_IS1_PCLK 20
> +#define CLK_GOUT_IS_SYSMMU_IS0_CLK 21
> +#define CLK_GOUT_IS_SYSMMU_IS1_CLK 22
> +#define CLK_GOUT_IS_SYSREG_PCLK 23
> +#define IS_NR_CLK 24
> +
> /* CMU_PERI */
> #define CLK_MOUT_PERI_BUS_USER 1
> #define CLK_MOUT_PERI_UART_USER 2
Reviewed-by: Chanwoo Choi <[email protected]>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
On 22. 8. 9. 20:33, Sam Protsenko wrote:
> CMU_AUD generates Cortex-A32 clock, bus clock and audio clocks for
> BLK_AUD. Add clock indices and binding documentation for CMU_AUD.
>
> Signed-off-by: Sam Protsenko <[email protected]>
> ---
> Changes in v2:
> - (none)
>
> .../clock/samsung,exynos850-clock.yaml | 19 ++++++
> include/dt-bindings/clock/exynos850.h | 68 ++++++++++++++++++-
> 2 files changed, 86 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
> index aa11815ad3a3..53511f056251 100644
> --- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
> @@ -33,6 +33,7 @@ properties:
> enum:
> - samsung,exynos850-cmu-top
> - samsung,exynos850-cmu-apm
> + - samsung,exynos850-cmu-aud
> - samsung,exynos850-cmu-cmgp
> - samsung,exynos850-cmu-core
> - samsung,exynos850-cmu-dpu
> @@ -88,6 +89,24 @@ allOf:
> - const: oscclk
> - const: dout_clkcmu_apm_bus
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: samsung,exynos850-cmu-aud
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (26 MHz)
> + - description: AUD clock (from CMU_TOP)
> +
> + clock-names:
> + items:
> + - const: oscclk
> + - const: dout_aud
> +
> - if:
> properties:
> compatible:
> diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
> index 0b6a3c6a7c90..3dc55d4e5b9e 100644
> --- a/include/dt-bindings/clock/exynos850.h
> +++ b/include/dt-bindings/clock/exynos850.h
> @@ -58,7 +58,10 @@
> #define CLK_MOUT_CLKCMU_APM_BUS 46
> #define CLK_DOUT_CLKCMU_APM_BUS 47
> #define CLK_GOUT_CLKCMU_APM_BUS 48
> -#define TOP_NR_CLK 49
> +#define CLK_MOUT_AUD 49
> +#define CLK_GOUT_AUD 50
> +#define CLK_DOUT_AUD 51
> +#define TOP_NR_CLK 52
>
> /* CMU_APM */
> #define CLK_RCO_I3C_PMIC 1
> @@ -87,6 +90,69 @@
> #define CLK_GOUT_SYSREG_APM_PCLK 24
> #define APM_NR_CLK 25
>
> +/* CMU_AUD */
> +#define CLK_DOUT_AUD_AUDIF 1
> +#define CLK_DOUT_AUD_BUSD 2
> +#define CLK_DOUT_AUD_BUSP 3
> +#define CLK_DOUT_AUD_CNT 4
> +#define CLK_DOUT_AUD_CPU 5
> +#define CLK_DOUT_AUD_CPU_ACLK 6
> +#define CLK_DOUT_AUD_CPU_PCLKDBG 7
> +#define CLK_DOUT_AUD_FM 8
> +#define CLK_DOUT_AUD_FM_SPDY 9
> +#define CLK_DOUT_AUD_MCLK 10
> +#define CLK_DOUT_AUD_UAIF0 11
> +#define CLK_DOUT_AUD_UAIF1 12
> +#define CLK_DOUT_AUD_UAIF2 13
> +#define CLK_DOUT_AUD_UAIF3 14
> +#define CLK_DOUT_AUD_UAIF4 15
> +#define CLK_DOUT_AUD_UAIF5 16
> +#define CLK_DOUT_AUD_UAIF6 17
> +#define CLK_FOUT_AUD_PLL 18
> +#define CLK_GOUT_AUD_ABOX_ACLK 19
> +#define CLK_GOUT_AUD_ASB_CCLK 20
> +#define CLK_GOUT_AUD_CA32_CCLK 21
> +#define CLK_GOUT_AUD_CNT_BCLK 22
> +#define CLK_GOUT_AUD_CODEC_MCLK 23
> +#define CLK_GOUT_AUD_DAP_CCLK 24
> +#define CLK_GOUT_AUD_GPIO_PCLK 25
> +#define CLK_GOUT_AUD_PPMU_ACLK 26
> +#define CLK_GOUT_AUD_PPMU_PCLK 27
> +#define CLK_GOUT_AUD_SPDY_BCLK 28
> +#define CLK_GOUT_AUD_SYSMMU_CLK 29
> +#define CLK_GOUT_AUD_SYSREG_PCLK 30
> +#define CLK_GOUT_AUD_TZPC_PCLK 31
> +#define CLK_GOUT_AUD_UAIF0_BCLK 32
> +#define CLK_GOUT_AUD_UAIF1_BCLK 33
> +#define CLK_GOUT_AUD_UAIF2_BCLK 34
> +#define CLK_GOUT_AUD_UAIF3_BCLK 35
> +#define CLK_GOUT_AUD_UAIF4_BCLK 36
> +#define CLK_GOUT_AUD_UAIF5_BCLK 37
> +#define CLK_GOUT_AUD_UAIF6_BCLK 38
> +#define CLK_GOUT_AUD_WDT_PCLK 39
> +#define CLK_MOUT_AUD_CPU 40
> +#define CLK_MOUT_AUD_CPU_HCH 41
> +#define CLK_MOUT_AUD_CPU_USER 42
> +#define CLK_MOUT_AUD_FM 43
> +#define CLK_MOUT_AUD_PLL 44
> +#define CLK_MOUT_AUD_TICK_USB_USER 45
> +#define CLK_MOUT_AUD_UAIF0 46
> +#define CLK_MOUT_AUD_UAIF1 47
> +#define CLK_MOUT_AUD_UAIF2 48
> +#define CLK_MOUT_AUD_UAIF3 49
> +#define CLK_MOUT_AUD_UAIF4 50
> +#define CLK_MOUT_AUD_UAIF5 51
> +#define CLK_MOUT_AUD_UAIF6 52
> +#define IOCLK_AUDIOCDCLK0 53
> +#define IOCLK_AUDIOCDCLK1 54
> +#define IOCLK_AUDIOCDCLK2 55
> +#define IOCLK_AUDIOCDCLK3 56
> +#define IOCLK_AUDIOCDCLK4 57
> +#define IOCLK_AUDIOCDCLK5 58
> +#define IOCLK_AUDIOCDCLK6 59
> +#define TICK_USB 60
> +#define AUD_NR_CLK 61
> +
> /* CMU_CMGP */
> #define CLK_RCO_CMGP 1
> #define CLK_MOUT_CMGP_ADC 2
Reviewed-by: Chanwoo Choi <[email protected]>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
On 22. 8. 9. 20:33, Sam Protsenko wrote:
> CMU_MFCMSCL generates MFC, M2M, MCSC and JPEG clocks for BLK_MFCMSCL.
> Add clock indices and binding documentation for CMU_MFCMSCL.
>
> Signed-off-by: Sam Protsenko <[email protected]>
> ---
> Changes in v2:
> - (none)
>
> .../clock/samsung,exynos850-clock.yaml | 25 +++++++++++++++
> include/dt-bindings/clock/exynos850.h | 32 ++++++++++++++++++-
> 2 files changed, 56 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
> index 7f2e0b1c764c..141cf173f87d 100644
> --- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
> +++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml
> @@ -39,6 +39,7 @@ properties:
> - samsung,exynos850-cmu-dpu
> - samsung,exynos850-cmu-hsi
> - samsung,exynos850-cmu-is
> + - samsung,exynos850-cmu-mfcmscl
> - samsung,exynos850-cmu-peri
>
> clocks:
> @@ -216,6 +217,30 @@ allOf:
> - const: dout_is_vra
> - const: dout_is_gdc
>
> + - if:
> + properties:
> + compatible:
> + contains:
> + const: samsung,exynos850-cmu-mfcmscl
> +
> + then:
> + properties:
> + clocks:
> + items:
> + - description: External reference clock (26 MHz)
> + - description: Multi-Format Codec clock (from CMU_TOP)
> + - description: Memory to Memory Scaler clock (from CMU_TOP)
> + - description: Multi-Channel Scaler clock (from CMU_TOP)
> + - description: JPEG codec clock (from CMU_TOP)
> +
> + clock-names:
> + items:
> + - const: oscclk
> + - const: dout_mfcmscl_mfc
> + - const: dout_mfcmscl_m2m
> + - const: dout_mfcmscl_mcsc
> + - const: dout_mfcmscl_jpeg
> +
> - if:
> properties:
> compatible:
> diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
> index f8bf26f118c1..88d5289883d3 100644
> --- a/include/dt-bindings/clock/exynos850.h
> +++ b/include/dt-bindings/clock/exynos850.h
> @@ -73,7 +73,19 @@
> #define CLK_DOUT_IS_ITP 61
> #define CLK_DOUT_IS_VRA 62
> #define CLK_DOUT_IS_GDC 63
> -#define TOP_NR_CLK 64
> +#define CLK_MOUT_MFCMSCL_MFC 64
> +#define CLK_MOUT_MFCMSCL_M2M 65
> +#define CLK_MOUT_MFCMSCL_MCSC 66
> +#define CLK_MOUT_MFCMSCL_JPEG 67
> +#define CLK_GOUT_MFCMSCL_MFC 68
> +#define CLK_GOUT_MFCMSCL_M2M 69
> +#define CLK_GOUT_MFCMSCL_MCSC 70
> +#define CLK_GOUT_MFCMSCL_JPEG 71
> +#define CLK_DOUT_MFCMSCL_MFC 72
> +#define CLK_DOUT_MFCMSCL_M2M 73
> +#define CLK_DOUT_MFCMSCL_MCSC 74
> +#define CLK_DOUT_MFCMSCL_JPEG 75
> +#define TOP_NR_CLK 76
>
> /* CMU_APM */
> #define CLK_RCO_I3C_PMIC 1
> @@ -225,6 +237,24 @@
> #define CLK_GOUT_IS_SYSREG_PCLK 23
> #define IS_NR_CLK 24
>
> +/* CMU_MFCMSCL */
> +#define CLK_MOUT_MFCMSCL_MFC_USER 1
> +#define CLK_MOUT_MFCMSCL_M2M_USER 2
> +#define CLK_MOUT_MFCMSCL_MCSC_USER 3
> +#define CLK_MOUT_MFCMSCL_JPEG_USER 4
> +#define CLK_DOUT_MFCMSCL_BUSP 5
> +#define CLK_GOUT_MFCMSCL_CMU_MFCMSCL_PCLK 6
> +#define CLK_GOUT_MFCMSCL_TZPC_PCLK 7
> +#define CLK_GOUT_MFCMSCL_JPEG_ACLK 8
> +#define CLK_GOUT_MFCMSCL_M2M_ACLK 9
> +#define CLK_GOUT_MFCMSCL_MCSC_CLK 10
> +#define CLK_GOUT_MFCMSCL_MFC_ACLK 11
> +#define CLK_GOUT_MFCMSCL_PPMU_ACLK 12
> +#define CLK_GOUT_MFCMSCL_PPMU_PCLK 13
> +#define CLK_GOUT_MFCMSCL_SYSMMU_CLK 14
> +#define CLK_GOUT_MFCMSCL_SYSREG_PCLK 15
> +#define MFCMSCL_NR_CLK 16
> +
> /* CMU_PERI */
> #define CLK_MOUT_PERI_BUS_USER 1
> #define CLK_MOUT_PERI_UART_USER 2
Reviewed-by: Chanwoo Choi <[email protected]>
--
Best Regards,
Samsung Electronics
Chanwoo Choi
On Tue, 9 Aug 2022 14:33:14 +0300, Sam Protsenko wrote:
> Now that the basic SysMMU v7 support is ready [1,2], all SysMMU nodes
> can be added to Exynos850 SoC device tree. This series includes next
> changes:
>
> 1. Add all missing clock domains needed for SysMMU clocks
> 2. Add corresponding CMU nodes in device tree
> 3. Add all SysMMU nodes in device tree
>
> [...]
Applied, thanks!
[1/9] dt-bindings: clock: Add bindings for Exynos850 CMU_AUD
https://git.kernel.org/krzk/linux/c/45bbf4d76a6730acf63805798d6fe7a126e49dbc
[2/9] dt-bindings: clock: Add bindings for Exynos850 CMU_IS
https://git.kernel.org/krzk/linux/c/f20f35f46f1a65e1c4b65d8fb62acdbdafd11e1e
[3/9] dt-bindings: clock: Add bindings for Exynos850 CMU_MFCMSCL
https://git.kernel.org/krzk/linux/c/8f3fc0ed70b97e7544ec1a57c60fe6b2f2f778c3
[4/9] clk: samsung: exynos850: Style fixes
https://git.kernel.org/krzk/linux/c/dbaa27cc7e62d87d46014ef314811eb00fad9bda
[5/9] clk: samsung: exynos850: Implement CMU_AUD domain
https://git.kernel.org/krzk/linux/c/b73fd95def4fd9cde548ed17be19f845349e1c0c
[6/9] clk: samsung: exynos850: Implement CMU_IS domain
https://git.kernel.org/krzk/linux/c/bf3a4c519ca5455d96de2b9a8b1467f536bc0679
[7/9] clk: samsung: exynos850: Implement CMU_MFCMSCL domain
https://git.kernel.org/krzk/linux/c/7f36d3b696aebb624fb50cd2e852bba289521604
[8/9] arm64: dts: exynos: Add CMU_AUD, CMU_IS and CMU_MFCMSCL for Exynos850
https://git.kernel.org/krzk/linux/c/2c8cf49c7dec4b5f7323588279aa9e8a4174ebf9
[9/9] arm64: dts: exynos: Add SysMMU nodes for Exynos850
https://git.kernel.org/krzk/linux/c/09a122384e34a4aa7ebae59c1eb11d69cd80658c
Best regards,
--
Krzysztof Kozlowski <[email protected]>