From: Frank Wunderlich <[email protected]>
Add a new binding file for Rockchip PCIe v3 phy driver.
Signed-off-by: Frank Wunderlich <[email protected]>
Reviewed-by: Krzysztof Kozlowski <[email protected]>
---
v4:
- add reviewed-by
- remove minitems for clock-names as i have static list to fix error
- fix reg error by using 32-bit adressing in binding example
- change lane-map to u32 data-lanes
- tried to move data-lanes to phy-provider
https://github.com/frank-w/dt-schema/blob/main/dtschema/schemas/phy/phy-provider.yaml#L17
cloned and installed via pip install -e <local path>
verified with pip show, but phy-privider seems not to be applied
v3:
- drop quotes
- drop rk3588
- make clockcount fixed to 3
- full path for binding header file
- drop phy-mode and its header and add lane-map
v2:
dt-bindings: rename yaml for PCIe v3
rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml
changes in pcie3 phy yaml
- change clock names to ordered const list
- extend pcie30-phymode description
- add phy-cells to required properties
- drop unevaluatedProperties
- example with 1 clock each line
- use default property instead of text describing it
- update license
---
.../bindings/phy/rockchip,pcie3-phy.yaml | 80 +++++++++++++++++++
1 file changed, 80 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
new file mode 100644
index 000000000000..9f2d8d2cc7a5
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Rockchip PCIe v3 phy
+
+maintainers:
+ - Heiko Stuebner <[email protected]>
+
+properties:
+ compatible:
+ enum:
+ - rockchip,rk3568-pcie3-phy
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 3
+ maxItems: 3
+
+ clock-names:
+ items:
+ - const: refclk_m
+ - const: refclk_n
+ - const: pclk
+
+ data-lanes:
+ description: which lanes (by position) should be mapped to which
+ controller (value). 0 means lane disabled, higher value means used.
+ (controller-number +1 )
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ minItems: 2
+ maxItems: 16
+ items:
+ minimum: 0
+ maximum: 16
+
+ "#phy-cells":
+ const: 0
+
+ resets:
+ maxItems: 1
+
+ reset-names:
+ const: phy
+
+ rockchip,phy-grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the syscon managing the phy "general register files"
+
+ rockchip,pipe-grf:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the syscon managing the pipe "general register files"
+
+required:
+ - compatible
+ - reg
+ - rockchip,phy-grf
+ - "#phy-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3568-cru.h>
+ pcie30phy: phy@fe8c0000 {
+ compatible = "rockchip,rk3568-pcie3-phy";
+ reg = <0xfe8c0000 0x20000>;
+ #phy-cells = <0>;
+ clocks = <&pmucru CLK_PCIE30PHY_REF_M>,
+ <&pmucru CLK_PCIE30PHY_REF_N>,
+ <&cru PCLK_PCIE30PHY>;
+ clock-names = "refclk_m", "refclk_n", "pclk";
+ resets = <&cru SRST_PCIE30PHY>;
+ reset-names = "phy";
+ rockchip,phy-grf = <&pcie30_phy_grf>;
+ };
--
2.34.1
On 25-08-22, 21:38, Frank Wunderlich wrote:
> From: Frank Wunderlich <[email protected]>
>
> Add a new binding file for Rockchip PCIe v3 phy driver.
Applied, thanks
--
~Vinod
On Thu, Aug 25, 2022 at 09:38:32PM +0200, Frank Wunderlich wrote:
> From: Frank Wunderlich <[email protected]>
>
> Add a new binding file for Rockchip PCIe v3 phy driver.
>
> Signed-off-by: Frank Wunderlich <[email protected]>
> Reviewed-by: Krzysztof Kozlowski <[email protected]>
> ---
> v4:
> - add reviewed-by
> - remove minitems for clock-names as i have static list to fix error
> - fix reg error by using 32-bit adressing in binding example
> - change lane-map to u32 data-lanes
> - tried to move data-lanes to phy-provider
> https://github.com/frank-w/dt-schema/blob/main/dtschema/schemas/phy/phy-provider.yaml#L17
> cloned and installed via pip install -e <local path>
> verified with pip show, but phy-privider seems not to be applied
>
> v3:
> - drop quotes
> - drop rk3588
> - make clockcount fixed to 3
> - full path for binding header file
> - drop phy-mode and its header and add lane-map
>
> v2:
> dt-bindings: rename yaml for PCIe v3
> rockchip-pcie3-phy.yaml => rockchip,pcie3-phy.yaml
>
> changes in pcie3 phy yaml
> - change clock names to ordered const list
> - extend pcie30-phymode description
> - add phy-cells to required properties
> - drop unevaluatedProperties
> - example with 1 clock each line
> - use default property instead of text describing it
> - update license
> ---
> .../bindings/phy/rockchip,pcie3-phy.yaml | 80 +++++++++++++++++++
> 1 file changed, 80 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
> new file mode 100644
> index 000000000000..9f2d8d2cc7a5
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
> @@ -0,0 +1,80 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/rockchip,pcie3-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Rockchip PCIe v3 phy
> +
> +maintainers:
> + - Heiko Stuebner <[email protected]>
> +
> +properties:
> + compatible:
> + enum:
> + - rockchip,rk3568-pcie3-phy
The driver also has 'rockchip,rk3588-pcie3-phy'. Please send a fix
adding it here or removing from the driver. Are they not compatible with
each other?
Rob
Am 4. Oktober 2022 17:09:29 MESZ schrieb Rob Herring <[email protected]>:
>On Thu, Aug 25, 2022 at 09:38:32PM +0200, Frank Wunderlich wrote:
>> From: Frank Wunderlich <[email protected]>
>> +properties:
>> + compatible:
>> + enum:
>> + - rockchip,rk3568-pcie3-phy
>
>The driver also has 'rockchip,rk3588-pcie3-phy'. Please send a fix
>adding it here or removing from the driver. Are they not compatible with
>each other?
Hi,
Right,
original driver has rk3588 support,but we can't test it. Initialization and lane-mapping (bifurcation) was bit different. So we wanted to upstream rk3568 first (but have not removed this part from driver).
I see that someone added rk3588 basic support and if he can test rk3588 i can send compatible for it.
regards Frank
Hi,
On Tue, Oct 04, 2022 at 05:19:11PM +0200, Frank Wunderlich wrote:
> Am 4. Oktober 2022 17:09:29 MESZ schrieb Rob Herring <[email protected]>:
> >On Thu, Aug 25, 2022 at 09:38:32PM +0200, Frank Wunderlich wrote:
> >> From: Frank Wunderlich <[email protected]>
>
> >> +properties:
> >> + compatible:
> >> + enum:
> >> + - rockchip,rk3568-pcie3-phy
> >
> >The driver also has 'rockchip,rk3588-pcie3-phy'. Please send a fix
> >adding it here or removing from the driver. Are they not compatible with
> >each other?
>
> Right, original driver has rk3588 support,but we can't test it.
> Initialization and lane-mapping (bifurcation) was bit different.
> So we wanted to upstream rk3568 first (but have not removed this
> part from driver).
>
> I see that someone added rk3588 basic support and if he can test
> rk3588 i can send compatible for it.
Basic rk3588 support is still WIP. At the moment patches for the CRU
are still pending as well as base DT. I hope to land them for v6.2
(so next merge window). At the same time I don't think PCIe support
is realistic before v6.3.
-- Sebastian
On 5/10/2022 7:57 am, Sebastian Reichel wrote:
> Hi,
>
> On Tue, Oct 04, 2022 at 05:19:11PM +0200, Frank Wunderlich wrote:
>> Am 4. Oktober 2022 17:09:29 MESZ schrieb Rob Herring <[email protected]>:
>>> On Thu, Aug 25, 2022 at 09:38:32PM +0200, Frank Wunderlich wrote:
>>>> From: Frank Wunderlich <[email protected]>
>>
>>>> +properties:
>>>> + compatible:
>>>> + enum:
>>>> + - rockchip,rk3568-pcie3-phy
>>>
>>> The driver also has 'rockchip,rk3588-pcie3-phy'. Please send a fix
>>> adding it here or removing from the driver. Are they not compatible with
>>> each other?
>>
>> Right, original driver has rk3588 support,but we can't test it.
>> Initialization and lane-mapping (bifurcation) was bit different.
>> So we wanted to upstream rk3568 first (but have not removed this
>> part from driver).
>>
>> I see that someone added rk3588 basic support and if he can test
>> rk3588 i can send compatible for it.
>
> Basic rk3588 support is still WIP. At the moment patches for the CRU
> are still pending as well as base DT. I hope to land them for v6.2
> (so next merge window). At the same time I don't think PCIe support
> is realistic before v6.3.
Hi all,
I can confirm this patchset successfully brings up the PCIe 3.0
controller/PHY on an RK3588 - I'm using a Pine64 QuartzPro64, which is
very similar to the Rockchip RK3588-EVB1 board. Runs fine at x1, x2, x4
lane widths and full 8GT/s lane throughput.
The PCIe 2.0 lanes (which use the same PCIe controller driver) need some
changes to the rockchip-naneng-combphy driver that I've not quite gotten
to a working state, but that's unrelated to this series.
I have a (very messy) tree based on v6.0 (on GitHub at [0]) with
Sebastian's other RK3588 support patches dropped in, along with this
series and a few other tweaks. Works quite well :)
So insofar as RK3588 support is concerned,
Tested-By: Andrew Powers-Holmes <[email protected]>
[0] https://github.com/neggles/linux-quartz64/tree/qp64-pcie
Cheers,
A