Hello Everyone!
This series enables the VTM nodes for all of Texas Instruments K3 SoCs
Most of this series updates the k3_j72xx_bandgap driver to conditionally
map an eFuse region used by the j721e to work around an issue in its VTM
implementation and allows us to save the SPARE_FUSE region on other SoCs
We can then update the device tree bindings for the driver and finally
define the VTM nodes for each device.
Thanks for reviewing!
~Bryan
Bryan Brattlof (11):
thermal: k3_j72xx_bandgap: simplify k3_thermal_get_temp() function
thermal: k3_j72xx_bandgap: use bool for i2128 erratum flag
thermal: k3_j72xx_bandgap: remove fuse_base from structure
thermal: k3_j72xx_bandgap: map fuse_base only for erratum workaround
dt-bindings: thermal: k3-j72xx: elaborate on binding descriptions
dt-bindings: thermal: k3-j72xx: conditionally require efuse reg range
arm64: dts: ti: k3-am64-main: add VTM node
arm64: dts: ti: k3-am62-wakeup: add VTM node
arm64: dts: ti: k3-j721e-mcu-wakeup: add VTM node
arm64: dts: ti: k3-j721s2-mcu-wakeup: add VTM node
arm64: dts: ti: k3-j7200-mcu-wakeup: add VTM node
.../bindings/thermal/ti,j72xx-thermal.yaml | 51 ++++++++-
arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi | 33 ++++++
arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 8 ++
arch/arm64/boot/dts/ti/k3-am62.dtsi | 7 +-
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 8 ++
arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi | 33 ++++++
arch/arm64/boot/dts/ti/k3-am64.dtsi | 4 +
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 8 ++
arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi | 47 ++++++++
arch/arm64/boot/dts/ti/k3-j7200.dtsi | 3 +
.../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 9 ++
arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi | 75 +++++++++++++
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 3 +
.../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 8 ++
arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi | 103 ++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 3 +
drivers/thermal/k3_j72xx_bandgap.c | 65 +++++------
17 files changed, 430 insertions(+), 38 deletions(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi
create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi
--
2.38.0
Only some of TI's J721E SoCs will need a eFuse register range mapped to
determine if they're affected by TI's i2128 erratum. All other SoC will
not need this eFuse range to be mapped to function properly
Update the bindings for the k3_j72xx_bandgap thermal driver so other
devices will only need to define two register ranges
Signed-off-by: Bryan Brattlof <[email protected]>
---
.../bindings/thermal/ti,j72xx-thermal.yaml | 34 +++++++++++++------
1 file changed, 24 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml b/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml
index 0b6a6fa07a532..387628ab35959 100644
--- a/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml
+++ b/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml
@@ -33,16 +33,6 @@ properties:
- ti,j721e-vtm
- ti,j7200-vtm
- reg:
- items:
- - description: VTM cfg1 register space
- - description: VTM cfg2 register space
- - description: |
- A software trimming method must be applied to some Jacinto
- devices to function properly. This eFuse region provides
- the information needed for these SoCs to report
- temperatures accurately.
-
power-domains:
description: |
Should contain the phandle to a power management (PM) domain
@@ -52,6 +42,30 @@ properties:
"#thermal-sensor-cells":
const: 1
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ti,j721e-vtm
+then:
+ properties:
+ reg:
+ items:
+ - description: VTM cfg1 register space
+ - description: VTM cfg2 register space
+ - description: |
+ A software trimming method must be applied to some Jacinto
+ devices to function properly. This eFuse region provides
+ the information needed for these SoCs to report
+ temperatures accurately.
+else:
+ properties:
+ reg:
+ items:
+ - description: VTM cfg1 register space
+ - description: VTM cfg2 register space
+
required:
- compatible
- reg
--
2.38.0
Some of TI's J721E's require a software trimming method to report
temperatures accurately. Currently we are using a few different data
types to indicate when this device should apply the erratum.
Change the 'workaround_needed' variable's data type to a bool to align
with how we are using this variable currently.
Signed-off-by: Bryan Brattlof <[email protected]>
---
drivers/thermal/k3_j72xx_bandgap.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/thermal/k3_j72xx_bandgap.c b/drivers/thermal/k3_j72xx_bandgap.c
index a9f99a190cb61..b9d20026771a5 100644
--- a/drivers/thermal/k3_j72xx_bandgap.c
+++ b/drivers/thermal/k3_j72xx_bandgap.c
@@ -340,7 +340,7 @@ static void print_look_up_table(struct device *dev, int *ref_table)
}
struct k3_j72xx_bandgap_data {
- unsigned int has_errata_i2128;
+ const bool has_errata_i2128;
};
static int k3_j72xx_bandgap_probe(struct platform_device *pdev)
@@ -351,7 +351,7 @@ static int k3_j72xx_bandgap_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct k3_j72xx_bandgap *bgp;
struct k3_thermal_data *data;
- int workaround_needed = 0;
+ bool workaround_needed = false;
const struct k3_j72xx_bandgap_data *driver_data;
struct thermal_zone_device *ti_thermal;
int *ref_table;
@@ -522,11 +522,11 @@ static int k3_j72xx_bandgap_remove(struct platform_device *pdev)
}
static const struct k3_j72xx_bandgap_data k3_j72xx_bandgap_j721e_data = {
- .has_errata_i2128 = 1,
+ .has_errata_i2128 = true,
};
static const struct k3_j72xx_bandgap_data k3_j72xx_bandgap_j7200_data = {
- .has_errata_i2128 = 0,
+ .has_errata_i2128 = false,
};
static const struct of_device_id of_k3_j72xx_bandgap_match[] = {
--
2.38.0
The k3_thermal_get_temp() function can be simplified to return only
the result of k3_bgp_read_temp() without needing the 'ret' variable
Signed-off-by: Bryan Brattlof <[email protected]>
---
drivers/thermal/k3_j72xx_bandgap.c | 9 +--------
1 file changed, 1 insertion(+), 8 deletions(-)
diff --git a/drivers/thermal/k3_j72xx_bandgap.c b/drivers/thermal/k3_j72xx_bandgap.c
index c073b1023bbe7..a9f99a190cb61 100644
--- a/drivers/thermal/k3_j72xx_bandgap.c
+++ b/drivers/thermal/k3_j72xx_bandgap.c
@@ -249,14 +249,7 @@ static inline int k3_bgp_read_temp(struct k3_thermal_data *devdata,
/* Get temperature callback function for thermal zone */
static int k3_thermal_get_temp(struct thermal_zone_device *tz, int *temp)
{
- struct k3_thermal_data *data = tz->devdata;
- int ret = 0;
-
- ret = k3_bgp_read_temp(data, temp);
- if (ret)
- return ret;
-
- return ret;
+ return k3_bgp_read_temp(tz->devdata, temp);
}
static const struct thermal_zone_device_ops k3_of_thermal_ops = {
--
2.38.0
The am64x supports a single VTM module which is located in the main
domain with two associated temperature monitors located at different hot
spots on the die.
Signed-off-by: Bryan Brattlof <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am64-main.dtsi | 8 +++++
arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi | 33 +++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am64.dtsi | 4 +++
3 files changed, 45 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi
diff --git a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
index ada00575f0f2e..4cd687cc44d9e 100644
--- a/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64-main.dtsi
@@ -1308,4 +1308,12 @@ main_mcan1: can@20711000 {
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
+
+ vtm0: temperature-sensor@b00000 {
+ compatible = "ti,j7200-vtm";
+ reg = <0x00 0xb00000 0x00 0x400>,
+ <0x00 0xb01000 0x00 0x400>;
+ power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
+ #thermal-sensor-cells = <1>;
+ };
};
diff --git a/arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi
new file mode 100644
index 0000000000000..1819a6948b19d
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am64-thermal.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+thermal_zones: thermal-zones {
+ main0_thermal: main0-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 0>;
+
+ trips {
+ main0_crit: main0-crit {
+ temperature = <105000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main1_thermal: main1-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 1>;
+
+ trips {
+ main1_crit: main1-crit {
+ temperature = <105000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am64.dtsi b/arch/arm64/boot/dts/ti/k3-am64.dtsi
index 016dd8511ca6f..4ebee0be648e0 100644
--- a/arch/arm64/boot/dts/ti/k3-am64.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am64.dtsi
@@ -69,6 +69,7 @@ cbass_main: bus@f4000 {
<0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
<0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
<0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
+ <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
<0x00 0x01000000 0x00 0x01000000 0x00 0x02330400>, /* First peripheral window */
<0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_CORE */
@@ -104,6 +105,9 @@ cbass_mcu: bus@4000000 {
ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */
};
};
+
+ #include "k3-am64-thermal.dtsi"
+
};
/* Now include the peripherals for each bus segments */
--
2.38.0
The am62x supports a single Voltage and Thermal Management (VTM) module
located in the wakeup domain with two associated temperature monitors
located in hot spots of the die.
Signed-off-by: Bryan Brattlof <[email protected]>
---
arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi | 33 +++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi | 8 +++++
arch/arm64/boot/dts/ti/k3-am62.dtsi | 7 ++++-
3 files changed, 47 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi
diff --git a/arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi
new file mode 100644
index 0000000000000..1819a6948b19d
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62-thermal.dtsi
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+thermal_zones: thermal-zones {
+ main0_thermal: main0-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 0>;
+
+ trips {
+ main0_crit: main0-crit {
+ temperature = <105000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main1_thermal: main1-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 1>;
+
+ trips {
+ main1_crit: main1-crit {
+ temperature = <105000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
index 4090134676cf6..3954a73a33f35 100644
--- a/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62-wakeup.dtsi
@@ -38,4 +38,12 @@ wkup_i2c0: i2c@2b200000 {
clocks = <&k3_clks 107 4>;
clock-names = "fck";
};
+
+ vtm0: temperature-sensor@b00000 {
+ compatible = "ti,j7200-vtm";
+ reg = <0x00 0xb00000 0x00 0x400>,
+ <0x00 0xb01000 0x00 0x400>;
+ power-domains = <&k3_pds 95 TI_SCI_PD_EXCLUSIVE>;
+ #thermal-sensor-cells = <1>;
+ };
};
diff --git a/arch/arm64/boot/dts/ti/k3-am62.dtsi b/arch/arm64/boot/dts/ti/k3-am62.dtsi
index 37fcbe7a3c336..1795f3ee534e0 100644
--- a/arch/arm64/boot/dts/ti/k3-am62.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62.dtsi
@@ -80,6 +80,7 @@ cbass_main: bus@f0000 {
<0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>,
/* Wakeup Domain Range */
+ <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
<0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>,
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
@@ -94,10 +95,14 @@ cbass_wakeup: bus@2b000000 {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
- ranges = <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
+ ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */
+ <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */
<0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>;
};
};
+
+ #include "k3-am62-thermal.dtsi"
+
};
/* Now include the peripherals for each bus segments */
--
2.38.0
The j721s2 supports a single Voltage and Thermal Management (VTM) device
located in the wakeup domain with seven associated temperature monitors
located in various hot spots on the die.
Signed-off-by: Bryan Brattlof <[email protected]>
---
.../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 8 ++
arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi | 103 ++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721s2.dtsi | 3 +
3 files changed, 114 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
index 4d1bfabd1313a..8287fd32c42f3 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi
@@ -299,4 +299,12 @@ cpts@3d000 {
ti,cpts-periodic-outputs = <2>;
};
};
+
+ vtm0: temperature-sensor@42040000 {
+ compatible = "ti,j7200-vtm";
+ reg = <0x0 0x42040000 0x0 0x350>,
+ <0x0 0x42050000 0x0 0x350>;
+ power-domains = <&k3_pds 154 TI_SCI_PD_SHARED>;
+ #thermal-sensor-cells = <1>;
+ };
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi
new file mode 100644
index 0000000000000..c51009536756e
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-thermal.dtsi
@@ -0,0 +1,103 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+thermal_zones: thermal-zones {
+ wkup0_thermal: wkup0-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 0>;
+
+ trips {
+ wkup0_crit: wkup0-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ wkup1_thermal: wkup1-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 1>;
+
+ trips {
+ wkup1_crit: wkup1-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main0_thermal: main0-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 2>;
+
+ trips {
+ main0_crit: main0-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main1_thermal: main1-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 3>;
+
+ trips {
+ main1_crit: main1-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main2_thermal: main2-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 4>;
+
+ trips {
+ main2_crit: main2-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main3_thermal: main3-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 5>;
+
+ trips {
+ main3_crit: main3-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main4_thermal: main4-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 6>;
+
+ trips {
+ main4_crit: main4-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi
index 7b930a85a29d6..33ea52e28b24f 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2.dtsi
@@ -161,6 +161,9 @@ cbass_mcu_wakeup: bus@28380000 {
};
};
+
+ #include "k3-j721s2-thermal.dtsi"
+
};
/* Now include peripherals from each bus segment */
--
2.38.0
The j7200 supports a single Voltage and Thermal Management (VTM) device
located in the wakeup domain with three associated temperature monitors
located in various hot spots on the die.
Signed-off-by: Bryan Brattlof <[email protected]>
---
.../boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 8 ++++
arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi | 47 +++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j7200.dtsi | 3 ++
3 files changed, 58 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index ff13bbeed30c9..34d3e9bbd181c 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -375,4 +375,12 @@ mcu_r5fss0_core1: r5f@41400000 {
ti,loczrama = <1>;
};
};
+
+ vtm0: temperature-sensor@42040000 {
+ compatible = "ti,j7200-vtm";
+ reg = <0x00 0x42040000 0x00 0x350>,
+ <0x00 0x42050000 0x00 0x350>;
+ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+ #thermal-sensor-cells = <1>;
+ };
};
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi
new file mode 100644
index 0000000000000..0bf52c93c3f9a
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j7200-thermal.dtsi
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+thermal_zones: thermal-zones {
+ mcu_thermal: mcu-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 0>;
+
+ trips {
+ wkup_crit: wkup-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ mpu_thermal: mpu-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 1>;
+
+ trips {
+ mpu_crit: mpu-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ main_thermal: main-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 2>;
+
+ trips {
+ c7x_crit: c7x-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j7200.dtsi b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
index b6da0454cc5bd..9368a6e3d4a62 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200.dtsi
@@ -168,6 +168,9 @@ cbass_mcu_wakeup: bus@28380000 {
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3 */
};
};
+
+ #include "k3-j7200-thermal.dtsi"
+
};
/* Now include the peripherals for each bus segments */
--
2.38.0
Elaborate on the function of this device node as well as some of the
properties that this node uses.
Signed-off-by: Bryan Brattlof <[email protected]>
---
.../bindings/thermal/ti,j72xx-thermal.yaml | 27 ++++++++++++++++++-
1 file changed, 26 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml b/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml
index c74f124ebfc00..0b6a6fa07a532 100644
--- a/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml
+++ b/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml
@@ -9,6 +9,24 @@ title: Texas Instruments J72XX VTM (DTS) binding
maintainers:
- Keerthy <[email protected]>
+description: |
+ The TI K3 family of SoCs typically have a Voltage & Thermal
+ Management (VTM) device to control up to 8 temperature diode
+ sensors to measure silicon junction temperatures from different
+ hotspots of the chip as well as provide temperature, interrupt
+ and alerting information.
+
+ The VTM device will periodically enable these temperature sensors
+ to make a temperature measurement and store the reported data
+ allowing the sensors to stay in a reset state when not in use
+ to maximize the sensor's life.
+
+ This VTM driver will then use the following polynomial equation to
+ calculate the temperature from the value stored in the VTM device.
+
+ Temp = (-9.2627e-12) * x^4 + (6.0373e-08) * x^3 + \
+ (-1.7058e-04) * x^2 + (3.2512e-01) * x + (-4.9003e+01)
+
properties:
compatible:
enum:
@@ -19,9 +37,16 @@ properties:
items:
- description: VTM cfg1 register space
- description: VTM cfg2 register space
- - description: VTM efuse register space
+ - description: |
+ A software trimming method must be applied to some Jacinto
+ devices to function properly. This eFuse region provides
+ the information needed for these SoCs to report
+ temperatures accurately.
power-domains:
+ description: |
+ Should contain the phandle to a power management (PM) domain
+ node and the device-id of this device.
maxItems: 1
"#thermal-sensor-cells":
--
2.38.0
The j721e supports a single Voltage and Thermal Management (VTM) module
located in the wakeup domain with five associated temperature monitors
located in various hot spots on the die.
Signed-off-by: Bryan Brattlof <[email protected]>
---
.../boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 9 +++
arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi | 75 +++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 3 +
3 files changed, 87 insertions(+)
create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index df08724bbf1c5..9a09f66c51c01 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -418,4 +418,13 @@ mcu_mcan1: can@40568000 {
interrupt-names = "int0", "int1";
bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
};
+
+ vtm0: temperature-sensor@42040000 {
+ compatible = "ti,j721e-vtm";
+ reg = <0x00 0x42040000 0x00 0x350>,
+ <0x00 0x42050000 0x00 0x350>,
+ <0x00 0x43000300 0x00 0x10>;
+ power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
+ #thermal-sensor-cells = <1>;
+ };
};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi
new file mode 100644
index 0000000000000..79641927a9092
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721e-thermal.dtsi
@@ -0,0 +1,75 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#include <dt-bindings/thermal/thermal.h>
+
+thermal_zones: thermal-zones {
+ wkup_thermal: wkup-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 0>;
+
+ trips {
+ wkup_crit: wkup-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ mpu_thermal: mpu-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 1>;
+
+ trips {
+ mpu_crit: mpu-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ c7x_thermal: c7x-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 2>;
+
+ trips {
+ c7x_crit: c7x-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ gpu_thermal: gpu-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 3>;
+
+ trips {
+ gpu_crit: gpu-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+
+ r5f_thermal: r5f-thermal {
+ polling-delay-passive = <250>; /* milliSeconds */
+ polling-delay = <500>; /* milliSeconds */
+ thermal-sensors = <&vtm0 4>;
+
+ trips {
+ r5f_crit: r5f-crit {
+ temperature = <125000>; /* milliCelsius */
+ hysteresis = <2000>; /* milliCelsius */
+ type = "critical";
+ };
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index 0e23886c9fd1d..cfab10e2455c4 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -181,6 +181,9 @@ cbass_mcu_wakeup: bus@28380000 {
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
};
};
+
+ #include "k3-j721e-thermal.dtsi"
+
};
/* Now include the peripherals for each bus segments */
--
2.38.0
'fuse_base' is only needed during the initial probe function to provide
a software trimming method for some devices effected by TI's i2128
erratum. Not all devices that use this hardware device will need to map
this eFuse region.
Remove fuse_base from the main k3_j72xx_bandgap structure
Signed-off-by: Bryan Brattlof <[email protected]>
---
drivers/thermal/k3_j72xx_bandgap.c | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/thermal/k3_j72xx_bandgap.c b/drivers/thermal/k3_j72xx_bandgap.c
index b9d20026771a5..99df62295a11f 100644
--- a/drivers/thermal/k3_j72xx_bandgap.c
+++ b/drivers/thermal/k3_j72xx_bandgap.c
@@ -177,7 +177,6 @@ struct k3_j72xx_bandgap {
struct device *dev;
void __iomem *base;
void __iomem *cfg2_base;
- void __iomem *fuse_base;
struct k3_thermal_data *ts_data[K3_VTM_MAX_NUM_TS];
};
@@ -276,7 +275,7 @@ static int k3_j72xx_bandgap_temp_to_adc_code(int temp)
}
static void get_efuse_values(int id, struct k3_thermal_data *data, int *err,
- struct k3_j72xx_bandgap *bgp)
+ void __iomem *fuse_base)
{
int i, tmp, pow;
int ct_offsets[5][K3_VTM_CORRECTION_TEMP_CNT] = {
@@ -298,16 +297,16 @@ static void get_efuse_values(int id, struct k3_thermal_data *data, int *err,
/* Extract the offset value using bit-mask */
if (ct_offsets[id][i] == -1 && i == 1) {
/* 25C offset Case of Sensor 2 split between 2 regs */
- tmp = (readl(bgp->fuse_base + 0x8) & 0xE0000000) >> (29);
- tmp |= ((readl(bgp->fuse_base + 0xC) & 0x1F) << 3);
+ tmp = (readl(fuse_base + 0x8) & 0xE0000000) >> (29);
+ tmp |= ((readl(fuse_base + 0xC) & 0x1F) << 3);
pow = tmp & 0x80;
} else if (ct_offsets[id][i] == -1 && i == 2) {
/* 125C Case of Sensor 3 split between 2 regs */
- tmp = (readl(bgp->fuse_base + 0x4) & 0xF8000000) >> (27);
- tmp |= ((readl(bgp->fuse_base + 0x8) & 0xF) << 5);
+ tmp = (readl(fuse_base + 0x4) & 0xF8000000) >> (27);
+ tmp |= ((readl(fuse_base + 0x8) & 0xF) << 5);
pow = tmp & 0x100;
} else {
- tmp = readl(bgp->fuse_base + ct_offsets[id][i]);
+ tmp = readl(fuse_base + ct_offsets[id][i]);
tmp &= ct_bm[id][i];
tmp = tmp >> __ffs(ct_bm[id][i]);
@@ -356,6 +355,7 @@ static int k3_j72xx_bandgap_probe(struct platform_device *pdev)
struct thermal_zone_device *ti_thermal;
int *ref_table;
struct err_values err_vals;
+ void __iomem *fuse_base;
const s64 golden_factors[] = {
-490019999999999936,
@@ -387,9 +387,9 @@ static int k3_j72xx_bandgap_probe(struct platform_device *pdev)
return PTR_ERR(bgp->cfg2_base);
res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
- bgp->fuse_base = devm_ioremap_resource(dev, res);
- if (IS_ERR(bgp->fuse_base))
- return PTR_ERR(bgp->fuse_base);
+ fuse_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(fuse_base))
+ return PTR_ERR(fuse_base);
driver_data = of_device_get_match_data(dev);
if (driver_data)
@@ -428,7 +428,7 @@ static int k3_j72xx_bandgap_probe(struct platform_device *pdev)
}
/* Workaround not needed if bit30/bit31 is set even for J721e */
- if (workaround_needed && (readl(bgp->fuse_base + 0x0) & 0xc0000000) == 0xc0000000)
+ if (workaround_needed && (readl(fuse_base + 0x0) & 0xc0000000) == 0xc0000000)
workaround_needed = false;
dev_dbg(bgp->dev, "Work around %sneeded\n",
--
2.38.0
Some of TI's J721E SoCs require a software trimming procedure for the
temperature monitors to function properly. To determine if a particular
J721E is not affected by this erratum, both bits in the WKUP_SPARE_FUSE0
region must be set. Other SoCs, not affected by this erratum, will not
need this region.
Map the 'fuse_base' region only when the erratum fix is needed.
Signed-off-by: Bryan Brattlof <[email protected]>
---
drivers/thermal/k3_j72xx_bandgap.c | 34 +++++++++++++++++++-----------
1 file changed, 22 insertions(+), 12 deletions(-)
diff --git a/drivers/thermal/k3_j72xx_bandgap.c b/drivers/thermal/k3_j72xx_bandgap.c
index 99df62295a11f..fdba116f7fe7b 100644
--- a/drivers/thermal/k3_j72xx_bandgap.c
+++ b/drivers/thermal/k3_j72xx_bandgap.c
@@ -386,15 +386,32 @@ static int k3_j72xx_bandgap_probe(struct platform_device *pdev)
if (IS_ERR(bgp->cfg2_base))
return PTR_ERR(bgp->cfg2_base);
- res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
- fuse_base = devm_ioremap_resource(dev, res);
- if (IS_ERR(fuse_base))
- return PTR_ERR(fuse_base);
-
driver_data = of_device_get_match_data(dev);
if (driver_data)
workaround_needed = driver_data->has_errata_i2128;
+ /*
+ * Some of TI's J721E SoCs require a software trimming procedure
+ * for the temperature monitors to function properly. To determine
+ * if this particular SoC is NOT affected, both bits in the
+ * WKUP_SPARE_FUSE0[31:30] will be set (0xC0000000) indicating
+ * when software trimming should NOT be applied.
+ *
+ * https://www.ti.com/lit/er/sprz455c/sprz455c.pdf
+ */
+ if (workaround_needed) {
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
+ fuse_base = devm_ioremap_resource(dev, res);
+ if (IS_ERR(fuse_base))
+ return PTR_ERR(fuse_base);
+
+ if ((readl(fuse_base) & 0xc0000000) == 0xc0000000)
+ workaround_needed = false;
+ }
+
+ dev_dbg(bgp->dev, "Work around %sneeded\n",
+ workaround_needed ? "" : "not ");
+
pm_runtime_enable(dev);
ret = pm_runtime_get_sync(dev);
if (ret < 0) {
@@ -427,13 +444,6 @@ static int k3_j72xx_bandgap_probe(struct platform_device *pdev)
goto err_free_ref_table;
}
- /* Workaround not needed if bit30/bit31 is set even for J721e */
- if (workaround_needed && (readl(fuse_base + 0x0) & 0xc0000000) == 0xc0000000)
- workaround_needed = false;
-
- dev_dbg(bgp->dev, "Work around %sneeded\n",
- workaround_needed ? "" : "not ");
-
if (!workaround_needed)
init_table(5, ref_table, golden_factors);
else
--
2.38.0
On Tue, 11 Oct 2022 18:17:22 -0500, Bryan Brattlof wrote:
> Only some of TI's J721E SoCs will need a eFuse register range mapped to
> determine if they're affected by TI's i2128 erratum. All other SoC will
> not need this eFuse range to be mapped to function properly
>
> Update the bindings for the k3_j72xx_bandgap thermal driver so other
> devices will only need to define two register ranges
>
> Signed-off-by: Bryan Brattlof <[email protected]>
> ---
> .../bindings/thermal/ti,j72xx-thermal.yaml | 34 +++++++++++++------
> 1 file changed, 24 insertions(+), 10 deletions(-)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.example.dtb: thermal-sensor@42040000: 'reg' does not match any of the regexes: 'pinctrl-[0-9]+'
From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
On 11/10/2022 19:17, Bryan Brattlof wrote:
> +then:
> + properties:
> + reg:
> + items:
> + - description: VTM cfg1 register space
> + - description: VTM cfg2 register space
> + - description: |
> + A software trimming method must be applied to some Jacinto
> + devices to function properly. This eFuse region provides
> + the information needed for these SoCs to report
> + temperatures accurately.
> +else:
> + properties:
> + reg:
> + items:
> + - description: VTM cfg1 register space
> + - description: VTM cfg2 register space
> +
BTW, you have additionalProperties:false, so how you coded it won't
work. Test your bindings before sending.
Best regards,
Krzysztof
On 11/10/2022 19:17, Bryan Brattlof wrote:
> Only some of TI's J721E SoCs will need a eFuse register range mapped to
> determine if they're affected by TI's i2128 erratum. All other SoC will
> not need this eFuse range to be mapped to function properly
>
> Update the bindings for the k3_j72xx_bandgap thermal driver so other
> devices will only need to define two register ranges
>
> Signed-off-by: Bryan Brattlof <[email protected]>
> ---
> .../bindings/thermal/ti,j72xx-thermal.yaml | 34 +++++++++++++------
> 1 file changed, 24 insertions(+), 10 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml b/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml
> index 0b6a6fa07a532..387628ab35959 100644
> --- a/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml
> +++ b/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml
> @@ -33,16 +33,6 @@ properties:
> - ti,j721e-vtm
> - ti,j7200-vtm
>
> - reg:
No, keep entire part here.
with minItems:2
> - items:
> - - description: VTM cfg1 register space
> - - description: VTM cfg2 register space
> - - description: |
> - A software trimming method must be applied to some Jacinto
> - devices to function properly. This eFuse region provides
> - the information needed for these SoCs to report
> - temperatures accurately.
> -
> power-domains:
> description: |
> Should contain the phandle to a power management (PM) domain
> @@ -52,6 +42,30 @@ properties:
> "#thermal-sensor-cells":
> const: 1
>
> +if:
Put it under allOf.
> + properties:
> + compatible:
> + contains:
> + enum:
> + - ti,j721e-vtm
> +then:
> + properties:
> + reg:
> + items:
> + - description: VTM cfg1 register space
> + - description: VTM cfg2 register space
> + - description: |
> + A software trimming method must be applied to some Jacinto
> + devices to function properly. This eFuse region provides
> + the information needed for these SoCs to report
> + temperatures accurately.
Instead:
minItems: 3
> +else:
> + properties:
> + reg:
> + items:
> + - description: VTM cfg1 register space
> + - description: VTM cfg2 register space
Instead:
maxItems: 2
> +
> required:
> - compatible
> - reg
Best regards,
Krzysztof
On 11/10/2022 19:17, Bryan Brattlof wrote:
> Elaborate on the function of this device node as well as some of the
> properties that this node uses.
>
> Signed-off-by: Bryan Brattlof <[email protected]>
> ---
> .../bindings/thermal/ti,j72xx-thermal.yaml | 27 ++++++++++++++++++-
> 1 file changed, 26 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml b/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml
> index c74f124ebfc00..0b6a6fa07a532 100644
> --- a/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml
> +++ b/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml
> @@ -9,6 +9,24 @@ title: Texas Instruments J72XX VTM (DTS) binding
> maintainers:
> - Keerthy <[email protected]>
>
> +description: |
> + The TI K3 family of SoCs typically have a Voltage & Thermal
> + Management (VTM) device to control up to 8 temperature diode
> + sensors to measure silicon junction temperatures from different
> + hotspots of the chip as well as provide temperature, interrupt
> + and alerting information.
> +
> + The VTM device will periodically enable these temperature sensors
> + to make a temperature measurement and store the reported data
> + allowing the sensors to stay in a reset state when not in use
> + to maximize the sensor's life.
> +
> + This VTM driver will then use the following polynomial equation to
"VTM driver" is some physical/electronic element called driver? Or Linux
driver? If the latter, drop it and just describe the equation.
> + calculate the temperature from the value stored in the VTM device.
> +
> + Temp = (-9.2627e-12) * x^4 + (6.0373e-08) * x^3 + \
> + (-1.7058e-04) * x^2 + (3.2512e-01) * x + (-4.9003e+01)
> +
> properties:
> compatible:
> enum:
> @@ -19,9 +37,16 @@ properties:
> items:
> - description: VTM cfg1 register space
> - description: VTM cfg2 register space
> - - description: VTM efuse register space
> + - description: |
> + A software trimming method must be applied to some Jacinto
> + devices to function properly. This eFuse region provides
> + the information needed for these SoCs to report
> + temperatures accurately.
>
> power-domains:
> + description: |
> + Should contain the phandle to a power management (PM) domain
> + node and the device-id of this device.
This is quite generic - why adding it?
> maxItems: 1
>
> "#thermal-sensor-cells":
Best regards,
Krzysztof
On October 12, 2022 thus sayeth Krzysztof Kozlowski:
> On 11/10/2022 19:17, Bryan Brattlof wrote:
> > Only some of TI's J721E SoCs will need a eFuse register range mapped to
> > determine if they're affected by TI's i2128 erratum. All other SoC will
> > not need this eFuse range to be mapped to function properly
> >
> > Update the bindings for the k3_j72xx_bandgap thermal driver so other
> > devices will only need to define two register ranges
> >
> > Signed-off-by: Bryan Brattlof <[email protected]>
> > ---
> > .../bindings/thermal/ti,j72xx-thermal.yaml | 34 +++++++++++++------
> > 1 file changed, 24 insertions(+), 10 deletions(-)
> >
> > diff --git a/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml b/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml
> > index 0b6a6fa07a532..387628ab35959 100644
> > --- a/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml
> > +++ b/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml
> > @@ -33,16 +33,6 @@ properties:
> > - ti,j721e-vtm
> > - ti,j7200-vtm
> >
> > - reg:
>
> No, keep entire part here.
> with minItems:2
>
Ah ok! I was unsure what this should look like. Your way is better :)
Thanks Krzysztof
~Bryan
On October 12, 2022 thus sayeth Krzysztof Kozlowski:
> On 11/10/2022 19:17, Bryan Brattlof wrote:
> > Elaborate on the function of this device node as well as some of the
> > properties that this node uses.
> >
> > Signed-off-by: Bryan Brattlof <[email protected]>
> > ---
> > .../bindings/thermal/ti,j72xx-thermal.yaml | 27 ++++++++++++++++++-
> > 1 file changed, 26 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml b/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml
> > index c74f124ebfc00..0b6a6fa07a532 100644
> > --- a/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml
> > +++ b/Documentation/devicetree/bindings/thermal/ti,j72xx-thermal.yaml
> > @@ -9,6 +9,24 @@ title: Texas Instruments J72XX VTM (DTS) binding
> > maintainers:
> > - Keerthy <[email protected]>
> >
> > +description: |
> > + The TI K3 family of SoCs typically have a Voltage & Thermal
> > + Management (VTM) device to control up to 8 temperature diode
> > + sensors to measure silicon junction temperatures from different
> > + hotspots of the chip as well as provide temperature, interrupt
> > + and alerting information.
> > +
> > + The VTM device will periodically enable these temperature sensors
> > + to make a temperature measurement and store the reported data
> > + allowing the sensors to stay in a reset state when not in use
> > + to maximize the sensor's life.
> > +
> > + This VTM driver will then use the following polynomial equation to
>
> "VTM driver" is some physical/electronic element called driver? Or Linux
> driver? If the latter, drop it and just describe the equation.
Yeah I was trying to talk about the Linux driver. I'll edit it to only
the equation.
>
> > + calculate the temperature from the value stored in the VTM device.
> > +
> > + Temp = (-9.2627e-12) * x^4 + (6.0373e-08) * x^3 + \
> > + (-1.7058e-04) * x^2 + (3.2512e-01) * x + (-4.9003e+01)
> > +
> > properties:
> > compatible:
> > enum:
> > @@ -19,9 +37,16 @@ properties:
> > items:
> > - description: VTM cfg1 register space
> > - description: VTM cfg2 register space
> > - - description: VTM efuse register space
> > + - description: |
> > + A software trimming method must be applied to some Jacinto
> > + devices to function properly. This eFuse region provides
> > + the information needed for these SoCs to report
> > + temperatures accurately.
> >
> > power-domains:
> > + description: |
> > + Should contain the phandle to a power management (PM) domain
> > + node and the device-id of this device.
>
> This is quite generic - why adding it?
This was really a "while I'm here" addition. But there is no need, I can
drop this
Thanks again Krzysztof
~Bryan
On 12/10/2022 14:19, Bryan Brattlof wrote:
>>> + temperatures accurately.
>>>
>>> power-domains:
>>> + description: |
>>> + Should contain the phandle to a power management (PM) domain
>>> + node and the device-id of this device.
>>
>> This is quite generic - why adding it?
>
> This was really a "while I'm here" addition. But there is no need, I can
> drop this
Drop it, we do not describe generic properties (already described in
core schema).
Best regards,
Krzysztof