This series attempts to fix the issue with core register (Ex:- DBI) accesses
causing system hang issues in platforms where there is a dependency on the
availability of PCIe Reference clock from the host for their core
initialization.
This series is verified on Tegra194 & Tegra234 platforms.
Manivannan, could you please verify on qcom platforms?
V5:
* Addressed review comments from Bjorn
* Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late()
* Skipped memory allocation if done already. This is to avoid freeing and then
allocating again during PERST# toggles from the host.
V4:
* Addressed review comments from Bjorn and Manivannan
* Added .ep_init_late() ops
* Added patches to refactor code in qcom and tegra platforms
Vidya Sagar (3):
PCI: designware-ep: Fix DBI access before core init
PCI: qcom-ep: Refactor EP initialization completion
PCI: tegra194: Refactor EP initialization completion
.../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++-------
drivers/pci/controller/dwc/pcie-designware.h | 10 +-
drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++--
drivers/pci/controller/dwc/pcie-tegra194.c | 4 +-
4 files changed, 97 insertions(+), 69 deletions(-)
--
2.17.1
Call only dw_pcie_ep_init_notify() which internally takes care of calling
dw_pcie_ep_init_complete() to notify about the EP initialization
completion to the DWC EP framework.
Signed-off-by: Vidya Sagar <[email protected]>
---
V5:
* None
V4:
* New patch in this series
drivers/pci/controller/dwc/pcie-tegra194.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
index 1b6b437823d2..2600304522eb 100644
--- a/drivers/pci/controller/dwc/pcie-tegra194.c
+++ b/drivers/pci/controller/dwc/pcie-tegra194.c
@@ -1885,14 +1885,12 @@ static void pex_ep_event_pex_rst_deassert(struct tegra_pcie_dw *pcie)
val = (upper_32_bits(ep->msi_mem_phys) & MSIX_ADDR_MATCH_HIGH_OFF_MASK);
dw_pcie_writel_dbi(pci, MSIX_ADDR_MATCH_HIGH_OFF, val);
- ret = dw_pcie_ep_init_complete(ep);
+ ret = dw_pcie_ep_init_notify(ep);
if (ret) {
dev_err(dev, "Failed to complete initialization: %d\n", ret);
goto fail_init_complete;
}
- dw_pcie_ep_init_notify(ep);
-
/* Program the private control to allow sending LTR upstream */
if (pcie->of_data->has_ltr_req_fix) {
val = appl_readl(pcie, APPL_LTR_MSG_2);
--
2.17.1
Hi Vidya,
On Thu, Oct 13, 2022 at 11:27:09PM +0530, Vidya Sagar wrote:
> This series attempts to fix the issue with core register (Ex:- DBI) accesses
> causing system hang issues in platforms where there is a dependency on the
> availability of PCIe Reference clock from the host for their core
> initialization.
> This series is verified on Tegra194 & Tegra234 platforms.
>
> Manivannan, could you please verify on qcom platforms?
>
Currently I'm on paternity leave this week and next. Will test/review the latest
version once I'm back.
Thanks,
Mani
> V5:
> * Addressed review comments from Bjorn
> * Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late()
> * Skipped memory allocation if done already. This is to avoid freeing and then
> allocating again during PERST# toggles from the host.
>
> V4:
> * Addressed review comments from Bjorn and Manivannan
> * Added .ep_init_late() ops
> * Added patches to refactor code in qcom and tegra platforms
>
> Vidya Sagar (3):
> PCI: designware-ep: Fix DBI access before core init
> PCI: qcom-ep: Refactor EP initialization completion
> PCI: tegra194: Refactor EP initialization completion
>
> .../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++-------
> drivers/pci/controller/dwc/pcie-designware.h | 10 +-
> drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++--
> drivers/pci/controller/dwc/pcie-tegra194.c | 4 +-
> 4 files changed, 97 insertions(+), 69 deletions(-)
>
> --
> 2.17.1
>
--
மணிவண்ணன் சதாசிவம்
On Thu, Oct 13, 2022 at 11:27:09PM +0530, Vidya Sagar wrote:
> This series attempts to fix the issue with core register (Ex:- DBI) accesses
> causing system hang issues in platforms where there is a dependency on the
> availability of PCIe Reference clock from the host for their core
> initialization.
> This series is verified on Tegra194 & Tegra234 platforms.
>
> Manivannan, could you please verify on qcom platforms?
>
Vidya, any plan to respin this series? The EPC rework series is now merged for
v6.3.
Thanks,
Mani
> V5:
> * Addressed review comments from Bjorn
> * Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late()
> * Skipped memory allocation if done already. This is to avoid freeing and then
> allocating again during PERST# toggles from the host.
>
> V4:
> * Addressed review comments from Bjorn and Manivannan
> * Added .ep_init_late() ops
> * Added patches to refactor code in qcom and tegra platforms
>
> Vidya Sagar (3):
> PCI: designware-ep: Fix DBI access before core init
> PCI: qcom-ep: Refactor EP initialization completion
> PCI: tegra194: Refactor EP initialization completion
>
> .../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++-------
> drivers/pci/controller/dwc/pcie-designware.h | 10 +-
> drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++--
> drivers/pci/controller/dwc/pcie-tegra194.c | 4 +-
> 4 files changed, 97 insertions(+), 69 deletions(-)
>
> --
> 2.17.1
>
--
மணிவண்ணன் சதாசிவம்
On 2/14/2023 6:33 PM, Manivannan Sadhasivam wrote:
> External email: Use caution opening links or attachments
>
>
> On Thu, Oct 13, 2022 at 11:27:09PM +0530, Vidya Sagar wrote:
>> This series attempts to fix the issue with core register (Ex:- DBI) accesses
>> causing system hang issues in platforms where there is a dependency on the
>> availability of PCIe Reference clock from the host for their core
>> initialization.
>> This series is verified on Tegra194 & Tegra234 platforms.
>>
>> Manivannan, could you please verify on qcom platforms?
>>
>
> Vidya, any plan to respin this series? The EPC rework series is now merged for
> v6.3.
Yes. I'll send an updated series soon.
Currently, I'm observing some regression with linux-next on Tegra
platform for endpoint mode. I'll post the patches as soon as that is
resolved.
Thanks,
Vidya Sagar
>
> Thanks,
> Mani
>
>> V5:
>> * Addressed review comments from Bjorn
>> * Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late()
>> * Skipped memory allocation if done already. This is to avoid freeing and then
>> allocating again during PERST# toggles from the host.
>>
>> V4:
>> * Addressed review comments from Bjorn and Manivannan
>> * Added .ep_init_late() ops
>> * Added patches to refactor code in qcom and tegra platforms
>>
>> Vidya Sagar (3):
>> PCI: designware-ep: Fix DBI access before core init
>> PCI: qcom-ep: Refactor EP initialization completion
>> PCI: tegra194: Refactor EP initialization completion
>>
>> .../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++-------
>> drivers/pci/controller/dwc/pcie-designware.h | 10 +-
>> drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++--
>> drivers/pci/controller/dwc/pcie-tegra194.c | 4 +-
>> 4 files changed, 97 insertions(+), 69 deletions(-)
>>
>> --
>> 2.17.1
>>
>
> --
> மணிவண்ணன் சதாசிவம்
On Tue, Feb 14, 2023 at 07:27:54PM +0530, Vidya Sagar wrote:
>
>
> On 2/14/2023 6:33 PM, Manivannan Sadhasivam wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > On Thu, Oct 13, 2022 at 11:27:09PM +0530, Vidya Sagar wrote:
> > > This series attempts to fix the issue with core register (Ex:- DBI) accesses
> > > causing system hang issues in platforms where there is a dependency on the
> > > availability of PCIe Reference clock from the host for their core
> > > initialization.
> > > This series is verified on Tegra194 & Tegra234 platforms.
> > >
> > > Manivannan, could you please verify on qcom platforms?
> > >
> >
> > Vidya, any plan to respin this series? The EPC rework series is now merged for
> > v6.3.
>
> Yes. I'll send an updated series soon.
> Currently, I'm observing some regression with linux-next on Tegra platform
> for endpoint mode. I'll post the patches as soon as that is resolved.
>
Ping!
Thanks,
Mani
> Thanks,
> Vidya Sagar
>
> >
> > Thanks,
> > Mani
> >
> > > V5:
> > > * Addressed review comments from Bjorn
> > > * Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late()
> > > * Skipped memory allocation if done already. This is to avoid freeing and then
> > > allocating again during PERST# toggles from the host.
> > >
> > > V4:
> > > * Addressed review comments from Bjorn and Manivannan
> > > * Added .ep_init_late() ops
> > > * Added patches to refactor code in qcom and tegra platforms
> > >
> > > Vidya Sagar (3):
> > > PCI: designware-ep: Fix DBI access before core init
> > > PCI: qcom-ep: Refactor EP initialization completion
> > > PCI: tegra194: Refactor EP initialization completion
> > >
> > > .../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++-------
> > > drivers/pci/controller/dwc/pcie-designware.h | 10 +-
> > > drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++--
> > > drivers/pci/controller/dwc/pcie-tegra194.c | 4 +-
> > > 4 files changed, 97 insertions(+), 69 deletions(-)
> > >
> > > --
> > > 2.17.1
> > >
> >
> > --
> > மணிவண்ணன் சதாசிவம்
--
மணிவண்ணன் சதாசிவம்
On Tue, Mar 07, 2023 at 08:48:39PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Feb 14, 2023 at 07:27:54PM +0530, Vidya Sagar wrote:
> >
> >
> > On 2/14/2023 6:33 PM, Manivannan Sadhasivam wrote:
> > > External email: Use caution opening links or attachments
> > >
> > >
> > > On Thu, Oct 13, 2022 at 11:27:09PM +0530, Vidya Sagar wrote:
> > > > This series attempts to fix the issue with core register (Ex:- DBI) accesses
> > > > causing system hang issues in platforms where there is a dependency on the
> > > > availability of PCIe Reference clock from the host for their core
> > > > initialization.
> > > > This series is verified on Tegra194 & Tegra234 platforms.
> > > >
> > > > Manivannan, could you please verify on qcom platforms?
> > > >
> > >
> > > Vidya, any plan to respin this series? The EPC rework series is now merged for
> > > v6.3.
> >
> > Yes. I'll send an updated series soon.
> > Currently, I'm observing some regression with linux-next on Tegra platform
> > for endpoint mode. I'll post the patches as soon as that is resolved.
> >
>
> Ping!
>
Ping again.
- Mani
> Thanks,
> Mani
>
> > Thanks,
> > Vidya Sagar
> >
> > >
> > > Thanks,
> > > Mani
> > >
> > > > V5:
> > > > * Addressed review comments from Bjorn
> > > > * Changed dw_pcie_ep_init_complete() to dw_pcie_ep_init_late()
> > > > * Skipped memory allocation if done already. This is to avoid freeing and then
> > > > allocating again during PERST# toggles from the host.
> > > >
> > > > V4:
> > > > * Addressed review comments from Bjorn and Manivannan
> > > > * Added .ep_init_late() ops
> > > > * Added patches to refactor code in qcom and tegra platforms
> > > >
> > > > Vidya Sagar (3):
> > > > PCI: designware-ep: Fix DBI access before core init
> > > > PCI: qcom-ep: Refactor EP initialization completion
> > > > PCI: tegra194: Refactor EP initialization completion
> > > >
> > > > .../pci/controller/dwc/pcie-designware-ep.c | 125 +++++++++++-------
> > > > drivers/pci/controller/dwc/pcie-designware.h | 10 +-
> > > > drivers/pci/controller/dwc/pcie-qcom-ep.c | 27 ++--
> > > > drivers/pci/controller/dwc/pcie-tegra194.c | 4 +-
> > > > 4 files changed, 97 insertions(+), 69 deletions(-)
> > > >
> > > > --
> > > > 2.17.1
> > > >
> > >
> > > --
> > > மணிவண்ணன் சதாசிவம்
>
> --
> மணிவண்ணன் சதாசிவம்
--
மணிவண்ணன் சதாசிவம்