Riscv's implementation of init_of_cache_level() is following
the Devicetree Specification v0.3 regarding caches, cf.:
- s3.7.3 'Internal (L1) Cache Properties'
- s3.8 'Multi-level and Shared Cache Nodes'
Allow reusing the implementation by moving it.
Signed-off-by: Pierre Gondois <[email protected]>
---
arch/riscv/kernel/cacheinfo.c | 39 +------------------------------
drivers/base/cacheinfo.c | 44 +++++++++++++++++++++++++++++++++++
include/linux/cacheinfo.h | 1 +
3 files changed, 46 insertions(+), 38 deletions(-)
diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
index 90deabfe63ea..440a3df5944c 100644
--- a/arch/riscv/kernel/cacheinfo.c
+++ b/arch/riscv/kernel/cacheinfo.c
@@ -115,44 +115,7 @@ static void fill_cacheinfo(struct cacheinfo **this_leaf,
int init_cache_level(unsigned int cpu)
{
- struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
- struct device_node *np = of_cpu_device_node_get(cpu);
- struct device_node *prev = NULL;
- int levels = 0, leaves = 0, level;
-
- if (of_property_read_bool(np, "cache-size"))
- ++leaves;
- if (of_property_read_bool(np, "i-cache-size"))
- ++leaves;
- if (of_property_read_bool(np, "d-cache-size"))
- ++leaves;
- if (leaves > 0)
- levels = 1;
-
- prev = np;
- while ((np = of_find_next_cache_node(np))) {
- of_node_put(prev);
- prev = np;
- if (!of_device_is_compatible(np, "cache"))
- break;
- if (of_property_read_u32(np, "cache-level", &level))
- break;
- if (level <= levels)
- break;
- if (of_property_read_bool(np, "cache-size"))
- ++leaves;
- if (of_property_read_bool(np, "i-cache-size"))
- ++leaves;
- if (of_property_read_bool(np, "d-cache-size"))
- ++leaves;
- levels = level;
- }
-
- of_node_put(np);
- this_cpu_ci->num_levels = levels;
- this_cpu_ci->num_leaves = leaves;
-
- return 0;
+ return init_of_cache_level(cpu);
}
int populate_cache_leaves(unsigned int cpu)
diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
index 4b5cd08c5a65..a4308b48dd3e 100644
--- a/drivers/base/cacheinfo.c
+++ b/drivers/base/cacheinfo.c
@@ -224,8 +224,52 @@ static int cache_setup_of_node(unsigned int cpu)
return 0;
}
+
+int init_of_cache_level(unsigned int cpu)
+{
+ struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
+ struct device_node *np = of_cpu_device_node_get(cpu);
+ struct device_node *prev = NULL;
+ int levels = 0, leaves = 0, level;
+
+ if (of_property_read_bool(np, "cache-size"))
+ ++leaves;
+ if (of_property_read_bool(np, "i-cache-size"))
+ ++leaves;
+ if (of_property_read_bool(np, "d-cache-size"))
+ ++leaves;
+ if (leaves > 0)
+ levels = 1;
+
+ prev = np;
+ while ((np = of_find_next_cache_node(np))) {
+ of_node_put(prev);
+ prev = np;
+ if (!of_device_is_compatible(np, "cache"))
+ break;
+ if (of_property_read_u32(np, "cache-level", &level))
+ break;
+ if (level <= levels)
+ break;
+ if (of_property_read_bool(np, "cache-size"))
+ ++leaves;
+ if (of_property_read_bool(np, "i-cache-size"))
+ ++leaves;
+ if (of_property_read_bool(np, "d-cache-size"))
+ ++leaves;
+ levels = level;
+ }
+
+ of_node_put(np);
+ this_cpu_ci->num_levels = levels;
+ this_cpu_ci->num_leaves = leaves;
+
+ return 0;
+}
+
#else
static inline int cache_setup_of_node(unsigned int cpu) { return 0; }
+int init_of_cache_level(unsigned int cpu) { return 0; }
#endif
int __weak cache_setup_acpi(unsigned int cpu)
diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h
index 00b7a6ae8617..ff0328f3fbb0 100644
--- a/include/linux/cacheinfo.h
+++ b/include/linux/cacheinfo.h
@@ -80,6 +80,7 @@ struct cpu_cacheinfo {
struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu);
int init_cache_level(unsigned int cpu);
+int init_of_cache_level(unsigned int cpu);
int populate_cache_leaves(unsigned int cpu);
int cache_setup_acpi(unsigned int cpu);
bool last_level_cache_is_valid(unsigned int cpu);
--
2.25.1
On Tue, Nov 08, 2022 at 12:04:17PM +0100, Pierre Gondois wrote:
> Riscv's implementation of init_of_cache_level() is following
heh, "Riscv" always looks a bit odd!
Code movement looks fine, nothing surface level is broken on RISC-V.
Reviewed-by: Conor Dooley <[email protected]>
> the Devicetree Specification v0.3 regarding caches, cf.:
> - s3.7.3 'Internal (L1) Cache Properties'
> - s3.8 'Multi-level and Shared Cache Nodes'
>
> Allow reusing the implementation by moving it.
>
> Signed-off-by: Pierre Gondois <[email protected]>
> ---
> arch/riscv/kernel/cacheinfo.c | 39 +------------------------------
> drivers/base/cacheinfo.c | 44 +++++++++++++++++++++++++++++++++++
> include/linux/cacheinfo.h | 1 +
> 3 files changed, 46 insertions(+), 38 deletions(-)
>
> diff --git a/arch/riscv/kernel/cacheinfo.c b/arch/riscv/kernel/cacheinfo.c
> index 90deabfe63ea..440a3df5944c 100644
> --- a/arch/riscv/kernel/cacheinfo.c
> +++ b/arch/riscv/kernel/cacheinfo.c
> @@ -115,44 +115,7 @@ static void fill_cacheinfo(struct cacheinfo **this_leaf,
>
> int init_cache_level(unsigned int cpu)
> {
> - struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
> - struct device_node *np = of_cpu_device_node_get(cpu);
> - struct device_node *prev = NULL;
> - int levels = 0, leaves = 0, level;
> -
> - if (of_property_read_bool(np, "cache-size"))
> - ++leaves;
> - if (of_property_read_bool(np, "i-cache-size"))
> - ++leaves;
> - if (of_property_read_bool(np, "d-cache-size"))
> - ++leaves;
> - if (leaves > 0)
> - levels = 1;
> -
> - prev = np;
> - while ((np = of_find_next_cache_node(np))) {
> - of_node_put(prev);
> - prev = np;
> - if (!of_device_is_compatible(np, "cache"))
> - break;
> - if (of_property_read_u32(np, "cache-level", &level))
> - break;
> - if (level <= levels)
> - break;
> - if (of_property_read_bool(np, "cache-size"))
> - ++leaves;
> - if (of_property_read_bool(np, "i-cache-size"))
> - ++leaves;
> - if (of_property_read_bool(np, "d-cache-size"))
> - ++leaves;
> - levels = level;
> - }
> -
> - of_node_put(np);
> - this_cpu_ci->num_levels = levels;
> - this_cpu_ci->num_leaves = leaves;
> -
> - return 0;
> + return init_of_cache_level(cpu);
> }
>
> int populate_cache_leaves(unsigned int cpu)
> diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c
> index 4b5cd08c5a65..a4308b48dd3e 100644
> --- a/drivers/base/cacheinfo.c
> +++ b/drivers/base/cacheinfo.c
> @@ -224,8 +224,52 @@ static int cache_setup_of_node(unsigned int cpu)
>
> return 0;
> }
> +
> +int init_of_cache_level(unsigned int cpu)
> +{
> + struct cpu_cacheinfo *this_cpu_ci = get_cpu_cacheinfo(cpu);
> + struct device_node *np = of_cpu_device_node_get(cpu);
> + struct device_node *prev = NULL;
> + int levels = 0, leaves = 0, level;
> +
> + if (of_property_read_bool(np, "cache-size"))
> + ++leaves;
> + if (of_property_read_bool(np, "i-cache-size"))
> + ++leaves;
> + if (of_property_read_bool(np, "d-cache-size"))
> + ++leaves;
> + if (leaves > 0)
> + levels = 1;
> +
> + prev = np;
> + while ((np = of_find_next_cache_node(np))) {
> + of_node_put(prev);
> + prev = np;
> + if (!of_device_is_compatible(np, "cache"))
> + break;
> + if (of_property_read_u32(np, "cache-level", &level))
> + break;
> + if (level <= levels)
> + break;
> + if (of_property_read_bool(np, "cache-size"))
> + ++leaves;
> + if (of_property_read_bool(np, "i-cache-size"))
> + ++leaves;
> + if (of_property_read_bool(np, "d-cache-size"))
> + ++leaves;
> + levels = level;
> + }
> +
> + of_node_put(np);
> + this_cpu_ci->num_levels = levels;
> + this_cpu_ci->num_leaves = leaves;
> +
> + return 0;
> +}
> +
> #else
> static inline int cache_setup_of_node(unsigned int cpu) { return 0; }
> +int init_of_cache_level(unsigned int cpu) { return 0; }
> #endif
>
> int __weak cache_setup_acpi(unsigned int cpu)
> diff --git a/include/linux/cacheinfo.h b/include/linux/cacheinfo.h
> index 00b7a6ae8617..ff0328f3fbb0 100644
> --- a/include/linux/cacheinfo.h
> +++ b/include/linux/cacheinfo.h
> @@ -80,6 +80,7 @@ struct cpu_cacheinfo {
>
> struct cpu_cacheinfo *get_cpu_cacheinfo(unsigned int cpu);
> int init_cache_level(unsigned int cpu);
> +int init_of_cache_level(unsigned int cpu);
> int populate_cache_leaves(unsigned int cpu);
> int cache_setup_acpi(unsigned int cpu);
> bool last_level_cache_is_valid(unsigned int cpu);
> --
> 2.25.1
>
On Tue, Nov 08, 2022 at 02:07:41PM +0000, Conor Dooley wrote:
> On Tue, Nov 08, 2022 at 12:04:17PM +0100, Pierre Gondois wrote:
> > Riscv's implementation of init_of_cache_level() is following
>
> heh, "Riscv" always looks a bit odd!
> Code movement looks fine, nothing surface level is broken on RISC-V.
> Reviewed-by: Conor Dooley <[email protected]>
>
Thanks for the review and testing. I was planning to ask Pierre to cc you
next time but you seem to have covered that for me :).
--
Regards,
Sudeep
On Tue, Nov 08, 2022 at 12:04:17PM +0100, Pierre Gondois wrote:
> Riscv's implementation of init_of_cache_level() is following
> the Devicetree Specification v0.3 regarding caches, cf.:
> - s3.7.3 'Internal (L1) Cache Properties'
> - s3.8 'Multi-level and Shared Cache Nodes'
>
> Allow reusing the implementation by moving it.
>
Reviewed-by: Sudeep Holla <[email protected]>
--
Regards,
Sudeep
On Tue, Nov 08, 2022 at 04:03:23PM +0000, Sudeep Holla wrote:
> On Tue, Nov 08, 2022 at 12:04:17PM +0100, Pierre Gondois wrote:
> > Riscv's implementation of init_of_cache_level() is following
> > the Devicetree Specification v0.3 regarding caches, cf.:
> > - s3.7.3 'Internal (L1) Cache Properties'
> > - s3.8 'Multi-level and Shared Cache Nodes'
> >
> > Allow reusing the implementation by moving it.
> >
>
> Reviewed-by: Sudeep Holla <[email protected]>
>
Forgot to mention earlier, I prefer to
s/riscv/RISC-V/
s/implem/implementation/
--
Regards,
Sudeep
On Tue, Nov 08, 2022 at 03:59:06PM +0000, Sudeep Holla wrote:
> On Tue, Nov 08, 2022 at 02:07:41PM +0000, Conor Dooley wrote:
> > On Tue, Nov 08, 2022 at 12:04:17PM +0100, Pierre Gondois wrote:
> > > Riscv's implementation of init_of_cache_level() is following
> >
> > heh, "Riscv" always looks a bit odd!
> > Code movement looks fine, nothing surface level is broken on RISC-V.
> > Reviewed-by: Conor Dooley <[email protected]>
> >
> Thanks for the review and testing. I was planning to ask Pierre to cc you
> next time but you seem to have covered that for me :).
Ye no worries.
Feel free to add some sort of "R: Conor Dooley <[email protected]>" entry
where appropriate if you want to make sure I'll take a look - but I
should see it anyway if it goes to the riscv list.
Up to you.