The following series of patches add support for the following
on J721S2 common processor board,
- USB
- SerDes
- OSPI
- PCIe
Changes from v1:
* Resolve issues with dt schema reporting
* Minor changes related to consistency on node naming and value
Changes from v2:
* Added PCIe RC + EP enablement patchsets
* Added device-id for j722s2 PCIe host in dt documentation
* Reworked SERDES + WIZ enablement patchset to use properies for clocks
defines versus entire devicetree nodes. Results in cleaner code that
doesn't break dt-schema or the driver functionality.
Changes from v3:
* Rebased changes on top of '[PATCH 00/12] TI J7x Disable Incomplete DT Nodes'
* Removed "dt-bindings: PCI: Add host mode device-id for j721s2 platform" patch and
send it own series to avoid a dependency that would hold up other patches in this
series
Changes from v4:
* Add my Signed-off-by lines to all patchsets
Changes from v5:
* Removed Cc from commit messages to reduce clutter
* Squashed changes for device tree nodes that get modified latter in the patchset
series
Aswath Govindraju (7):
arm64: dts: ti: k3-j721s2-main: Add support for USB
arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI
arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0
arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support
arm64: dts: ti: k3-j721s2: Add support for OSPI Flashes
arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node
arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe
Matt Ranostay (1):
arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node
.../dts/ti/k3-j721s2-common-proc-board.dts | 92 ++++++++++
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 157 ++++++++++++++++++
.../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 40 +++++
arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 42 +++++
4 files changed, 331 insertions(+)
--
2.38.GIT
From: Aswath Govindraju <[email protected]>
x1 lane PCIe slot in the common processor board is enabled and connected to
J721S2 SOM. Add PCIe DT node in common processor board to reflect the
same.
Reviewed-by: Siddharth Vadapalli <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Vignesh Raghavendra <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
---
.../boot/dts/ti/k3-j721s2-common-proc-board.dts | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index 0503e690cfaf..862611784ab3 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -374,6 +374,20 @@ flash@0{
};
};
+&pcie1_rc {
+ reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+};
+
+&pcie1_ep {
+ phys = <&serdes0_pcie_link>;
+ phy-names = "pcie-phy";
+ num-lanes = <1>;
+ status = "disabled";
+};
+
&mcu_mcan0 {
status = "okay";
pinctrl-names = "default";
--
2.38.GIT
From: Aswath Govindraju <[email protected]>
Add support for single instance of USB 3.0 controller in J721S2 SoC.
Reviewed-by: Ravi Gunasekaran <[email protected]>
Signed-off-by: Aswath Govindraju <[email protected]>
Signed-off-by: Matt Ranostay <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 42 ++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index 8915132efcc1..b4869bff4f22 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -26,6 +26,20 @@ l3cache-sram@200000 {
};
};
+ scm_conf: syscon@104000 {
+ compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+ reg = <0x00 0x00104000 0x00 0x18000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x00104000 0x18000>;
+
+ usb_serdes_mux: mux-controller-0 {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
+ };
+ };
+
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
@@ -745,6 +759,34 @@ cpts@310d0000 {
};
};
+ usbss0: cdns-usb@4104000 {
+ compatible = "ti,j721e-usb";
+ reg = <0x00 0x04104000 0x00 0x100>;
+ clocks = <&k3_clks 360 16>, <&k3_clks 360 15>;
+ clock-names = "ref", "lpm";
+ assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
+ assigned-clock-parents = <&k3_clks 360 17>;
+ power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-coherent;
+
+ usb0: usb@6000000 {
+ compatible = "cdns,usb3";
+ reg = <0x00 0x06000000 0x00 0x10000>,
+ <0x00 0x06010000 0x00 0x10000>,
+ <0x00 0x06020000 0x00 0x10000>;
+ reg-names = "otg", "xhci", "dev";
+ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host", "peripheral", "otg";
+ maximum-speed = "super-speed";
+ dr_mode = "otg";
+ };
+ };
+
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,
--
2.38.GIT
Add dt node for the single instance of WIZ (SERDES wrapper) and
SERDES module shared by PCIe, eDP and USB.
Signed-off-by: Matt Ranostay <[email protected]>
---
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 54 ++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index b4869bff4f22..adbb172658b9 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -5,6 +5,17 @@
* Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include <dt-bindings/phy/phy-cadence.h>
+#include <dt-bindings/phy/phy-ti.h>
+
+/ {
+ serdes_refclk: clock-cmnrefclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ clock-frequency = <0>;
+ };
+};
+
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
@@ -38,6 +49,13 @@ usb_serdes_mux: mux-controller-0 {
#mux-control-cells = <1>;
mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
};
+
+ serdes_ln_ctrl: mux-controller-80 {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
+ <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
+ };
};
gic500: interrupt-controller@1800000 {
@@ -787,6 +805,42 @@ usb0: usb@6000000 {
};
};
+ serdes_wiz0: wiz@5060000 {
+ compatible = "ti,am64-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "ext_ref_clk";
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x5060000 0x0 0x5060000 0x10000>;
+
+ assigned-clocks = <&k3_clks 365 3>;
+ assigned-clock-parents = <&k3_clks 365 7>;
+
+ serdes0: serdes@5060000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05060000 0x00010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 365 3>,
+ <&k3_clks 365 3>,
+ <&k3_clks 365 3>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+ };
+ };
+
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,
--
2.38.GIT
On 19/11/2022 06:08, Matt Ranostay wrote:
> The following series of patches add support for the following
> on J721S2 common processor board,
>
> - USB
> - SerDes
> - OSPI
> - PCIe
>
> Changes from v1:
> * Resolve issues with dt schema reporting
> * Minor changes related to consistency on node naming and value
>
> Changes from v2:
> * Added PCIe RC + EP enablement patchsets
> * Added device-id for j722s2 PCIe host in dt documentation
> * Reworked SERDES + WIZ enablement patchset to use properies for clocks
> defines versus entire devicetree nodes. Results in cleaner code that
> doesn't break dt-schema or the driver functionality.
>
> Changes from v3:
> * Rebased changes on top of '[PATCH 00/12] TI J7x Disable Incomplete DT Nodes'
> * Removed "dt-bindings: PCI: Add host mode device-id for j721s2 platform" patch and
> send it own series to avoid a dependency that would hold up other patches in this
> series
>
> Changes from v4:
> * Add my Signed-off-by lines to all patchsets
>
> Changes from v5:
> * Removed Cc from commit messages to reduce clutter
> * Squashed changes for device tree nodes that get modified latter in the patchset
> series
>
> Aswath Govindraju (7):
> arm64: dts: ti: k3-j721s2-main: Add support for USB
> arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI
> arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0
> arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support
> arm64: dts: ti: k3-j721s2: Add support for OSPI Flashes
> arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node
> arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe
>
> Matt Ranostay (1):
> arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node
>
> .../dts/ti/k3-j721s2-common-proc-board.dts | 92 ++++++++++
> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 157 ++++++++++++++++++
> .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 40 +++++
> arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 42 +++++
> 4 files changed, 331 insertions(+)
>
Reviewed-by: Roger Quadros <[email protected]>
--
cheers,
-roger
On 19/11/22 9:39 am, Matt Ranostay wrote:
> Add dt node for the single instance of WIZ (SERDES wrapper) and
> SERDES module shared by PCIe, eDP and USB.
>
> Signed-off-by: Matt Ranostay <[email protected]>
> ---
> arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 54 ++++++++++++++++++++++
> 1 file changed, 54 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index b4869bff4f22..adbb172658b9 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -5,6 +5,17 @@
> * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
> */
>
> +#include <dt-bindings/phy/phy-cadence.h>
> +#include <dt-bindings/phy/phy-ti.h>
> +
> +/ {
> + serdes_refclk: clock-cmnrefclk {
> + #clock-cells = <0>;
> + compatible = "fixed-clock";
> + clock-frequency = <0>;
> + };
> +};
> +
> &cbass_main {
> msmc_ram: sram@70000000 {
> compatible = "mmio-sram";
> @@ -38,6 +49,13 @@ usb_serdes_mux: mux-controller-0 {
> #mux-control-cells = <1>;
> mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
> };
> +
> + serdes_ln_ctrl: mux-controller-80 {
> + compatible = "mmio-mux";
> + #mux-control-cells = <1>;
> + mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
> + <0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
> + };
> };
>
> gic500: interrupt-controller@1800000 {
> @@ -787,6 +805,42 @@ usb0: usb@6000000 {
> };
> };
>
> + serdes_wiz0: wiz@5060000 {
> + compatible = "ti,am64-wiz-10g";
Using compatible "ti,am64-wiz-10g" may cause issues as the wiz_data->type plays a role in serdes configuration
Please relook into this
> + #address-cells = <1>;
> + #size-cells = <1>;
> + power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
> + clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
> + clock-names = "fck", "core_ref_clk", "ext_ref_clk";
> + num-lanes = <4>;
> + #reset-cells = <1>;
> + #clock-cells = <1>;
> + ranges = <0x5060000 0x0 0x5060000 0x10000>;
> +
> + assigned-clocks = <&k3_clks 365 3>;
> + assigned-clock-parents = <&k3_clks 365 7>;
> +
> + serdes0: serdes@5060000 {
> + compatible = "ti,j721e-serdes-10g";
> + reg = <0x05060000 0x00010000>;
> + reg-names = "torrent_phy";
> + resets = <&serdes_wiz0 0>;
> + reset-names = "torrent_reset";
> + clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
> + clock-names = "refclk", "phy_en_refclk";
> + assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
> + <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
> + <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
> + assigned-clock-parents = <&k3_clks 365 3>,
> + <&k3_clks 365 3>,
> + <&k3_clks 365 3>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #clock-cells = <1>;
> + };
> + };
> +
> main_mcan0: can@2701000 {
> compatible = "bosch,m_can";
> reg = <0x00 0x02701000 0x00 0x200>,
--
Regards,
Ravi