This series improves the RISC-V timer driver to set CLOCK_EVT_FEAT_C3STOP
feature based on RISC-V platform capabilities.
These patches can also be found in riscv_timer_dt_imp_v3 branch at:
https://github.com/avpatel/linux.git
Changes since v2:
- Include Conor's revert patch as the first patch and rebased other patches
- Update PATCH2 to document bindings for separate RISC-V timer DT node
- Update PATCH3 based on RISC-V timer DT node bindings
Changes since v1:
- Rebased on Linux-5.19-rc8
- Renamed "riscv,always-on" DT property to "riscv,timer-can-wake-cpu"
Anup Patel (2):
dt-bindings: timer: Add bindings for the RISC-V timer device
clocksource: timer-riscv: Set CLOCK_EVT_FEAT_C3STOP based on DT
Conor Dooley (1):
Revert "clocksource/drivers/riscv: Events are stopped during CPU
suspend"
.../bindings/timer/riscv,timer.yaml | 52 +++++++++++++++++++
drivers/clocksource/timer-riscv.c | 12 ++++-
2 files changed, 63 insertions(+), 1 deletion(-)
create mode 100644 Documentation/devicetree/bindings/timer/riscv,timer.yaml
--
2.34.1
We should set CLOCK_EVT_FEAT_C3STOP for a clock_event_device only
when riscv,timer-cant-wake-up DT property is present in the RISC-V
timer DT node.
This way CLOCK_EVT_FEAT_C3STOP feature is set for clock_event_device
based on RISC-V platform capabilities rather than having it set for
all RISC-V platforms.
Signed-off-by: Anup Patel <[email protected]>
---
drivers/clocksource/timer-riscv.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index a0d66fabf073..0c8bdd168a45 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -28,6 +28,7 @@
#include <asm/timex.h>
static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
+static bool riscv_timer_cant_wake_cpu;
static int riscv_clock_next_event(unsigned long delta,
struct clock_event_device *ce)
@@ -85,6 +86,8 @@ static int riscv_timer_starting_cpu(unsigned int cpu)
ce->cpumask = cpumask_of(cpu);
ce->irq = riscv_clock_event_irq;
+ if (riscv_timer_cant_wake_cpu)
+ ce->features |= CLOCK_EVT_FEAT_C3STOP;
clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
enable_percpu_irq(riscv_clock_event_irq,
@@ -139,6 +142,13 @@ static int __init riscv_timer_init_dt(struct device_node *n)
if (cpuid != smp_processor_id())
return 0;
+ child = of_find_compatible_node(NULL, NULL, "riscv,timer");
+ if (child) {
+ riscv_timer_cant_wake_cpu = of_property_read_bool(child,
+ "riscv,timer-cant-wake-cpu");
+ of_node_put(child);
+ }
+
domain = NULL;
child = of_get_compatible_child(n, "riscv,cpu-intc");
if (!child) {
--
2.34.1
From: Conor Dooley <[email protected]>
This reverts commit 232ccac1bd9b5bfe73895f527c08623e7fa0752d.
On the subject of suspend, the RISC-V SBI spec states:
> Request the SBI implementation to put the calling hart in a platform
> specific suspend (or low power) state specified by the suspend_type
> parameter. The hart will automatically come out of suspended state and
> resume normal execution when it receives an interrupt or platform
> specific hardware event.
This does not cover whether any given events actually reach the hart or
not, just what the hart will do if it receives an event. On PolarFire
SoC, and potentially other SiFive based implementations, events from the
RISC-V timer do reach a hart during suspend. This is not the case for
the implementation on the Allwinner D1 - there timer events are not
received during suspend.
To fix this, the C3STOP feature was enabled for the timer driver -
but this has broken both RCU stall detection and timers generally on
PolarFire SoC (and potentially other SiFive based implementations).
If an AXI read to the PCIe controller on PolarFire SoC times out, the
system will stall, however, with this patch applied, the system just
locks up without RCU stalling:
io scheduler mq-deadline registered
io scheduler kyber registered
microchip-pcie 2000000000.pcie: host bridge /soc/pcie@2000000000 ranges:
microchip-pcie 2000000000.pcie: MEM 0x2008000000..0x2087ffffff -> 0x0008000000
microchip-pcie 2000000000.pcie: sec error in pcie2axi buffer
microchip-pcie 2000000000.pcie: ded error in pcie2axi buffer
microchip-pcie 2000000000.pcie: axi read request error
microchip-pcie 2000000000.pcie: axi read timeout
microchip-pcie 2000000000.pcie: sec error in pcie2axi buffer
microchip-pcie 2000000000.pcie: ded error in pcie2axi buffer
microchip-pcie 2000000000.pcie: sec error in pcie2axi buffer
microchip-pcie 2000000000.pcie: ded error in pcie2axi buffer
microchip-pcie 2000000000.pcie: sec error in pcie2axi buffer
microchip-pcie 2000000000.pcie: ded error in pcie2axi buffer
Freeing initrd memory: 7332K
Similarly issues were reported with clock_nanosleep() - with a test app
that sleeps each cpu for 6, 5, 4, 3 ms respectively, HZ=250 & the blamed
commit in place, the sleep times are rounded up to the next jiffy:
== CPU: 1 == == CPU: 2 == == CPU: 3 == == CPU: 4 ==
Mean: 7.974992 Mean: 7.976534 Mean: 7.962591 Mean: 3.952179
Std Dev: 0.154374 Std Dev: 0.156082 Std Dev: 0.171018 Std Dev: 0.076193
Hi: 9.472000 Hi: 10.495000 Hi: 8.864000 Hi: 4.736000
Lo: 6.087000 Lo: 6.380000 Lo: 4.872000 Lo: 3.403000
Samples: 521 Samples: 521 Samples: 521 Samples: 521
Fortunately, the D1 has a second timer, which is "currently used in
preference to the RISC-V/SBI timer driver" so a revert here does not
hurt operation of D1 in its current form.
Ultimately, a DeviceTree property (or node) will be added to encode the
behaviour of the timers, but until then revert the addition of
CLOCK_EVT_FEAT_C3STOP.
Link: https://lore.kernel.org/linux-riscv/YzYTNQRxLr7Q9JR0@spud/
Link: https://github.com/riscv-non-isa/riscv-sbi-doc/issues/98/
Link: https://lore.kernel.org/linux-riscv/[email protected]/
Fixes: 232ccac1bd9b ("clocksource/drivers/riscv: Events are stopped during CPU suspend")
CC: Samuel Holland <[email protected]>
CC: Anup Patel <[email protected]>
CC: Palmer Dabbelt <[email protected]>
Reviewed-by: Palmer Dabbelt <[email protected]>
Acked-by: Palmer Dabbelt <[email protected]>
Acked-by: Samuel Holland <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
Signed-off-by: Anup Patel <[email protected]>
---
drivers/clocksource/timer-riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
index 969a552da8d2..a0d66fabf073 100644
--- a/drivers/clocksource/timer-riscv.c
+++ b/drivers/clocksource/timer-riscv.c
@@ -51,7 +51,7 @@ static int riscv_clock_next_event(unsigned long delta,
static unsigned int riscv_clock_event_irq;
static DEFINE_PER_CPU(struct clock_event_device, riscv_clock_event) = {
.name = "riscv_timer_clockevent",
- .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_C3STOP,
+ .features = CLOCK_EVT_FEAT_ONESHOT,
.rating = 100,
.set_next_event = riscv_clock_next_event,
};
--
2.34.1
We add DT bindings for a separate RISC-V timer DT node which can
be used to describe implementation specific behaviour (such as
timer interrupt not triggered during non-retentive suspend).
Signed-off-by: Anup Patel <[email protected]>
---
.../bindings/timer/riscv,timer.yaml | 52 +++++++++++++++++++
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/timer/riscv,timer.yaml
diff --git a/Documentation/devicetree/bindings/timer/riscv,timer.yaml b/Documentation/devicetree/bindings/timer/riscv,timer.yaml
new file mode 100644
index 000000000000..cf53dfff90bc
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/riscv,timer.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/riscv,timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V timer
+
+maintainers:
+ - Anup Patel <[email protected]>
+
+description: |+
+ RISC-V platforms always have a RISC-V timer device for the supervisor-mode
+ based on the time CSR defined by the RISC-V privileged specification. The
+ timer interrupts of this device are configured using the RISC-V SBI Time
+ extension or the RISC-V Sstc extension.
+
+ The clock frequency of RISC-V timer device is specified via the
+ "timebase-frequency" DT property of "/cpus" DT node which is described
+ in Documentation/devicetree/bindings/riscv/cpus.yaml
+
+properties:
+ compatible:
+ enum:
+ - riscv,timer
+
+ interrupts-extended:
+ minItems: 1
+ maxItems: 4096 # Should be enough?
+
+ riscv,timer-cant-wake-cpu:
+ type: boolean
+ description:
+ If present, the timer interrupt can't wake up the CPU from
+ suspend/idle state.
+
+additionalProperties: false
+
+required:
+ - compatible
+ - interrupts-extended
+
+examples:
+ - |
+ timer {
+ compatible = "riscv,timer";
+ interrupts-extended = <&cpu1intc 5>,
+ <&cpu2intc 5>,
+ <&cpu3intc 5>,
+ <&cpu4intc 5>;
+ };
+...
--
2.34.1
Hey Anup,
For the future, could you please CC me on all patches in a series that I
have previously reviewed?
On Fri, Nov 25, 2022 at 04:51:04PM +0530, Anup Patel wrote:
> We add DT bindings for a separate RISC-V timer DT node which can
> be used to describe implementation specific behaviour (such as
> timer interrupt not triggered during non-retentive suspend).
>
> Signed-off-by: Anup Patel <[email protected]>
> ---
> .../bindings/timer/riscv,timer.yaml | 52 +++++++++++++++++++
> 1 file changed, 52 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/timer/riscv,timer.yaml
>
> diff --git a/Documentation/devicetree/bindings/timer/riscv,timer.yaml b/Documentation/devicetree/bindings/timer/riscv,timer.yaml
> new file mode 100644
> index 000000000000..cf53dfff90bc
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/timer/riscv,timer.yaml
> @@ -0,0 +1,52 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/timer/riscv,timer.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: RISC-V timer
> +
> +maintainers:
> + - Anup Patel <[email protected]>
> +
> +description: |+
> + RISC-V platforms always have a RISC-V timer device for the supervisor-mode
> + based on the time CSR defined by the RISC-V privileged specification. The
> + timer interrupts of this device are configured using the RISC-V SBI Time
> + extension or the RISC-V Sstc extension.
> +
> + The clock frequency of RISC-V timer device is specified via the
> + "timebase-frequency" DT property of "/cpus" DT node which is described
> + in Documentation/devicetree/bindings/riscv/cpus.yaml
> +
> +properties:
> + compatible:
> + enum:
> + - riscv,timer
> +
> + interrupts-extended:
> + minItems: 1
> + maxItems: 4096 # Should be enough?
> +
> + riscv,timer-cant-wake-cpu:
> + type: boolean
> + description:
> + If present, the timer interrupt can't wake up the CPU from
> + suspend/idle state.
I'm really not sure about this... I would be inclined to think that if
someone does not specify then we should assume that they took the
scroogiest view of the spec and so do not get events during suspend.
I suppose you could then argue that their DT is wrong & it's their fault
though. Plus the existing platforms behave this way & we avoid having to
retrofit stuff here.
> +
> +additionalProperties: false
> +
> +required:
> + - compatible
> + - interrupts-extended
> +
> +examples:
> + - |
> + timer {
> + compatible = "riscv,timer";
> + interrupts-extended = <&cpu1intc 5>,
> + <&cpu2intc 5>,
> + <&cpu3intc 5>,
> + <&cpu4intc 5>;
> + };
> +...
> --
> 2.34.1
>
On Fri, Nov 25, 2022 at 04:51:05PM +0530, Anup Patel wrote:
> We should set CLOCK_EVT_FEAT_C3STOP for a clock_event_device only
> when riscv,timer-cant-wake-up DT property is present in the RISC-V
> timer DT node.
>
> This way CLOCK_EVT_FEAT_C3STOP feature is set for clock_event_device
> based on RISC-V platform capabilities rather than having it set for
> all RISC-V platforms.
I need to go do some testing on what setting the C3STOP flag does on
platforms other than PolarFire SoC. I'm not sure that we should be
enabling this flag *at all* until we know that it does not break on
other platforms too.
Hopefully I'll get to it tonight or tomorrow..
> Signed-off-by: Anup Patel <[email protected]>
> ---
> drivers/clocksource/timer-riscv.c | 10 ++++++++++
> 1 file changed, 10 insertions(+)
>
> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> index a0d66fabf073..0c8bdd168a45 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -28,6 +28,7 @@
> #include <asm/timex.h>
>
> static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
> +static bool riscv_timer_cant_wake_cpu;
>
> static int riscv_clock_next_event(unsigned long delta,
> struct clock_event_device *ce)
> @@ -85,6 +86,8 @@ static int riscv_timer_starting_cpu(unsigned int cpu)
>
> ce->cpumask = cpumask_of(cpu);
> ce->irq = riscv_clock_event_irq;
> + if (riscv_timer_cant_wake_cpu)
> + ce->features |= CLOCK_EVT_FEAT_C3STOP;
> clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
>
> enable_percpu_irq(riscv_clock_event_irq,
> @@ -139,6 +142,13 @@ static int __init riscv_timer_init_dt(struct device_node *n)
> if (cpuid != smp_processor_id())
> return 0;
>
> + child = of_find_compatible_node(NULL, NULL, "riscv,timer");
> + if (child) {
> + riscv_timer_cant_wake_cpu = of_property_read_bool(child,
> + "riscv,timer-cant-wake-cpu");
> + of_node_put(child);
> + }
> +
> domain = NULL;
> child = of_get_compatible_child(n, "riscv,cpu-intc");
> if (!child) {
> --
> 2.34.1
>
On Fri, Nov 25, 2022 at 6:40 PM Conor Dooley <[email protected]> wrote:
>
> Hey Anup,
>
> For the future, could you please CC me on all patches in a series that I
> have previously reviewed?
Okay.
>
> On Fri, Nov 25, 2022 at 04:51:04PM +0530, Anup Patel wrote:
> > We add DT bindings for a separate RISC-V timer DT node which can
> > be used to describe implementation specific behaviour (such as
> > timer interrupt not triggered during non-retentive suspend).
> >
> > Signed-off-by: Anup Patel <[email protected]>
> > ---
> > .../bindings/timer/riscv,timer.yaml | 52 +++++++++++++++++++
> > 1 file changed, 52 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/timer/riscv,timer.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/timer/riscv,timer.yaml b/Documentation/devicetree/bindings/timer/riscv,timer.yaml
> > new file mode 100644
> > index 000000000000..cf53dfff90bc
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/timer/riscv,timer.yaml
> > @@ -0,0 +1,52 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/timer/riscv,timer.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: RISC-V timer
> > +
> > +maintainers:
> > + - Anup Patel <[email protected]>
> > +
> > +description: |+
> > + RISC-V platforms always have a RISC-V timer device for the supervisor-mode
> > + based on the time CSR defined by the RISC-V privileged specification. The
> > + timer interrupts of this device are configured using the RISC-V SBI Time
> > + extension or the RISC-V Sstc extension.
> > +
> > + The clock frequency of RISC-V timer device is specified via the
> > + "timebase-frequency" DT property of "/cpus" DT node which is described
> > + in Documentation/devicetree/bindings/riscv/cpus.yaml
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - riscv,timer
> > +
> > + interrupts-extended:
> > + minItems: 1
> > + maxItems: 4096 # Should be enough?
> > +
> > + riscv,timer-cant-wake-cpu:
> > + type: boolean
> > + description:
> > + If present, the timer interrupt can't wake up the CPU from
> > + suspend/idle state.
>
> I'm really not sure about this... I would be inclined to think that if
> someone does not specify then we should assume that they took the
> scroogiest view of the spec and so do not get events during suspend.
>
> I suppose you could then argue that their DT is wrong & it's their fault
> though. Plus the existing platforms behave this way & we avoid having to
> retrofit stuff here.
Yes, the DT property is defined to keep things working for
existing platforms.
IMO, people should always read the DT bindings document at time of
creating DT for their platform. If there are queries then they can always
shoot email to the maintainers on LKML.
>
> > +
> > +additionalProperties: false
> > +
> > +required:
> > + - compatible
> > + - interrupts-extended
> > +
> > +examples:
> > + - |
> > + timer {
> > + compatible = "riscv,timer";
> > + interrupts-extended = <&cpu1intc 5>,
> > + <&cpu2intc 5>,
> > + <&cpu3intc 5>,
> > + <&cpu4intc 5>;
> > + };
> > +...
> > --
> > 2.34.1
> >
Regards,
Anup
On Fri, Nov 25, 2022 at 01:13:04PM +0000, Conor Dooley wrote:
> On Fri, Nov 25, 2022 at 04:51:05PM +0530, Anup Patel wrote:
> > We should set CLOCK_EVT_FEAT_C3STOP for a clock_event_device only
> > when riscv,timer-cant-wake-up DT property is present in the RISC-V
> > timer DT node.
> >
> > This way CLOCK_EVT_FEAT_C3STOP feature is set for clock_event_device
> > based on RISC-V platform capabilities rather than having it set for
> > all RISC-V platforms.
>
> I need to go do some testing on what setting the C3STOP flag does on
> platforms other than PolarFire SoC. I'm not sure that we should be
> enabling this flag *at all* until we know that it does not break on
> other platforms too.
I tried my fu540 & fu740 - both of those seem to exhibit broken timer
behaviour with C3STOP set. Ethernet doesn't work upstream on the
VisionFive, so I didn't go through the hassle of testing that - but I
would imagine it is the same as the fu740. Whenever I get a VisionFive 2
I'll give that a try too.
I did try the D1 (thanks for fielding my dumb questions Samuel) but I
was not able to get the thing to boot if I disabled the sunxi timer :/
Ethernet would not come up in U-Boot, clearly I did something not
right..
Obviously we need to fix things & get it backported etc, so taking a
pragmatic approach: I think that it is better to merge this stuff even
though it there's a pretty good chance I think that it'll break the
SBI timer on a D1, since it is not intended that it will be used.
It does make me worried about some of the other platforms though, like
that Bouffalolabs SoC that Jisheng sent in a DT for. It's also using
thead stuff so I wonder if it needs C3STOP too. I've added Jisheng to
CC :)
> > Signed-off-by: Anup Patel <[email protected]>
> > ---
> > drivers/clocksource/timer-riscv.c | 10 ++++++++++
> > 1 file changed, 10 insertions(+)
> >
> > diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> > index a0d66fabf073..0c8bdd168a45 100644
> > --- a/drivers/clocksource/timer-riscv.c
> > +++ b/drivers/clocksource/timer-riscv.c
> > @@ -28,6 +28,7 @@
> > #include <asm/timex.h>
> >
> > static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
> > +static bool riscv_timer_cant_wake_cpu;
> >
> > static int riscv_clock_next_event(unsigned long delta,
> > struct clock_event_device *ce)
> > @@ -85,6 +86,8 @@ static int riscv_timer_starting_cpu(unsigned int cpu)
> >
> > ce->cpumask = cpumask_of(cpu);
> > ce->irq = riscv_clock_event_irq;
> > + if (riscv_timer_cant_wake_cpu)
> > + ce->features |= CLOCK_EVT_FEAT_C3STOP;
> > clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
> >
> > enable_percpu_irq(riscv_clock_event_irq,
> > @@ -139,6 +142,13 @@ static int __init riscv_timer_init_dt(struct device_node *n)
> > if (cpuid != smp_processor_id())
> > return 0;
> >
> > + child = of_find_compatible_node(NULL, NULL, "riscv,timer");
> > + if (child) {
> > + riscv_timer_cant_wake_cpu = of_property_read_bool(child,
> > + "riscv,timer-cant-wake-cpu");
> > + of_node_put(child);
> > + }
> > +
> > domain = NULL;
> > child = of_get_compatible_child(n, "riscv,cpu-intc");
> > if (!child) {
Anyway, the mechanics of the change here look good to me. The re-use of
child is understandable but a little odd though, since riscv,timer /is
not/ actually a child. That's relatively minor thing to change though.
I'm still not happy about turning on C3STOP when we have not figured out
why it's breaking timer behaviour, but I think that's the lessor of two
evils. Somewhat reluctantly:
Reviewed-by: Conor Dooley <[email protected]>
I'll try to spend some time looking into why it's broken.
Thanks,
Conor.
On Fri, Nov 25, 2022 at 07:18:48PM +0530, Anup Patel wrote:
> On Fri, Nov 25, 2022 at 6:40 PM Conor Dooley <[email protected]> wrote:
> >
> > Hey Anup,
> >
> > For the future, could you please CC me on all patches in a series that I
> > have previously reviewed?
>
> Okay.
>
> >
> > On Fri, Nov 25, 2022 at 04:51:04PM +0530, Anup Patel wrote:
> > > We add DT bindings for a separate RISC-V timer DT node which can
> > > be used to describe implementation specific behaviour (such as
> > > timer interrupt not triggered during non-retentive suspend).
> > >
> > > Signed-off-by: Anup Patel <[email protected]>
> > > ---
> > > .../bindings/timer/riscv,timer.yaml | 52 +++++++++++++++++++
> > > 1 file changed, 52 insertions(+)
> > > create mode 100644 Documentation/devicetree/bindings/timer/riscv,timer.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/timer/riscv,timer.yaml b/Documentation/devicetree/bindings/timer/riscv,timer.yaml
> > > new file mode 100644
> > > index 000000000000..cf53dfff90bc
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/timer/riscv,timer.yaml
> > > @@ -0,0 +1,52 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/timer/riscv,timer.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: RISC-V timer
> > > +
> > > +maintainers:
> > > + - Anup Patel <[email protected]>
> > > +
> > > +description: |+
> > > + RISC-V platforms always have a RISC-V timer device for the supervisor-mode
> > > + based on the time CSR defined by the RISC-V privileged specification. The
> > > + timer interrupts of this device are configured using the RISC-V SBI Time
> > > + extension or the RISC-V Sstc extension.
> > > +
> > > + The clock frequency of RISC-V timer device is specified via the
> > > + "timebase-frequency" DT property of "/cpus" DT node which is described
> > > + in Documentation/devicetree/bindings/riscv/cpus.yaml
> > > +
> > > +properties:
> > > + compatible:
> > > + enum:
> > > + - riscv,timer
> > > +
> > > + interrupts-extended:
> > > + minItems: 1
> > > + maxItems: 4096 # Should be enough?
> > > +
> > > + riscv,timer-cant-wake-cpu:
> > > + type: boolean
> > > + description:
> > > + If present, the timer interrupt can't wake up the CPU from
> > > + suspend/idle state.
> >
> > I'm really not sure about this... I would be inclined to think that if
> > someone does not specify then we should assume that they took the
> > scroogiest view of the spec and so do not get events during suspend.
> >
> > I suppose you could then argue that their DT is wrong & it's their fault
> > though. Plus the existing platforms behave this way & we avoid having to
> > retrofit stuff here.
>
> Yes, the DT property is defined to keep things working for
> existing platforms.
>
> IMO, people should always read the DT bindings document at time of
> creating DT for their platform. If there are queries then they can always
> shoot email to the maintainers on LKML.
Aye, I suppose so. For every platform that may exist that this change
hurts, there's likely another one that it fixes a timer for... /shrug
Binding itself looks grand though & we are in lessor of two evils
territory, so:
Reviewed-by: Conor Dooley <[email protected]>
Thanks for turning around a v3 promptly Anup!
Conor.
> > > +
> > > +additionalProperties: false
> > > +
> > > +required:
> > > + - compatible
> > > + - interrupts-extended
> > > +
> > > +examples:
> > > + - |
> > > + timer {
> > > + compatible = "riscv,timer";
> > > + interrupts-extended = <&cpu1intc 5>,
> > > + <&cpu2intc 5>,
> > > + <&cpu3intc 5>,
> > > + <&cpu4intc 5>;
> > > + };
> > > +...
> > > --
> > > 2.34.1
> > >
>
> Regards,
> Anup
Hey all,
On Fri, Nov 25, 2022 at 11:44:01PM +0000, Conor Dooley wrote:
> On Fri, Nov 25, 2022 at 01:13:04PM +0000, Conor Dooley wrote:
> > On Fri, Nov 25, 2022 at 04:51:05PM +0530, Anup Patel wrote:
> > > We should set CLOCK_EVT_FEAT_C3STOP for a clock_event_device only
> > > when riscv,timer-cant-wake-up DT property is present in the RISC-V
> > > timer DT node.
> > >
> > > This way CLOCK_EVT_FEAT_C3STOP feature is set for clock_event_device
> > > based on RISC-V platform capabilities rather than having it set for
> > > all RISC-V platforms.
> >
> > I need to go do some testing on what setting the C3STOP flag does on
> > platforms other than PolarFire SoC. I'm not sure that we should be
> > enabling this flag *at all* until we know that it does not break on
> > other platforms too.
>
> I tried my fu540 & fu740 - both of those seem to exhibit broken timer
> behaviour with C3STOP set. Ethernet doesn't work upstream on the
> VisionFive, so I didn't go through the hassle of testing that - but I
> would imagine it is the same as the fu740. Whenever I get a VisionFive 2
> I'll give that a try too.
>
> I did try the D1 (thanks for fielding my dumb questions Samuel) but I
> was not able to get the thing to boot if I disabled the sunxi timer :/
> Ethernet would not come up in U-Boot, clearly I did something not
> right..
>
> Obviously we need to fix things & get it backported etc, so taking a
> pragmatic approach: I think that it is better to merge this stuff even
> though it there's a pretty good chance I think that it'll break the
> SBI timer on a D1, since it is not intended that it will be used.
>
> It does make me worried about some of the other platforms though, like
> that Bouffalolabs SoC that Jisheng sent in a DT for. It's also using
> thead stuff so I wonder if it needs C3STOP too. I've added Jisheng to
> CC :)
>
> > > Signed-off-by: Anup Patel <[email protected]>
> > > ---
> > > drivers/clocksource/timer-riscv.c | 10 ++++++++++
> > > 1 file changed, 10 insertions(+)
> > >
> > > diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> > > index a0d66fabf073..0c8bdd168a45 100644
> > > --- a/drivers/clocksource/timer-riscv.c
> > > +++ b/drivers/clocksource/timer-riscv.c
> > > @@ -28,6 +28,7 @@
> > > #include <asm/timex.h>
> > >
> > > static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
> > > +static bool riscv_timer_cant_wake_cpu;
> > >
> > > static int riscv_clock_next_event(unsigned long delta,
> > > struct clock_event_device *ce)
> > > @@ -85,6 +86,8 @@ static int riscv_timer_starting_cpu(unsigned int cpu)
> > >
> > > ce->cpumask = cpumask_of(cpu);
> > > ce->irq = riscv_clock_event_irq;
> > > + if (riscv_timer_cant_wake_cpu)
> > > + ce->features |= CLOCK_EVT_FEAT_C3STOP;
> > > clockevents_config_and_register(ce, riscv_timebase, 100, 0x7fffffff);
> > >
> > > enable_percpu_irq(riscv_clock_event_irq,
> > > @@ -139,6 +142,13 @@ static int __init riscv_timer_init_dt(struct device_node *n)
> > > if (cpuid != smp_processor_id())
> > > return 0;
> > >
> > > + child = of_find_compatible_node(NULL, NULL, "riscv,timer");
> > > + if (child) {
> > > + riscv_timer_cant_wake_cpu = of_property_read_bool(child,
> > > + "riscv,timer-cant-wake-cpu");
> > > + of_node_put(child);
> > > + }
> > > +
> > > domain = NULL;
> > > child = of_get_compatible_child(n, "riscv,cpu-intc");
> > > if (!child) {
>
> Anyway, the mechanics of the change here look good to me. The re-use of
> child is understandable but a little odd though, since riscv,timer /is
> not/ actually a child. That's relatively minor thing to change though.
>
> I'm still not happy about turning on C3STOP when we have not figured out
> why it's breaking timer behaviour, but I think that's the lessor of two
> evils. Somewhat reluctantly:
> Reviewed-by: Conor Dooley <[email protected]>
>
> I'll try to spend some time looking into why it's broken.
Right, so some good news! After Samuel provided me with an openSBI setup
to actually test that timer & C3STOP is currently breaking the timers on
the D1 too! IOW the same timer durations are rounded up to the next
jiffy. He then suggested the fix for it too, see below the scissors :)
I think the revert in patch 1 is still needed (to preserve suspend
functionality for existing platforms) but the commit message needs to be
changed.
Perhaps, it should become:
> From: Conor Dooley <[email protected]>
>
> This reverts commit 232ccac1bd9b5bfe73895f527c08623e7fa0752d.
>
> On the subject of suspend, the RISC-V SBI spec states:
> > Request the SBI implementation to put the calling hart in a platform
> > specific suspend (or low power) state specified by the suspend_type
> > parameter. The hart will automatically come out of suspended state and
> > resume normal execution when it receives an interrupt or platform
> > specific hardware event.
>
> This does not cover whether any given events actually reach the hart or
> not, just what the hart will do if it receives an event. On PolarFire
> SoC, and potentially other SiFive based implementations, events from the
> RISC-V timer do reach a hart during suspend. This is not the case for
> the implementation on the Allwinner D1 - there timer events are not
> received during suspend.
>
> To prevent a device from entering an unrecoverable sleep state, the
> C3STOP feature was enabled unconditionally for the RISC-V timer driver.
> Unfortunately, this will have disabled sleep states used by existing
> platforms.
>
> Fortunately, the D1 has a second timer, which is "currently used in
> preference to the RISC-V/SBI timer driver" so a revert here does not
> hurt operation of D1 in its current form.
>
> Ultimately, a DeviceTree property (or node) will be added to encode the
> behaviour of the timers, but until then revert the addition of
> CLOCK_EVT_FEAT_C3STOP.
>
> Link: https://github.com/riscv-non-isa/riscv-sbi-doc/issues/98/
> Link: https://lore.kernel.org/linux-riscv/[email protected]/
> Fixes: 232ccac1bd9b ("clocksource/drivers/riscv: Events are stopped during CPU suspend")
> CC: Samuel Holland <[email protected]>
> CC: Anup Patel <[email protected]>
> CC: Palmer Dabbelt <[email protected]>
> Reviewed-by: Palmer Dabbelt <[email protected]>
> Acked-by: Palmer Dabbelt <[email protected]>
> Acked-by: Samuel Holland <[email protected]>
> Signed-off-by: Conor Dooley <[email protected]>
> Signed-off-by: Anup Patel <[email protected]>
Anyways, I think the new order of the patchset would have the below as
patch 1 & the current series on top of that. With those changes, I am
happy with the series & thanks for your (plural) help in figuring all of
this out!
Thanks,
Conor.
-- >8 --
From aaf20926a7645394eab4c4ad934e7f8c55e25981 Mon Sep 17 00:00:00 2001
From: Conor Dooley <[email protected]>
Date: Sat, 26 Nov 2022 14:19:44 +0000
Subject: [PATCH] RISC-V: time: initialize broadcast hrtimer based clock event
device
Similarly to commit 022eb8ae8b5e ("ARM: 8938/1: kernel: initialize
broadcast hrtimer based clock event device"), RISC-V needs to initiate
hrtimers before C3STOP can be used. Otherwise, the introduction of C3STOP
for the RISC-V arch timer in commit 232ccac1bd9b
("clocksource/drivers/riscv: Events are stopped during CPU suspend")
breaks timer behaviour, for example clock_nanosleep().
A test app that sleeps each cpu for 6, 5, 4, 3 ms respectively, HZ=250
& C3STOP enabled, the sleep times are rounded up to the next jiffy:
== CPU: 1 == == CPU: 2 == == CPU: 3 == == CPU: 4 ==
Mean: 7.974992 Mean: 7.976534 Mean: 7.962591 Mean: 3.952179
Std Dev: 0.154374 Std Dev: 0.156082 Std Dev: 0.171018 Std Dev: 0.076193
Hi: 9.472000 Hi: 10.495000 Hi: 8.864000 Hi: 4.736000
Lo: 6.087000 Lo: 6.380000 Lo: 4.872000 Lo: 3.403000
Samples: 521 Samples: 521 Samples: 521 Samples: 521
Link: https://lore.kernel.org/linux-riscv/YzYTNQRxLr7Q9JR0@spud/
Fixes: 232ccac1bd9b ("clocksource/drivers/riscv: Events are stopped during CPU suspend")
Suggested-by: Samuel Holland <[email protected]>
Signed-off-by: Conor Dooley <[email protected]>
---
arch/riscv/kernel/time.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/riscv/kernel/time.c b/arch/riscv/kernel/time.c
index 8217b0f67c6c..1cf21db4fcc7 100644
--- a/arch/riscv/kernel/time.c
+++ b/arch/riscv/kernel/time.c
@@ -5,6 +5,7 @@
*/
#include <linux/of_clk.h>
+#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/delay.h>
#include <asm/sbi.h>
@@ -29,6 +30,8 @@ void __init time_init(void)
of_clk_init(NULL);
timer_probe();
+
+ tick_setup_hrtimer_broadcast();
}
void clocksource_arch_init(struct clocksource *cs)
--
2.38.1