2022-12-12 07:17:39

by Ira Weiny

Subject: [PATCH V4 1/9] PCI/CXL: Export native CXL error reporting control

From: Ira Weiny <[email protected]>

CXL _OSC Error Reporting Control is used by the OS to determine if
Firmware has control of various CXL error reporting capabilities
including the event logs.

Expose the result of negotiating CXL Error Reporting Control in struct
pci_host_bridge for consumption by the CXL drivers.

Cc: Bjorn Helgaas <[email protected]>
Cc: Lukas Wunner <[email protected]>
Cc: [email protected]
Cc: [email protected]
Signed-off-by: Ira Weiny <[email protected]>

---
Changes from V3:
New patch split out
---
drivers/acpi/pci_root.c | 3 +++
drivers/pci/probe.c | 1 +
include/linux/pci.h | 1 +
3 files changed, 5 insertions(+)

diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
index b3c202d2a433..84030804a763 100644
--- a/drivers/acpi/pci_root.c
+++ b/drivers/acpi/pci_root.c
@@ -1047,6 +1047,9 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root,
if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL))
host_bridge->native_dpc = 0;

+ if (!(root->osc_ext_control_set & OSC_CXL_ERROR_REPORTING_CONTROL))
+ host_bridge->native_cxl_error = 0;
+
/*
* Evaluate the "PCI Boot Configuration" _DSM Function. If it
* exists and returns 0, we must preserve any PCI resource
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 2f4e88a44e8b..34c9fd6840c4 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -596,6 +596,7 @@ static void pci_init_host_bridge(struct pci_host_bridge *bridge)
bridge->native_ltr = 1;
bridge->native_dpc = 1;
bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET;
+ bridge->native_cxl_error = 1;

device_initialize(&bridge->dev);
}
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 1f81807492ef..08c3ccd2617b 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -577,6 +577,7 @@ struct pci_host_bridge {
unsigned int native_pme:1; /* OS may use PCIe PME */
unsigned int native_ltr:1; /* OS may use PCIe LTR */
unsigned int native_dpc:1; /* OS may use PCIe DPC */
+ unsigned int native_cxl_error:1; /* OS may use CXL RAS/Events */
unsigned int preserve_config:1; /* Preserve FW resource setup */
unsigned int size_windows:1; /* Enable root bus sizing */
unsigned int msi_domain:1; /* Bridge wants MSI domain */
--
2.37.2

2022-12-13 19:48:01

by Dan Williams

Subject: RE: [PATCH V4 1/9] PCI/CXL: Export native CXL error reporting control

ira.weiny@ wrote:
> From: Ira Weiny <[email protected]>
>
> CXL _OSC Error Reporting Control is used by the OS to determine if
> Firmware has control of various CXL error reporting capabilities
> including the event logs.
>
> Expose the result of negotiating CXL Error Reporting Control in struct
> pci_host_bridge for consumption by the CXL drivers.
>
> Cc: Bjorn Helgaas <[email protected]>
> Cc: Lukas Wunner <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Signed-off-by: Ira Weiny <[email protected]>

Looks good to me,

Reviewed-by: Dan Williams <[email protected]>

>
> ---
> Changes from V3:
> New patch split out
> ---
> drivers/acpi/pci_root.c | 3 +++
> drivers/pci/probe.c | 1 +
> include/linux/pci.h | 1 +
> 3 files changed, 5 insertions(+)
>
> diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
> index b3c202d2a433..84030804a763 100644
> --- a/drivers/acpi/pci_root.c
> +++ b/drivers/acpi/pci_root.c
> @@ -1047,6 +1047,9 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root,
> if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL))
> host_bridge->native_dpc = 0;
>
> + if (!(root->osc_ext_control_set & OSC_CXL_ERROR_REPORTING_CONTROL))
> + host_bridge->native_cxl_error = 0;
> +
> /*
> * Evaluate the "PCI Boot Configuration" _DSM Function. If it
> * exists and returns 0, we must preserve any PCI resource
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index 2f4e88a44e8b..34c9fd6840c4 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -596,6 +596,7 @@ static void pci_init_host_bridge(struct pci_host_bridge *bridge)
> bridge->native_ltr = 1;
> bridge->native_dpc = 1;
> bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET;
> + bridge->native_cxl_error = 1;
>
> device_initialize(&bridge->dev);
> }
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 1f81807492ef..08c3ccd2617b 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -577,6 +577,7 @@ struct pci_host_bridge {
> unsigned int native_pme:1; /* OS may use PCIe PME */
> unsigned int native_ltr:1; /* OS may use PCIe LTR */
> unsigned int native_dpc:1; /* OS may use PCIe DPC */
> + unsigned int native_cxl_error:1; /* OS may use CXL RAS/Events */
> unsigned int preserve_config:1; /* Preserve FW resource setup */
> unsigned int size_windows:1; /* Enable root bus sizing */
> unsigned int msi_domain:1; /* Bridge wants MSI domain */
> --
> 2.37.2
>

2022-12-16 14:59:52

by Jonathan Cameron

Subject: Re: [PATCH V4 1/9] PCI/CXL: Export native CXL error reporting control

On Sun, 11 Dec 2022 23:06:19 -0800
[email protected] wrote:

> From: Ira Weiny <[email protected]>
>
> CXL _OSC Error Reporting Control is used by the OS to determine if
> Firmware has control of various CXL error reporting capabilities
> including the event logs.
>
> Expose the result of negotiating CXL Error Reporting Control in struct
> pci_host_bridge for consumption by the CXL drivers.
>
> Cc: Bjorn Helgaas <[email protected]>
> Cc: Lukas Wunner <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Signed-off-by: Ira Weiny <[email protected]>
>
Reviewed-by: Jonathan Cameron <[email protected]>

> ---
> Changes from V3:
> New patch split out
> ---
> drivers/acpi/pci_root.c | 3 +++
> drivers/pci/probe.c | 1 +
> include/linux/pci.h | 1 +
> 3 files changed, 5 insertions(+)
>
> diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
> index b3c202d2a433..84030804a763 100644
> --- a/drivers/acpi/pci_root.c
> +++ b/drivers/acpi/pci_root.c
> @@ -1047,6 +1047,9 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root,
> if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL))
> host_bridge->native_dpc = 0;
>
> + if (!(root->osc_ext_control_set & OSC_CXL_ERROR_REPORTING_CONTROL))
> + host_bridge->native_cxl_error = 0;
> +
> /*
> * Evaluate the "PCI Boot Configuration" _DSM Function. If it
> * exists and returns 0, we must preserve any PCI resource
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index 2f4e88a44e8b..34c9fd6840c4 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -596,6 +596,7 @@ static void pci_init_host_bridge(struct pci_host_bridge *bridge)
> bridge->native_ltr = 1;
> bridge->native_dpc = 1;
> bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET;
> + bridge->native_cxl_error = 1;
>
> device_initialize(&bridge->dev);
> }
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 1f81807492ef..08c3ccd2617b 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -577,6 +577,7 @@ struct pci_host_bridge {
> unsigned int native_pme:1; /* OS may use PCIe PME */
> unsigned int native_ltr:1; /* OS may use PCIe LTR */
> unsigned int native_dpc:1; /* OS may use PCIe DPC */
> + unsigned int native_cxl_error:1; /* OS may use CXL RAS/Events */
> unsigned int preserve_config:1; /* Preserve FW resource setup */
> unsigned int size_windows:1; /* Enable root bus sizing */
> unsigned int msi_domain:1; /* Bridge wants MSI domain */

2023-01-05 03:45:38

by Ira Weiny

Subject: Re: [PATCH V4 1/9] PCI/CXL: Export native CXL error reporting control

On Sun, Dec 11, 2022 at 11:06:19PM -0800, Ira wrote:
> From: Ira Weiny <[email protected]>
>
> CXL _OSC Error Reporting Control is used by the OS to determine if
> Firmware has control of various CXL error reporting capabilities
> including the event logs.
>
> Expose the result of negotiating CXL Error Reporting Control in struct
> pci_host_bridge for consumption by the CXL drivers.
>

Rafael,

I should have CC'ed you on this patch. Could I get an ack on it so Dan can
take it through the CXL tree?

Thanks,
Ira

> Cc: Bjorn Helgaas <[email protected]>
> Cc: Lukas Wunner <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Signed-off-by: Ira Weiny <[email protected]>
>
> ---
> Changes from V3:
> New patch split out
> ---
> drivers/acpi/pci_root.c | 3 +++
> drivers/pci/probe.c | 1 +
> include/linux/pci.h | 1 +
> 3 files changed, 5 insertions(+)
>
> diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
> index b3c202d2a433..84030804a763 100644
> --- a/drivers/acpi/pci_root.c
> +++ b/drivers/acpi/pci_root.c
> @@ -1047,6 +1047,9 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root,
> if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL))
> host_bridge->native_dpc = 0;
>
> + if (!(root->osc_ext_control_set & OSC_CXL_ERROR_REPORTING_CONTROL))
> + host_bridge->native_cxl_error = 0;
> +
> /*
> * Evaluate the "PCI Boot Configuration" _DSM Function. If it
> * exists and returns 0, we must preserve any PCI resource
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index 2f4e88a44e8b..34c9fd6840c4 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -596,6 +596,7 @@ static void pci_init_host_bridge(struct pci_host_bridge *bridge)
> bridge->native_ltr = 1;
> bridge->native_dpc = 1;
> bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET;
> + bridge->native_cxl_error = 1;
>
> device_initialize(&bridge->dev);
> }
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 1f81807492ef..08c3ccd2617b 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -577,6 +577,7 @@ struct pci_host_bridge {
> unsigned int native_pme:1; /* OS may use PCIe PME */
> unsigned int native_ltr:1; /* OS may use PCIe LTR */
> unsigned int native_dpc:1; /* OS may use PCIe DPC */
> + unsigned int native_cxl_error:1; /* OS may use CXL RAS/Events */
> unsigned int preserve_config:1; /* Preserve FW resource setup */
> unsigned int size_windows:1; /* Enable root bus sizing */
> unsigned int msi_domain:1; /* Bridge wants MSI domain */
> --
> 2.37.2
>

2023-01-05 17:10:33

by Bjorn Helgaas

Subject: Re: [PATCH V4 1/9] PCI/CXL: Export native CXL error reporting control

On Sun, Dec 11, 2022 at 11:06:19PM -0800, [email protected] wrote:
> From: Ira Weiny <[email protected]>
>
> CXL _OSC Error Reporting Control is used by the OS to determine if
> Firmware has control of various CXL error reporting capabilities
> including the event logs.
>
> Expose the result of negotiating CXL Error Reporting Control in struct
> pci_host_bridge for consumption by the CXL drivers.
>
> Cc: Bjorn Helgaas <[email protected]>
> Cc: Lukas Wunner <[email protected]>
> Cc: [email protected]
> Cc: [email protected]
> Signed-off-by: Ira Weiny <[email protected]>

FWIW, for probe.c and pci.h:

Acked-by: Bjorn Helgaas <[email protected]>

> ---
> Changes from V3:
> New patch split out
> ---
> drivers/acpi/pci_root.c | 3 +++
> drivers/pci/probe.c | 1 +
> include/linux/pci.h | 1 +
> 3 files changed, 5 insertions(+)
>
> diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
> index b3c202d2a433..84030804a763 100644
> --- a/drivers/acpi/pci_root.c
> +++ b/drivers/acpi/pci_root.c
> @@ -1047,6 +1047,9 @@ struct pci_bus *acpi_pci_root_create(struct acpi_pci_root *root,
> if (!(root->osc_control_set & OSC_PCI_EXPRESS_DPC_CONTROL))
> host_bridge->native_dpc = 0;
>
> + if (!(root->osc_ext_control_set & OSC_CXL_ERROR_REPORTING_CONTROL))
> + host_bridge->native_cxl_error = 0;
> +
> /*
> * Evaluate the "PCI Boot Configuration" _DSM Function. If it
> * exists and returns 0, we must preserve any PCI resource
> diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
> index 2f4e88a44e8b..34c9fd6840c4 100644
> --- a/drivers/pci/probe.c
> +++ b/drivers/pci/probe.c
> @@ -596,6 +596,7 @@ static void pci_init_host_bridge(struct pci_host_bridge *bridge)
> bridge->native_ltr = 1;
> bridge->native_dpc = 1;
> bridge->domain_nr = PCI_DOMAIN_NR_NOT_SET;
> + bridge->native_cxl_error = 1;
>
> device_initialize(&bridge->dev);
> }
> diff --git a/include/linux/pci.h b/include/linux/pci.h
> index 1f81807492ef..08c3ccd2617b 100644
> --- a/include/linux/pci.h
> +++ b/include/linux/pci.h
> @@ -577,6 +577,7 @@ struct pci_host_bridge {
> unsigned int native_pme:1; /* OS may use PCIe PME */
> unsigned int native_ltr:1; /* OS may use PCIe LTR */
> unsigned int native_dpc:1; /* OS may use PCIe DPC */
> + unsigned int native_cxl_error:1; /* OS may use CXL RAS/Events */
> unsigned int preserve_config:1; /* Preserve FW resource setup */
> unsigned int size_windows:1; /* Enable root bus sizing */
> unsigned int msi_domain:1; /* Bridge wants MSI domain */
> --
> 2.37.2
>